JP3253182B2 - Frequency adjustment circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a frequency adjustment circuit such as a PLL (Phase Locked Loop) circuit used in the communication field and the like.

[0002]

2. Description of the Related Art FIG. 4 is a block diagram showing a configuration example of a conventional PLL frequency synthesizer. In FIG. 4, 1
Voltage controlled oscillator of the oscillation frequency f ₁ (hereinafter, VCO (Vol
tage Control Oscillator) hereinafter), 2 is a frequency divider division ratio N1, 3 the reference oscillator of the oscillation frequency f _2, 4 is a frequency divider division ratio N2, 5 is a phase comparator, 6 low-pass filter ( Hereinafter, LPF (Low Pass Filter) is shown.

In such a configuration, the signal S ₁ of the frequency f ₁ output from the VCO ₁ is divided by the frequency divider 2 into (1 / N
Is divided into 1), it is input as a signal S ₂ to the phase comparator 5. On the other hand, the signal S ₃ of the frequency f ₂ output from the reference oscillator 3 is frequency-divided by the frequency divider 4 to (1 / N2) and input to the phase comparator 5 as the signal S ₄ .

[0004] The phase comparator 5 compares the phase of the input signal S ₄ with the signal S ₂ . The output of the phase comparator 5 includes an AC component and a DC component (error output current), and is output to the LPF 6. The value of the DC component in the phase comparator 5, depending on whether or delayed phase signal S ₂ is advanced with respect to signal S _4, the positive and negative polarity and magnitude changes.

The LPF 6 removes the AC component from the output of the phase comparator 5 and extracts only the DC component.
Will be returned to Thus, the center frequency of the output signals S ₁ of VCO1 is always follows the output signal S ₃ of the phase of the reference oscillator 3, come to satisfy the relationship shown below, VCO
1, oscillates at a frequency f ₂ to satisfy the following expression, so-called locked state. _{f 1 / N1 = f 2 /} N2 Also, the value of f ₂ by varying the division ratio N1 of the frequency divider 2, can be arbitrarily varied in the step of (f ₂ / N2).

[0006]

In the circuit described above, for example, immediately after the power is turned on and the circuit starts up, or when the division ratio N1 of the frequency divider 2 is changed, the circuit is not in the locked state. (Unlocked state), only the DC component is fed back to the VCO 1 from the LPF 6, and after a while, the locked state is established. The time required to transition from the unlocked state to the locked state (lock-up time) is determined by the capacitors C ₁ (for example, 500 pF) and C ₂ (for example, 0.2 μF) and the resistance element R ₁ (for example, 10 kΩ) which constitute the LPF 6. Determined, and in the conventional circuit described above,
It has been difficult to shorten the lock-up time for reasons such as maintaining a stable lock state. In particular, this is because the take time to charge the large capacitor C ₂ of the capacitor.

The present invention has been made in view of such circumstances, and an object of the present invention is to provide a frequency adjustment circuit capable of shortening a lock-up time.

[0008]

To achieve the above object, a frequency adjustment circuit according to the present invention is a frequency adjustment circuit for adjusting the frequency by causing the oscillation frequency of a voltage controlled oscillator to follow the frequency of a reference signal. A phase comparator for detecting a phase difference between an output signal of the voltage controlled oscillator and the reference signal, a first capacitor connected between an output of the phase comparator and a reference potential, and a phase comparator. A DC component corresponding to an output signal of the phase comparator includes a resistance element having one terminal connected to the output and a second capacitor connected between the other terminal of the resistance element and a reference potential. A filter that feeds back to the voltage controlled oscillator; and a boost circuit that obtains an integrated value of a voltage waveform appearing at both ends of the resistance element and accumulates a charge proportional to the integrated value in the second capacitor.

[0009]

According to the present invention, for example, immediately after the start of the circuit, the phase comparator compares the phase with the output signal of the voltage controlled oscillator with reference to the reference signal, and outputs the error output current as a DC component. The included signal is output to the filter.
The value of the DC component in the phase comparator changes in positive / negative polarity and magnitude depending on whether the phase of the output signal of the voltage controlled oscillator advances or lags with respect to the reference signal. In the filter, only the DC component is extracted from the output of the phase comparator and is fed back to the voltage controlled oscillator. At this time, in the filter, the input error output current is accumulated in the first capacitor, and the charge is transferred to the second capacitor with a time constant determined by the capacitance of the first capacitor and the resistance value of the resistance element. You. At this time, at both ends of the resistance element,
A predetermined voltage waveform appears.

[0010] The voltage waveform appearing at both ends of the resistance element of the filter is input to the boost circuit, and its integral value is obtained. The charge corresponding to this integral value is accumulated in the second capacitor of the filter. As a result, the second capacitor is rapidly charged, and the voltage-controlled oscillator quickly transitions from the unlocked state to the locked state.

[0011]

FIG. 1 is a block diagram showing an embodiment of a PLL frequency synthesizer as a frequency adjusting circuit according to the present invention. In FIG. 1, the same components as those in FIG. That is, 1 VCO, 2 is a frequency divider division ratio N1, the reference oscillator of the oscillation frequency f ₂ 3, 4
Is a frequency divider having a frequency dividing ratio N2, 5 is a phase comparator, 6 is an LPF,
Reference numeral 7 denotes a boost circuit.

The boost circuit 7 includes a voltage-current converter VI
C, comparators CMP1 and CMP2, diode bridge D
B, the switching elements SW1, SW2, and is constituted by a capacitor C _3, a constant current source I _e1 ~I _e4 and the constant voltage source V ₁ ~V _3. These elements are connected as follows.

One input (+) of the voltage-current converter VIC is
Resistor R of LPF6₁Between one end of VCO1 and the input of VCO1
The other input (-) is connected to the resistor element of LPF6.
Child R ₁The other end and capacitor C_TwoConnected to the midpoint of the connection
ing. The output of the voltage-current converter VIC is
Ridge DB diode D₁Cathode and diode
D_TwoOf the comparator CMP1
Connected to the positive input and the negative input of comparator CMP2, respectively.
Have been. Also, the output of the voltage-current converter VIC and the ground
Capacitor C between_ThreeIs connected.

The diode D _{1 of the} diode bridge DB
Connection point between the anode of the anode and the diode D ₃ is connected to the constant current source I _e2, the constant current source I _e2 power supply voltage V _CC
It is connected to the. Connection point between the cathode of the cathode and the diode D ₄ of the diode bridge DB diode D ₂ is connected to the constant current source I _e1, the constant current source I _e1 is grounded. Connection point between the anode of the cathode and the diode D ₄ of the diode D ₃ of the diode bridge DB together with being connected to the negative input of the comparator CMP1 via the constant voltage source V _2, via a constant voltage source V ₃ Comparator CMP2
Is connected to the positive input. The constant voltage source V ₁ is connected between ground and the connection point between the anode of the cathode and the diode D ₄ of the diode D _3. Comparator CMP1
Is connected to the control terminal of the switching element SW2, and the output of the comparator CMP2 is connected to the control terminal of the switching element SW1.

The stationary contact points of the switching elements SW1 and SW2 are connected, these connection point is connected to the connection point between the other end and the capacitor C ₂ of the resistance element R ₁ of LPF 6. The movable contact of the switching element SW1 is connected to the constant current source I _e3, the constant current source I _e3 are grounded. The movable contact of the switching element SW2 is a constant current source I _e4
It is connected to the constant current source I _e4 is connected to the power supply voltage V _CC. The constant current sources I _e3 and I _e4 are, for example, 60
Provides a current of μA.

Next, the operation of the above configuration will be described. For example, immediately after the start-up of the circuit, the signal S ₁ of the frequency f ₁ output from the VCO ₁ is divided by the frequency divider 2 into (1 / N
Is divided into 1), it is input as a signal S ₂ to the phase comparator 5. On the other hand, the signal S ₃ of the frequency f ₂ output from the reference oscillator 3 is frequency-divided by the frequency divider 4 to (1 / N2) and input to the phase comparator 5 as the signal S ₄ .

The phase comparator 5 compares the phase of the signal S ₂ with the signal S ₂ with reference to the input signal S _4, and outputs a signal including an error output current as a DC component to the LPF 6. In addition,
The value of the DC component in the phase comparator 5, depending on whether or delayed phase signal S ₂ is advanced with respect to signal S _4, the positive and negative polarity and magnitude changes. In the LPF 6, the phase comparator 5
, The AC component is removed from the output, only the DC component is extracted, and the output is fed back to the VCO 1. At this time, the center frequency of the output signal S ₁ of the VCO ₁ always follows the phase of the output signal S ₃ of the reference oscillator 3 by the operation of the boost circuit 70 as described below, and the VCO ₁ is quickly locked.

[0018] That is, the LPF 6, the input error output current is accumulated in the capacitor _{C 1, (R 1V · C} 1V)
Its charge with a time constant determined by is moved to the capacitor C _2. Here, R _1V is the resistance value of the resistance element R ₁ ,
C _1V indicates the capacitance of the capacitor C ₁ . At this time, the both ends of the resistance element R _1, appears a voltage waveform as shown in FIG. 1 reference numeral a. The voltage signal a is a voltage / current conversion in the voltage-current converter VIC boost circuit 7, the charge is accumulated in the capacitor C _3. Voltage generated in the capacitor C ₃ is applied to the negative input of the positive input and the comparator CMP2 of the comparator CMP1. Also, the voltage flows as a current through the diode bridge DB,
Through a constant voltage source V ₁ ~V ₃ is applied to the positive input of the negative input and a comparator CMP2 of the comparator CMP1.

The potential of the capacitor C _3, since the flow as current through the diode bridge DB as described above, as the waveform as shown in FIG. 1, reference numeral c After a while, the flow returns to the original potential. In the time from the voltage generation of the capacitor C ₃ to return to the original potential, one of the outputs of the comparators CMP1, CMP2 goes high, is outputted to the control terminal of the switching element SW2 or SW1. Specifically, when the output pulse (charge) of the phase comparator 5 is larger on the positive side than in the normal locked state, the output of the comparator CMP1 becomes high level, and the switching element SW2 is turned on. On the other hand, when the output pulse (charge) of the phase comparator 5 is larger on the negative side than in the normal locked state, the output of the comparator CMP2 becomes high level, and the switching element SW1 is turned on.

[0020] That is, the voltage generated in the capacitor C ₃ is equal to or a certain level or more, the switching element SW1
Or SW2 is turned on, and the resistance element R
In the same direction as the direction in which the flow through _one, will be the current through the switching element SW1 or SW2 by the constant current source I _e4, I _e3 is flown against capacitor C ₂ of the LPF 6, the circuit quickly locked Operate to transition.

[0021] The time until the potential of the capacitor C ₃ is returned to the original potential, the switching element SW1 or SW
Since any of the 2 holds the on-state, the amount of charge flowing through the switching SW1 or SW2 is proportional to the amount of charge that has passed through the resistive element R _1.

Actually, a simulation was performed by constructing an equivalent circuit as shown in FIG. In the circuit of FIG.
Frequency of O1 corresponds to the output current of the voltage-current converter VIC _1, frequency divider 2 is the output current of the voltage-current converter VIC ₁ integrates via the capacitor C _4, a phase comparator 5 the switching element SW3 and the resistive element R ₂ and outputs an error as charge. Except for the VCO 1, the frequency divider 2, and the phase comparator 5, all were designed according to actual transistors. For example, a circuit equivalent to a diode bridge is represented by p
np type bipolar transistors P1, P2 and npn
It is configured using the bipolar transistors N1 and N2.

FIG. 3 is a graph showing the result of simulation by the circuit of FIG. 2. The horizontal axis represents time (ms), and the vertical axis represents level. Further, a connection point in the figure, the waveform at a connection point curve indicated by A and the capacitor C ₁ of the circuit of Figure 2 and the resistance element R _1, the curve indicated by B and the resistance element R ₁ and the capacitor C ₂ the waveform at, C is a waveform in the connection point between the output and the capacitor C ₃ of the voltage-current converter VIC, D and the output waveform of the comparator CMP1, E
Indicates the output waveform of the comparator CMP2. Note that the level of each waveform is different for each waveform, and FIG. 3 shows the levels relatively for easy understanding.

The circuit of the present invention, as can be seen from FIG.
When the phase comparison reference frequency is set to 10 kHz, the waveform at the point A rapidly approaches the convergence point about 1 ms after the rise, and can quickly transition to the locked state. By configuring the constant current sources _Ie3 and _Ie4 to change according to the signal at the point C, it is possible to more quickly and stably bring the point A closer to the convergence point.

As described above, according to this embodiment,
The voltage waveform appearing across the resistance element R ₁ of LPF6 converts voltage / current by the voltage-current converter VIC, and accumulates the charges in the capacitor C _3, a comparator a voltage generated in the result the capacitor C ₃ CMP1 and CMP2 is input to, as an on-state switching element SW1, SW2 if there is a generated voltage level or more, through the resistance element R ₁ in the same direction as the flow into the capacitor C _2, charge proportional to the amount of charge passed to R ₁ the since so as to flow accumulated in the capacitor C _2, it is possible to transition pulse (charge) is larger unlocked state output from the phase comparator 5 only, quickly locked state by operating the boost circuit. Therefore, there is an advantage that the lock-up time can be shortened, and a communication device with good responsiveness can be realized.

[0026]

As described above, according to the present invention,
There is an advantage that the lock-up time for transition from the unlocked state to the locked state such as immediately after the rise of the circuit can be reduced.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an embodiment of a PLL frequency synthesizer as a frequency adjustment circuit according to the present invention.

FIG. 2 is a diagram illustrating a configuration example of a simulation equivalent circuit.

FIG. 3 is a graph showing a simulation result by the circuit of FIG. 2;

FIG. 4 is a block diagram illustrating a configuration example of a PLL frequency synthesizer as a conventional frequency adjustment circuit.

[Explanation of symbols]

1 ... VCO 2, 4 ... divider 3 ... reference oscillator 5 ... phase comparator 6 ... LPF R ₁ ... resistance element C _1, C ₂ ... capacitor 7 ... boost circuit VIC ... voltage-current converter CMP1, CMP2 ... comparator DB ... diode bridge SW1, SW2 ... switching element C ₃ ... capacitor I _e1 ~I _e4 ... constant current source V ₁ ~V ₃ ... constant voltage source

Claims (1)

(57) [Claims] 1. A frequency adjustment circuit for adjusting the frequency by causing an oscillation frequency of a voltage controlled oscillator to follow a frequency of a reference signal, wherein a phase difference between an output signal of the voltage controlled oscillator and the reference signal is detected. A phase comparator; a first capacitor connected between the output of the phase comparator and a reference potential; a resistance element having one terminal connected to the output of the phase comparator; and the other of the resistance elements And a second capacitor connected between the terminal of the phase comparator and a filter that feeds back a DC component corresponding to an output signal of the phase comparator to the voltage controlled oscillator. Find the integral value of the voltage waveform,
A boost circuit for storing a charge proportional to the integral value in the second capacitor.