JPH07120735B2 - Semiconductor chip - Google Patents

Semiconductor chip

Info

Publication number
JPH07120735B2
JPH07120735B2 JP63209765A JP20976588A JPH07120735B2 JP H07120735 B2 JPH07120735 B2 JP H07120735B2 JP 63209765 A JP63209765 A JP 63209765A JP 20976588 A JP20976588 A JP 20976588A JP H07120735 B2 JPH07120735 B2 JP H07120735B2
Authority
JP
Japan
Prior art keywords
heat
high thermal
thermal conductive
semiconductor
semiconductor chip
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP63209765A
Other languages
Japanese (ja)
Other versions
JPH0258255A (en
Inventor
宣夫 御子柴
和夫 坪内
Original Assignee
宣夫 御子柴
和夫 坪内
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 宣夫 御子柴, 和夫 坪内 filed Critical 宣夫 御子柴
Priority to JP63209765A priority Critical patent/JPH07120735B2/en
Priority to GB8918867A priority patent/GB2222721B/en
Priority to FR8911128A priority patent/FR2636777B1/en
Priority to DE19893927866 priority patent/DE3927866A1/en
Publication of JPH0258255A publication Critical patent/JPH0258255A/en
Priority to GB9117667A priority patent/GB2246472A/en
Priority to GB9117666A priority patent/GB2246471B/en
Publication of JPH07120735B2 publication Critical patent/JPH07120735B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73251Location after the connecting process on different surfaces
    • H01L2224/73265Layer and wire connectors

Description

【発明の詳細な説明】 [産業上の利用分野] 本発明は半導体装置に係り、特に超高速、超高集積の電
子回路を実現するための半導体チップの放熱/冷却構造
に関する。
Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly to a heat dissipation / cooling structure of a semiconductor chip for realizing an electronic circuit of ultra-high speed and ultra-high integration.

[発明の概要] 高熱伝導性絶縁層を含む熱流回路によりチップ内の基板
に形成された半導体素子の発生する熱を除去するように
した半導体チップである。
[Summary of the Invention] A semiconductor chip in which heat generated by a semiconductor element formed on a substrate in a chip is removed by a heat flow circuit including a high thermal conductive insulating layer.

[従来の技術] 半導体集積回路は、超高速、超高密度の要求に従って、
年と共に集積化が進行しているが、すでに現在におい
て、高速動作のため消費電力を要する集積回路の集積度
は、放熱限界で制限されつつある。
[Prior Art] Semiconductor integrated circuits meet the requirements of ultra high speed and ultra high density.
Although the degree of integration has been increasing over the years, the degree of integration of integrated circuits that require power consumption for high-speed operation is now being limited by the heat radiation limit.

現在使われている半導体集積回路で、例えば論理回路の
一例では、1チップ当り略1500ゲート程度の集積度であ
るが、1ゲート当り略1mW程度の消費電力であるため1
チップ当り略1Wの発熱があり、この発熱量は通常の空冷
の放熱の限界に近く、今後単なる微細化技術だけによる
集積化は難しい。
In a semiconductor integrated circuit currently used, for example, in one example of a logic circuit, the degree of integration is about 1500 gates per chip, but the power consumption is about 1 mW per gate.
There is a heat generation of about 1 W per chip, and this heat generation amount is close to the limit of heat dissipation of ordinary air cooling, and it will be difficult to integrate by only simple miniaturization technology in the future.

[発明が解決しようとする課題] しかし、半導体集積回路の高性能化、高速化の要求に伴
って、1チップ当りの消費電力は急激に増加している。
消費される電力のほとんどは熱となり、この発生した熱
はチップ全体の温度を上昇させ、素子特性の劣化や信頼
性の低下を引き起こす。しかしながら、熱が発生してい
る部分は、非常に微小な動作領域であり、かつ動作速度
が非常に高速であるので、局所的、過渡的な温度の変化
が問題になる。従って従来までの静的、大領域を扱う放
熱回路では全く不十分であり、動作時の素子の過渡状態
を考えた動的、微小領域までを考慮した高速熱流回路が
必要である。
[Problems to be Solved by the Invention] However, with the demand for higher performance and higher speed of semiconductor integrated circuits, the power consumption per chip is rapidly increasing.
Most of the consumed electric power is heat, and the generated heat raises the temperature of the entire chip, causing deterioration of element characteristics and deterioration of reliability. However, the part where heat is generated is a very small operation region and the operation speed is very high, so that a local or transient temperature change becomes a problem. Therefore, the conventional heat dissipation circuit that handles static and large areas is completely inadequate, and a high-speed heat flow circuit that considers dynamic and minute areas considering the transient state of the element during operation is required.

まず、従来の半導体素子の放熱における問題点を図示す
る。
First, a problem in heat dissipation of a conventional semiconductor device will be illustrated.

第6図乃至第10図にSiを用いたMOS FET素子の従来の例
を示す。
6 to 10 show conventional examples of MOS FET devices using Si.

第6図には、従来のMOS FET素子の典型的な構造が示し
てある。構造が対称であるため1個のMOS FET素子の1/4
の部分を示してある。同図で、1は基板で、例えばp-Si
から成る。2はチャンネル、3はゲート電極で、このゲ
ート電極は例えば多結晶Siから成る。4はゲート絶縁膜
で、例えばシリコン酸化膜SiO2である。5はソース又は
ドレインで、例えばn+Siから成る。6は配線で、例えば
Alで作られている。7は絶縁層で例えばSiO2から成る。
8は絶縁層で、例えばSiO2である。この典型的な例で
は、ゲート長は、1.3μmでゲート幅は5μmである。
駆動パルス電流は、クロック周波数5MHz、パルス幅100n
secの標準的なものを使用する。
FIG. 6 shows a typical structure of a conventional MOS FET device. 1/4 of one MOS FET element because the structure is symmetrical
Is shown. In the figure, 1 is a substrate, for example, p-Si
Consists of. 2 is a channel, 3 is a gate electrode, and this gate electrode is made of, for example, polycrystalline Si. Reference numeral 4 is a gate insulating film, which is, for example, a silicon oxide film SiO 2 . Reference numeral 5 denotes a source or a drain, which is made of, for example, n + Si. 6 is wiring, for example
Made of Al. An insulating layer 7 is made of, for example, SiO 2 .
An insulating layer 8 is, for example, SiO 2 . In this typical example, the gate length is 1.3 μm and the gate width is 5 μm.
Drive pulse current, clock frequency 5MHz, pulse width 100n
Use the standard sec.

ゲート下のチャンネルは厚さ約8nmであるが、上記パル
ス電流によって、発熱レートは2.9mWでジュール熱がチ
ャンネル近傍に発生する。素子全体は、初期温度20℃
で、絶縁層8の表面は自然対流(熱伝達係数10-3W/cm2
・℃)で放熱している。
The thickness of the channel under the gate is about 8 nm, but due to the pulse current, the heat generation rate is 2.9 mW and Joule heat is generated near the channel. Initial temperature of the entire device is 20 ° C
Then, the surface of the insulating layer 8 has natural convection (heat transfer coefficient of 10 -3 W / cm 2
・ It radiates heat at (℃).

第7図に上記MOS FET素子のチャンネル周辺における温
度の時間変化を示す。パルス電流のON,OFFの変化に対応
してチャンネル周辺の温度がμmオーダーの局所的領域
で、nsecオーダーの過渡的な変化をしている。
FIG. 7 shows the time variation of the temperature around the channel of the MOS FET element. Corresponding to the ON / OFF change of the pulse current, the temperature around the channel is in a local region of the μm order and undergoes a transient change of the nsec order.

第8図に、100nsec後、つまりパルス電流を切った直後
の第10図に示したX-Y平面図の温度分布を示す。
FIG. 8 shows the temperature distribution of the XY plan view shown in FIG. 10 after 100 nsec, that is, immediately after the pulse current was cut off.

この時のチャンネル2の温度上昇は約4℃であるが、ゲ
ート絶縁膜4において深さ方向(Y方向)に約100℃/
μmという非常に大きな温度勾配が生じており、加えて
温度変化が数nsecで応答している点を考慮すると、この
結果発生する局所的過渡的な熱ストレスは非常に大きい
ものである。
The temperature rise of the channel 2 at this time is about 4 ° C., but about 100 ° C./depth in the depth direction (Y direction) in the gate insulating film
Considering that a very large temperature gradient of μm occurs and the temperature change responds in a few nanoseconds, the resulting local transient thermal stress is very large.

第9図に、110nsec後、つまりパルス電流を切って10nse
c後のX-Y平面図の温度分布を同様に示す。
In Fig. 9, after 110nsec, that is, 10nse after turning off the pulse current.
Similarly, the temperature distribution of the XY plan view after c is shown.

パルス電流が切れた後は、チャンネル近傍の温度は急激
に下がっている。このように、従来のMOS FET素子の構
造では、チャンネル近傍に、局所的、過渡的に大きな温
度変化があり、これを除去するためには、新しい熱流回
路の構造が必要である。
After the pulse current is cut off, the temperature near the channel drops sharply. As described above, in the structure of the conventional MOS FET element, a large temperature change is locally or transiently generated in the vicinity of the channel, and a new heat flow circuit structure is required to remove it.

第11図乃至第15図にSOI(Silicon on Insulator)構造
のMOS FET素子の従来の例を示す。
11 to 15 show a conventional example of a MOS FET element having an SOI (Silicon on Insulator) structure.

第11図に示すSOI構造のMOS FET素子において、9がSOI
用の絶縁層で、例えば厚さ2μmのSiO2層である。10が
SOI用の半導体活性層で、例えばp-Siで、厚さ0.3μm、
面積5×7μm2の典型的な例が示してある。他の構造は
第6図のMOS FET素子と類似している。第11図の素子に
は、第6図〜第10図の例と同様のパルス電流を流す。
In the SOI structure MOS FET element shown in FIG. 11, 9 is SOI
The insulating layer is a SiO 2 layer having a thickness of 2 μm. 10 is
A semiconductor active layer for SOI, for example p-Si, with a thickness of 0.3 μm,
A typical example with an area of 5 × 7 μm 2 is shown. The other structure is similar to the MOS FET device shown in FIG. A pulse current similar to that in the example of FIGS. 6 to 10 is passed through the element of FIG.

第12図に、上記素子におけるシリコン活性層10とチャン
ネル2の周辺における温度の時間変化を示す。やはり、
パルス電流のON,OFFの変化に対応して、チャンネル周辺
の温度が局所的、過渡的に激しく変動する。
FIG. 12 shows the time variation of the temperature around the silicon active layer 10 and the channel 2 in the above device. also,
The temperature around the channel fluctuates locally and transiently in response to changes in ON / OFF of the pulse current.

第13図に100nsec後、つまりパルス電流を切った直後の
第15図に示す部分の温度分布を示す。このSOI構造MOS F
ET素子では、上記のSi基板上のMOS FET素子よりもチャ
ンネル2周辺の温度がずっと高くなってしまう。これ
は、絶縁膜(SiO2)9の熱伝導率がSiよりも2桁程度小
さいために基板への放熱が防げられシリコン活性層10に
熱が蓄積してしまう。
FIG. 13 shows the temperature distribution of the portion shown in FIG. 15 after 100 nsec, that is, immediately after the pulse current was cut off. This SOI structure MOS F
In the ET element, the temperature around the channel 2 is much higher than that in the MOS FET element on the Si substrate. This is because the thermal conductivity of the insulating film (SiO 2 ) 9 is smaller than that of Si by about two orders of magnitude, so that heat dissipation to the substrate is prevented and heat is accumulated in the silicon active layer 10.

パルス印加後100nsecにおけるチャンネル2の温度は約3
0℃で上記のSi基板上MOS FET素子よりも約6℃高い。ま
た、ゲート絶縁膜9の幅には、Y方向に約170℃/μm
の温度勾配ができており、上記のSi基板上MOS FET素子
の場合よりも更に大きい熱ストレスが発生している。
The temperature of channel 2 is about 3 at 100nsec after pulse application.
At 0 ° C, it is about 6 ° C higher than the above MOS FET device on the Si substrate. The width of the gate insulating film 9 is about 170 ° C./μm in the Y direction.
The temperature gradient is generated, and the thermal stress is larger than that of the above-mentioned MOS FET device on Si substrate.

第14図に、150nsec後、つまりパルス電流を切って50nse
c後の、やはり第15図に示すX-Y平面部分の温度分布を示
す。上記の第10図に比較すると、熱が残ってしまう。
Fig. 14 shows that after 150nsec, that is, when the pulse current is cut off, 50nse
After c, the temperature distribution in the XY plane portion shown in FIG. 15 is also shown. Compared to FIG. 10 above, heat remains.

従って、SOI構造の場合には、絶縁層9に妨げられてSi
基板へチャンネル2から熱が逃げないので、この熱を除
去するため、さらに新しい熱流回路の構造が必要であ
る。
Therefore, in the case of the SOI structure, Si is blocked by the insulating layer 9.
Since heat does not escape from the channels 2 to the substrate, a new heat flow circuit structure is needed to remove this heat.

[発明の目的] 本発明の目的は1個以上の半導体素子を内蔵する半導体
チップ全体にわたって過渡的かつ局所的な熱の除去を可
能にすることにある。
[Object of the Invention] It is an object of the present invention to enable transient and local heat removal over the entire semiconductor chip containing one or more semiconductor elements.

[課題を解決するための手段] 本発明の半導体チップは上記目的を達成するため、基板
に形成された1個以上の半導体素子と、該素子上に形成
された絶縁層から成るチップにおいて、該絶縁層に少な
くとも上記半導体素子近傍に至るように設けられたスル
ーホールに高熱伝導性絶縁膜を形成し、該半導体素子が
発生する熱を上記高熱伝導性絶縁膜を含む熱流回路によ
り除去するように構成することを要旨とする。
[Means for Solving the Problems] In order to achieve the above-mentioned object, a semiconductor chip of the present invention is a chip including one or more semiconductor elements formed on a substrate and an insulating layer formed on the element. A high thermal conductive insulating film is formed in a through hole provided at least near the semiconductor element in the insulating layer, and heat generated by the semiconductor element is removed by a heat flow circuit including the high thermal conductive insulating film. The point is to configure.

[作用] チップ内で半導体素子の発熱で、過渡的、局所的に温度
上昇があっても、上記スルーホールに形成した高熱伝導
性絶縁膜を含む熱流回路により速やかに除去する。
[Operation] Even if the temperature of the semiconductor element rises transiently or locally due to heat generation of the semiconductor element in the chip, it is promptly removed by the heat flow circuit including the high thermal conductive insulating film formed in the through hole.

[実施例] 以下、図面に示す実施例を参照して本発明を説明する
と、第1図はチップ全体にわたる局所、過渡的熱流回
路、として平面型熱流回路の一実施例を示す。同図にお
いて基板14に発熱素子15が形成され、その上をカバーす
るように高熱伝導性絶縁層16が設けられている。基板14
は、Si,GaAs,InP,Al2O3など発熱素子15を形成するのに
適したものであれば何でもよい。この場合、発熱素子15
は、MOS型トランジスタ、パイポーラ型トランジスタ、
半導体レーザ、発光ダイオードなどの半導体素子の何で
あってもよく、要するに局所的、過渡的発熱源の性質を
もったもの何でも良い。
Embodiments The present invention will be described below with reference to the embodiments shown in the drawings. FIG. 1 shows an embodiment of a planar heat flow circuit as a local or transient heat flow circuit over the entire chip. In the figure, a heating element 15 is formed on a substrate 14, and a high thermal conductive insulating layer 16 is provided so as to cover the heating element 15. Board 14
May be Si, GaAs, InP, Al 2 O 3 , or any other material suitable for forming the heating element 15. In this case, the heating element 15
Is a MOS transistor, bipolar transistor,
It may be any semiconductor element such as a semiconductor laser or a light emitting diode, that is, any element having a property of a local or transient heat source.

高熱伝導性絶縁層16は、金属なみの熱伝導率をもち、か
つ絶縁体であれば何でも良いが、例えばAlN,BNなどが良
い。上記絶縁層16を含む平面型熱流回路によって、発熱
素子15の周辺で発生した局所的、過渡的に変動する熱は
平均化され、熱ストレスがなくなると同時に図示してい
ないが層16の上に設けられた放熱回路又は冷却回路によ
って熱がチップ全体に拡がる前に効率よく外部へ放出さ
れる。
The high thermal conductive insulating layer 16 may be made of any material as long as it has a thermal conductivity similar to that of a metal and is an insulating material, such as AlN or BN. Due to the planar heat flow circuit including the insulating layer 16, the locally and transiently fluctuating heat generated around the heating element 15 is averaged, and the thermal stress is eliminated and at the same time, although not shown, on the layer 16. The heat dissipation circuit or the cooling circuit provided allows the heat to be efficiently released to the outside before spreading to the entire chip.

なお、上記の手法は発熱素子又は半導体チップが3次元
的多層構造のものでも適用できる。
The above method can be applied even if the heating element or the semiconductor chip has a three-dimensional multilayer structure.

第2図は、金属配線併合熱流回路とよぶ実施例であり、
14,15は第2図と同様の基板、発熱素子である。発熱素
子15の周辺で発生した局所的、過渡的に変動する熱は、
金属配線17によって吸い出される。18は絶縁層で、これ
も高熱伝導性絶縁層で形成するのが望ましいが、通常は
SiO2などの絶縁層で作られている。従ってこの場合金属
配線17で発熱素子15から熱を吸い上げ、高熱伝導性絶縁
層16で平均化され、さらに図示していないのが層16の上
に設けられた放熱回路又は冷却回路によって熱が効率よ
く外部へ放出される。
FIG. 2 shows an embodiment called a metal wiring combined heat flow circuit,
Reference numerals 14 and 15 denote substrates and heating elements similar to those shown in FIG. The locally and transiently fluctuating heat generated around the heating element 15 is
It is sucked out by the metal wiring 17. 18 is an insulating layer, which is also preferably formed of a high thermal conductive insulating layer, but usually
It is made of an insulating layer such as SiO 2 . Therefore, in this case, the metal wiring 17 absorbs heat from the heat-generating element 15 and is averaged by the high thermal conductive insulating layer 16, and the heat is efficiently generated by the heat radiation circuit or the cooling circuit (not shown) provided on the layer 16. It is often released to the outside.

第3図は、スルーホール型熱流回路とよぶ実施例であ
る。基板14に、目的に応じた発熱する半導体素子が形成
される。基板14は、Si,GaAs,InP,Al2O3,SiO2など、発熱
素子15を形成するのに適したものであれば何でもよい。
この場合、発熱素子15は、MOS型トランジスタ、バイポ
ーラ型トランジスタ、半導体レーザ、発光ダイオードな
ど何であってもよく、要するに局所的、過渡的発熱源の
性質をもったもの何でも良い。
FIG. 3 shows an embodiment called a through-hole type heat flow circuit. Semiconductor elements that generate heat according to the purpose are formed on the substrate 14. The substrate 14 may be made of Si, GaAs, InP, Al 2 O 3 , SiO 2 , or any other material suitable for forming the heating element 15.
In this case, the heat generating element 15 may be any of a MOS type transistor, a bipolar type transistor, a semiconductor laser, a light emitting diode, etc., that is, any one having a property of a local or transient heat source.

第1図の実施例では、平面型に熱流回路をすぐに形成で
きたが、通常、多層配線、メサ構造などがあって発熱素
子の周辺は凹凸で直ちに平面的な高熱伝導膜を形成でき
るものではない。
In the embodiment shown in FIG. 1, the heat flow circuit could be immediately formed in a flat type, but normally, there are multilayer wiring, a mesa structure, etc., and the periphery of the heating element can be immediately formed with a flat and high thermal conductive film. is not.

従って、本実施例では、第3図に示すように絶縁層18に
スルーホールを発熱素子近くまで開け、高熱伝導性膜19
を形成する。高熱伝導性膜19は、発熱素子15の電気的特
性を阻害しなければ金属でもよい。通常、膜19は高熱伝
導性膜で形成する方が設計しやすく、また発熱素子15に
直接触れる構造でもよい。高熱伝導性絶縁膜19とは、例
えばAlN,BNなどである。
Therefore, in this embodiment, as shown in FIG. 3, through holes are formed in the insulating layer 18 up to the vicinity of the heating element, and the high thermal conductive film 19 is formed.
To form. The high thermal conductive film 19 may be made of metal as long as it does not hinder the electrical characteristics of the heating element 15. Usually, the film 19 is easier to design if it is formed of a high thermal conductivity film, and may have a structure in which it directly contacts the heating element 15. The high thermal conductive insulating film 19 is, for example, AlN, BN or the like.

第3図の例では、さらに基板側にスルーホールが開けら
れ、高熱伝導性膜20が形成されており、基板側からも熱
を取る工夫がなされているが、スルーホール型熱流回路
19又は20は各々一方のみであっても効果がある。
In the example of FIG. 3, a through hole is further opened on the substrate side and the high thermal conductive film 20 is formed, and the device for taking heat from the substrate side is also taken into consideration.
19 or 20 is effective even if only one of them is used.

高熱伝導性膜20は、発熱素子15の電気特性を阻害しなけ
れば金属でもよい。通常膜20は高熱伝導性絶縁膜で形成
する方が設計しやすく、また発熱素子15に直接触れる構
造でもよい。高熱伝導性絶縁膜20とは、例えばAlN,BNな
どである。
The high thermal conductive film 20 may be made of metal as long as it does not hinder the electrical characteristics of the heating element 15. Usually, the film 20 is easier to design if it is formed of a high thermal conductive insulating film, and may have a structure in which it directly contacts the heating element 15. The high thermal conductive insulating film 20 is, for example, AlN, BN or the like.

図示はしていないが、層19,20の次に設けられた放熱回
路又は冷却回路によって熱が効率よくチップ全体に拡が
る前に外へ放出される。
Although not shown, the heat dissipation circuit or cooling circuit provided next to the layers 19 and 20 allows heat to be released to the outside before being efficiently spread over the entire chip.

第4図は、空冷フィンによる放熱回路の実施例である。FIG. 4 shows an example of a heat dissipation circuit using air-cooled fins.

チップ21は、前述した熱流回路が施されたものであり、
チップ内の発熱素子としてはすでに述べたようにMOS型
トランジスタ、バイポーラ型トランジスタ、半導体レー
ザ、発光ダイオードなどの半導体素子であって、高速動
作のため、局所的、過渡的に発熱している。このチップ
21を放熱フィン24と接続するためにチップの表と裏の両
方から熱を取り去るように工夫されている。チップの一
方側は、熱伝導性の優れた接着法によって高熱伝導板22
(通常絶縁体がよく例えばAlN,BNなどである。金属で良
ければ、Al,Cu板などである)に取付けられ、放熱フィ
ン22に熱が伝えられる。チップの他方側は、高熱伝導膜
23(例えば、AlN,BN膜など)でカバーされ、高熱伝導板
26との隙間を埋めてあり、放熱フィン27に熱が伝えられ
る。
The chip 21 is provided with the heat flow circuit described above,
The heat generating element in the chip is a semiconductor element such as a MOS transistor, a bipolar transistor, a semiconductor laser, and a light emitting diode as described above, and locally or transiently generates heat because of high speed operation. This tip
It is devised to remove heat from both the front and back of the chip to connect 21 to the radiating fins 24. One side of the chip has a high thermal conductive plate 22 by an adhesive method with excellent thermal conductivity.
(The insulator is usually good, for example, AlN, BN, etc., and if it is a metal, it is an Al, Cu plate, etc.) and the heat is transferred to the radiation fin 22. High thermal conductivity film on the other side of the chip
High thermal conductive plate covered with 23 (eg AlN, BN film)
The gap with 26 is filled, and heat is transferred to the radiation fin 27.

25は取付けボードである。このようにして、チップ内に
発生した局所的、過渡的発熱は、チップの横方向に拡が
る前に外へ取り出されるので、高速動作が安定に行え
る。
25 is a mounting board. In this way, the local and transient heat generation generated in the chip is taken out before it spreads in the lateral direction of the chip, so that high-speed operation can be stably performed.

第5図は、冷却による放熱又は冷却回路の実施例であ
る。第4図の実施例と同様に21はチップ、22は高熱伝導
板、23は高熱伝導膜、24,27は放熱フィン、25は取付け
ボードである。本実施例では、冷却し、液体28は、29の
液体循環管に沿って流れる。この場合冷却用液体28は、
冷却に適したものならば何でもよいが、例えばフレオ
ン、水などが適当である。
FIG. 5 shows an embodiment of a heat radiation or cooling circuit by cooling. Similar to the embodiment of FIG. 4, 21 is a chip, 22 is a high thermal conductive plate, 23 is a high thermal conductive film, 24 and 27 are radiation fins, and 25 is a mounting board. In this embodiment, with cooling, the liquid 28 flows along the liquid circulation pipe 29. In this case, the cooling liquid 28 is
Any material suitable for cooling may be used, but freon, water, etc. are suitable.

このようにして空冷に比較してはるかに大量の熱をチッ
プから効率よく取り去ることができ、さらに安定な高速
動作が得られる。
In this way, a much larger amount of heat can be efficiently removed from the chip as compared with air cooling, and more stable high speed operation can be obtained.

[発明の効果] 以上説明した所から明らかなように本発明によれば、過
渡的に応答し、微小域からの熱を除去できる熱流回路を
半導体チップ内に設けることによって電子回路の集積度
が向上し、かつ高速動作が安定化され、実用上の効果は
多大である。
[Effects of the Invention] As is apparent from the above description, according to the present invention, a heat flow circuit capable of transiently responding and removing heat from a minute region is provided in a semiconductor chip, so that the integration degree of an electronic circuit can be improved. It is improved, the high speed operation is stabilized, and the practical effect is great.

【図面の簡単な説明】[Brief description of drawings]

第1図乃至第5図は夫々本発明の一実施例を示す概略
図、第6図乃至第10図は夫々従来のMOS FET素子の問題
点を説明するための図、第11図乃至第15図は夫々従来の
SOI構造のMOS FET素子の問題点を説明するための図であ
る。 1……基板、2……チャンネル、3……ゲート電極、4
……ゲート絶縁膜、5……ドレイン又はソース、6……
配線、7……絶縁層、8……絶縁層、9……絶縁層(SO
I用)、10……半導体層(SOI用)、14……基板、15……
発熱素子、16……高熱伝導性絶縁層、17……配線用金属
層、18……絶縁層、19……高熱伝導性膜、20……高熱伝
導性膜、21……チップ、22……高熱伝導板、23……高熱
伝導膜、24……放熱フィン、25……ボード、26……高熱
伝導板、27……放熱フィン、28……冷却用液体、29……
液体循環管。
1 to 5 are schematic diagrams showing an embodiment of the present invention, FIGS. 6 to 10 are diagrams for explaining the problems of the conventional MOS FET device, and FIGS. Figures are conventional
It is a figure for demonstrating the problem of the MOS FET element of SOI structure. 1 ... Substrate, 2 ... Channel, 3 ... Gate electrode, 4
...... Gate insulating film, 5 …… Drain or source, 6 ……
Wiring, 7 ... Insulating layer, 8 ... Insulating layer, 9 ... Insulating layer (SO
I ...), 10 ... Semiconductor layer (for SOI), 14 ... Substrate, 15 ...
Heating element, 16 ... High thermal conductive insulating layer, 17 ... Wiring metal layer, 18 ... Insulating layer, 19 ... High thermal conductive film, 20 ... High thermal conductive film, 21 ... Chip, 22 ... High thermal conductive plate, 23 …… High thermal conductive film, 24 …… Radiating fin, 25 …… Board, 26 …… High thermal conductive plate, 27 …… Radiating fin, 28 …… Cooling liquid, 29 ……
Liquid circulation pipe.

Claims (6)

【特許請求の範囲】[Claims] 【請求項1】基板に形成された1個以上の半導体素子
と、該素子上に形成された絶縁層から成るチップにおい
て、該絶縁層に少なくとも上記半導体素子近傍に至るよ
うに設けられたスルーホールに高熱伝導性絶縁膜を形成
し、該半導体素子が発生する熱を上記高熱伝導性絶縁膜
を含む熱流回路により除去するように構成したことを特
徴とする半導体チップ。
1. A chip comprising one or more semiconductor elements formed on a substrate and an insulating layer formed on the element, and a through hole provided in the insulating layer at least near the semiconductor element. A semiconductor chip characterized in that a high thermal conductive insulating film is formed on a substrate, and heat generated by the semiconductor element is removed by a heat flow circuit including the high thermal conductive insulating film.
【請求項2】上記基板に少なくとも上記半導体素子近傍
に至るように設けられたスルーホールに、高熱伝導性絶
縁膜を形成した請求項(1)記載の半導体チップ。
2. The semiconductor chip according to claim 1, wherein a high thermal conductive insulating film is formed in a through hole provided on the substrate at least near the semiconductor element.
【請求項3】前記高熱伝導性絶縁膜がAlN又はBNである
請求項(1)に記載の半導体チップ。
3. The semiconductor chip according to claim 1, wherein the high thermal conductive insulating film is AlN or BN.
【請求項4】前記高熱伝導性絶縁膜上に、放熱又は冷却
回路を設けた請求項(1)に記載の半導体チップ。
4. The semiconductor chip according to claim 1, wherein a heat dissipation or cooling circuit is provided on the high thermal conductive insulating film.
【請求項5】前記チップの一方側に取付けた高熱伝導性
板上にフィンを設けると共に上記チップの他方側に高熱
伝導性膜を介して高熱伝導性板を設け、この高熱伝導性
板上フィンを設けた請求項(1)に記載の半導体チッ
プ。
5. A fin is provided on a high heat conductive plate attached to one side of the chip, and a high heat conductive plate is provided on the other side of the chip via a high heat conductive film, and the fin on the high heat conductive plate is provided. The semiconductor chip according to claim 1, wherein the semiconductor chip is provided.
【請求項6】上記フィンを冷却用液体によって冷却する
ように構成した請求項(5)に記載の半導体チップ。
6. The semiconductor chip according to claim 5, wherein the fin is cooled by a cooling liquid.
JP63209765A 1988-08-23 1988-08-23 Semiconductor chip Expired - Fee Related JPH07120735B2 (en)

Priority Applications (6)

Application Number Priority Date Filing Date Title
JP63209765A JPH07120735B2 (en) 1988-08-23 1988-08-23 Semiconductor chip
GB8918867A GB2222721B (en) 1988-08-23 1989-08-18 Cooling semiconductor devices
FR8911128A FR2636777B1 (en) 1988-08-23 1989-08-22 SEMICONDUCTOR DEVICE WITH HEAT DISCHARGE CIRCUIT
DE19893927866 DE3927866A1 (en) 1988-08-23 1989-08-23 SEMICONDUCTOR COMPONENT
GB9117667A GB2246472A (en) 1988-08-23 1991-08-15 Cooling semiconductor devices
GB9117666A GB2246471B (en) 1988-08-23 1991-08-15 Cooling semiconductor devices

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP63209765A JPH07120735B2 (en) 1988-08-23 1988-08-23 Semiconductor chip

Publications (2)

Publication Number Publication Date
JPH0258255A JPH0258255A (en) 1990-02-27
JPH07120735B2 true JPH07120735B2 (en) 1995-12-20

Family

ID=16578250

Family Applications (1)

Application Number Title Priority Date Filing Date
JP63209765A Expired - Fee Related JPH07120735B2 (en) 1988-08-23 1988-08-23 Semiconductor chip

Country Status (1)

Country Link
JP (1) JPH07120735B2 (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103444080B (en) 2011-04-01 2016-07-27 瑞萨电子株式会社 Semiconductor device and manufacture method thereof and pocket telephone

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4828956A (en) * 1971-08-20 1973-04-17
JPS5895848A (en) * 1981-12-02 1983-06-07 Hitachi Ltd Semiconductor integrated circuit device

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4828956A (en) * 1971-08-20 1973-04-17
JPS5895848A (en) * 1981-12-02 1983-06-07 Hitachi Ltd Semiconductor integrated circuit device

Also Published As

Publication number Publication date
JPH0258255A (en) 1990-02-27

Similar Documents

Publication Publication Date Title
US6727422B2 (en) Heat sink/heat spreader structures and methods of manufacture
US6743972B2 (en) Heat dissipating IC devices
KR950005452B1 (en) Semiconductor apparatus and semiconductor package
US6521516B2 (en) Process for local on-chip cooling of semiconductor devices using buried microchannels
US20030097846A1 (en) Active temperature gradient reducer
US7290596B2 (en) Thermal management of systems having localized regions of elevated heat flux
TWI416675B (en) Integrated circuit with increased heat transfer
JP2007157835A (en) Mounting substrate
US7779638B2 (en) Localized microelectronic cooling apparatuses and associated methods and systems
CN110660762A (en) Heat transfer structure, power electronic module, method for manufacturing power electronic module, and cooling element
US7759789B2 (en) Local area semiconductor cooling system
US7842553B2 (en) Cooling micro-channels
US7303947B1 (en) Source bridge for cooling and/or external connection
JPH07120735B2 (en) Semiconductor chip
JPH0964255A (en) Semiconductor device
GB2222721A (en) Cooling semiconductor devices
JP2007299817A (en) Semiconductor device
JP3193142B2 (en) Board
GB2246472A (en) Cooling semiconductor devices
GB2246471A (en) Cooling semiconductor devices
JPH11135692A (en) Integrated circuit
JPH01295455A (en) Semiconductor laminated and integrated circuit element
JPH10256677A (en) Printed board
JPS63289847A (en) Heat dissipation structure of lsi package
JPH0258254A (en) Semiconductor element

Legal Events

Date Code Title Description
R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

LAPS Cancellation because of no payment of annual fees