GB2222721A - Cooling semiconductor devices - Google Patents

Cooling semiconductor devices Download PDF

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Publication number
GB2222721A
GB2222721A GB8918867A GB8918867A GB2222721A GB 2222721 A GB2222721 A GB 2222721A GB 8918867 A GB8918867 A GB 8918867A GB 8918867 A GB8918867 A GB 8918867A GB 2222721 A GB2222721 A GB 2222721A
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heat
insulating layer
intense
semiconductor device
heat conductive
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GB8918867A
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GB2222721B (en
GB8918867D0 (en
Inventor
Nobuo Mikoshiba
Kazuo Tsubouchi
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Priority claimed from JP20976488A external-priority patent/JPH0258254A/en
Priority claimed from JP63209765A external-priority patent/JPH07120735B2/en
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Publication of GB8918867D0 publication Critical patent/GB8918867D0/en
Publication of GB2222721A publication Critical patent/GB2222721A/en
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Publication of GB2222721B publication Critical patent/GB2222721B/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H01L23/367—Cooling facilitated by shape of device
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    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H01L23/373—Cooling facilitated by selection of materials for the device or materials for thermal expansion adaptation, e.g. carbon
    • H01L23/3731—Ceramic materials or glass
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    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
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    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
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    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
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    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
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    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
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    • H01L2924/12—Passive devices, e.g. 2 terminal devices
    • H01L2924/1204—Optical Diode
    • H01L2924/12042—LASER
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    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1306—Field-effect transistor [FET]
    • H01L2924/13091—Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
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    • H01L2924/151—Die mounting substrate
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    • H01L2924/1532—Connection portion the connection portion being formed on the die mounting surface of the substrate

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  • Engineering & Computer Science (AREA)
  • Chemical & Material Sciences (AREA)
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  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Materials Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Ceramic Engineering (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
  • Thin Film Transistor (AREA)

Description

r 1 222272, 1 SEMICONDUCTOR ELEMENT
FIELD OF THE INVENTION
This invention relates to a semiconductor element, and more particularly to an improvement using an arrangemerit suitable for heat discharge and cooling of the semiconductor element itself for purposes of establishing an ultra-high speed, ultra-high integrated electronic circuit.
BACKGROUND OF THE INVENTION
Incorporation of semiconductor integrated circuits into an integrated circuit has been developed to meet requirements of a ultra-high speed and a ultra-high density. However, a limit of heat discharge now prevents a further integration density of inte rated circuits which consume large power for high speed operations.
A logic circuit, for example, among presently used semiconductor integrated circuits, has the integra- tion rate of 1500 gates per chip approximately. Is power consumption per gate is about lmW, and heat Of about lw is generated per chip. This amount of heat is near the limit of heat charge by normal air-cooling, and it is difficult to further develop such integration by merely diminishing the sizes of elements.
In contrast, power consumption per chip is largely increased due to requirements of increasing the efficiency and the speed of a semiconductor integrated circuit. Large part of the consumed power is changed to heat, and the heat increases the temperature of the 2 entire chip and invites deterioration of the characteristic and the reliability of the element. Since-the beating generating portion is a very small operative region and the operation speed is very high, local and transient changes in the temperature are serious problems. Therefore, an existing heat discharging or radiating circuit designed for dealing with static, large regions is not sufficient at all, and the industry desires a high speed heat flow circuit suitable for dynamic, very small regions as well, considering transient conditions of the element during operation.
The problem of heat discharge of an existing semiconductor element is explained below, referring to drawings.
Figures 9 through 13 show existing MOS FET elements using silicon (Si).
The MOS FET element of Figure 9 has a typical structure. Since the structure is symmetrical, Figure 9 shows a quarter of one MOS FET element. Reference numeral 1 denotes a substrate made from p-Si, for example. Numeral 2 refers to a channel, and 3 to a gate electrode made from polycrystalline Si. Numeral 4, denotes a gate insulating layer made from, for example, silicon oxide SiO 2' and numeral 5 designates a source or drain made from, for example, n Si. Numeral 6 indicates a wiring made from, for example, Al. Numeral 7 designates an insulating layer made from, for example, SiO 2 Numeral 8 denotes an insulating layer made from, for example, SiO 2' In this typical arrangement,_the-gate length is 1.3pmr and the gate width is 51im. The driving 3 pulse current may be in a standard form of clock frequency SmHz and pulse width 100n sec (100 nanoseconds).
The thickness of the channel under the gate is about 8nm. The aforementioned pulse current causes generation of Joule heat of heat generating rate 2.9mW near the channel. The initial temperature of the entire element is 201C, and the surface of the insulating layer 8 discharges heat due to natural convection (heat transfer coefficient 103W/cm2,C).
Figure 10 shows how the temperature T changes with time around the channel of the MOS PET element. In response to ON and OFF changes of a pulse current, the temperature around the channel exhibits a transient chanQe of n sec. order in a local region of pm order.
Figure 11 shows a temperature distribution of an X-Y plan view of Figure 12 at the time 100n sec. later than application of the pulse current, i.e. just after the pulse current is cut off.
The temperature increase of the channel 2 at this time is about 41C. However, considering that,a significantly large temperature gradient as much as 100'C/im approximately is produced in the depth dir,ection (Y direction) in the gate insulating layer 4 and that temperature changes are responsive every several nanoseconds, the resulting local transient heat stress is very large.
Figure 12 shows a temperature distribution of the X-Y Plan view at the time 110n sec. later than application of the pulse current, i.e. 10n sec. later than the pulse current is cut off.
4 After the pulse current is cut off, the temperature near the channel suddenlv drolDs. Thus in the conventional arranaement of MOS FET element, locally, transiently large temperature changes occur near the channel, and a new heat flow circuit arrangement is required to remove this.
Figures 14 through 18 conventional SOI (silicon on insulator) arrangements for MOS FET elements.
In the MOS FET element having the SOI arrangement of Figure 14, numeral 9 denotes an insulating layer for the SOI arrangement which may be, for example, a SiO 2 layer of thickness 2Pm. Numeral 10 designates a semiconductor active layer for the SOI arrangement which may be a typical p-Si layer of thickness-0.3pm and area 5 x 7p 2 m as illustrated. The remainder arrangement is similar to the MOS FET element of Figure 9. To the element of Figure 14 is fed a pulse current similar to that in the example of Figures 9 through 13.
Figure 15 shows changes in the temperature with time around the silicon active layer and the channe ' 1 of the aforegoing element. Also in this case, the temperature around the channel 2 exhibits a locally, transiently violent change in response to ON and OFF changes of the pulse current.
Figure 16 shows a temperature distribution of a portion shown in Figure 18 at the time 100n sec. later than application of the pulse current, i.e. just after the pulse current is cut off. In this SOI-arranged MOS FET element, the temperature around the channel 2 is elevated much higher than the above-indicated MOS FET element on the Si substrate, because the heat conduction rate of the insulating laver (S'2) 9 is smaller by two digits or so than Si, heat discharge to the substrate is prevented, and the heat remains in the silicon active layer 10.
The temperature of the channel 2 is about 300C, 100n sec. later than application of the pulse, and it is higher by 6'C approximately than the MOS PET element on the Si substrate. Further, in the width of the gate insulating layer 9, a temperature gradient of about 170'C/pm is produced in the Y direction, that is, a larger heat stress than the case of the MOS PET element on the Si substrate is generated.
Figure 17 shows a temperature distribution of an X-Y plane portion also shown in Figure 18 at the time 150n sec. later than application of the pulse current, i.e. 50n sec. later than the pulse current is cut off. As compared to Figure 13, heat remains.
Therefore, in case of the SOI arrangement, heat discharge from the channel 2 to the Si substrate iq prevented by the insulating layer 9, and a new heat flow circuit arranqement is required to remove the heat.
OBJECT OF THE INVENTION It is therefore an object of the invention to provide a semiconductor device having a heat flow circuit capable of removing heat from small regions in a transient responsive manner.
SUMMARY OF THE INVENTION
In order to achieve the above-indicated object, an inventive semiconductor device is characterized in 6 that at least an insulating layer is made from an intenseheat conductive insulating material and that heat of a heat generating portion is removed by a heat flow circuit including the intense-heat conductive insulating layer.
Even if the temperature is increased trasiently and locally in a heat generating portion like the aforementioned channel, the heat is immediately removed by the heat flow circuit including the intense-beat conductive insulatinq laver.
BRIEF DESCRIPTION OF THE DRAWINGS
Figures 1 and 4 are schematic views of a MOS FET element embodying the invention; Figures 2 and 3 are temperature distribution views of the same embodiment; Figures 5 and 8 are schematic views of a SOIarranqed MOS FET element embodying the invention; Figures 6 and 7 are temperature distribution views of the same embodiment; Figures 9 through 13 are views for explaining 20 problems of a conventional MOS FET element; Figure 14 through 18 are views for explaining problems of a conventional SOI-arranged MOS FET element; and Figures 19 through 23 are schematic views of further embodiments of the invention.
DETAILED DESCRIPTION
Embodiments of the invention are explained below, referring to drawings.
A first embodiment shown in Figures 1 through 4 30 has a new arrangement of heat flow circuit in order to 7 overcome problems of a conventional MOS FET element.
As shown in Figure 1, the embodiment uses intenseheat conductive insulating layers 11 and 12 in lieu of the insulating layers 7 and 8 which prevent the heat flow in the conventional MOS FET element of Figure 9. An insulating layer 4 is made from SiO 2 as in the conventional device in order to maintain the MOS characteristic. As far as the MOS characteristic is not degraded, the layer 4 may also be an intense-heat conductive insulating layer. In this case, the intense-heat conductive insu lating layer is of A1N, BN or the like, but it may be any other layer which has a heat conduction ratio equivalent to a metal and which is an insulator. Also when one of the layers 11 and 12 alone is such an intense-heat conductive insulator and the other is a normal insulator, the device is effective.
Figures 2 through 4 show specific characteristics of the embodiment in which A1N is used as the intense-heat conductive insulating layers 11 and 12 to form an arrange- ment shown in Figure 4. Figure 2 shows a temperatu ' re distribution at the time 100n sec. later than the same pulse current as used in the conventional device is,fed.
Comparing Figure 2 of this embodiment with Figure 11 of the conventional device, the temperature around the channel is not increased in this embodiment, and an effect of this arrangement of heat flow circuit appears.
Figure 3 shows a temperature distribution of this embodiment at the time 110n sec. later than applica- tion of the pulse current (10n sec. later than the pulse 8 is cut off). As compared to Figure 12 of the conventional device, Figure 3 shows that heat is removed from the vicinity of the channel 2 in a short time as much as lOn sec. after the pulse current is cut off. This means that the inventive heat flow circuit is simple and greatly effective.
The above-described method can be used in a semiconductor element of a three-dimensional multi-layer structure.
A second embodiment shown in Figures 5 through 8 is described below.
This has a new arrangement of heat flow circuit in order to solve problems of the conventional SOIarranged MOS PET element.
As shown in Figure 5, this embodiment uses intense-heat conductive insulating layers 11, 12 and 13 in lieu of the insulating layers 7, 8 and 9 which behave as an obstacle of the heat flow circuit in the conventional SOI-arranged MOS PET element shown in Figure 14.
The insulating layer 4 is made ftom SiO 2 as in the, conventional device in order to maintain the electric characteristics of the MOS arrangement. However, as far as the MOS characteristic is not degraded, the insulating layer 4 may also be an intense-heat conductive insulating layer.
In this case, the intense-heat conductive insulating layer is of A1N, BN or the like, but it may be of any other material which has a heat conduction ratio equivalent to a metal and which is an insulator. Further, also when one or two of the insulating layers 11, 12 and 1 c 9 13 are intense-heat conductive insulating layers while the other or others are normal insulating layers, the device is effective. Figures 6 through 8 show specific characteristics of this embodiment in which AlN is used as the intense-heat conductive insulating layers 11, 12 and 13 as shown in Figure 8.
Figure 6 shows a temperature distribution of a portion shown in Figure 8 at the time 100n sec. later than the same pulse current as used in the conventional device is fed.
Comparing Figure 6 of this embodiment with Figure 16 of the conventional device, the temperature near the channel 2, gate insulating layer 4 and gate electrode 3 is not increased, that is, an effect of this arrangement of heat flow circuit appears.
Figure 7 shows a temperature distribution of the characteristic of this embodiment at the time 150n sec. later than application of the pulse current (50n sec. later than the pulse current is cut off).
As compared to Figure 17 of the conventiona,l arrangement, the device of Figure 7 removes heat from the vicinity of the channel 2 in a short time as much as 50n sec. after the pulse current is cut off. This shows that the inventive heat flow circuit is simple and greatly effective.
Figure 19 shows a further embodiment using a planar type heat flow circuit as a local, transient heat flow circuit throughout the entire chip. In the same drawing, a heat generating element 15 is provided on a substrate 14, and an intense-heat conductive insulating layer 16 is provided to cover them. The substrate 14 may be of Si, GaAs, InP, Al 2 0 3 or any other material suitable for forming the heat generating element 15. In this case, the heat generating element 15 may be any semiconductor element such as MOS type transistor, bipolar type transistor, semiconductor laser, light emitting diode, etc. which has a property of a local, transient heat generating source.
The intense-heat conductive insulating layer 16 may be of any material which has a heat conduction ratio equivalent to a metal and which is an insulator. For example, AlN, BN or the like is preferable. Locally, transiently variable heat generated around the heat generating element 15 is averaged by the planar type heat flow circuit including the insulating layer 16, heat stress is removed, and at the same time, a heat discharge circuit or a cooling circuit (both not shown) provided on the layer 16 efficiently discharges heat to the exterior before the heat extends to the entire chip. 20 The above-indicated method can also be used in a device in which the heat generating element or the semiconductor chip has a threedimensional multi-layer structure. Figure 20 shows a still further embodiment using a metal-wiring-combined heat flow circuit including the same substrate 14 and heat generating element 15 as those in Figure 19. Locally, transiently variable heat generated around the heat generating element 15 is pumped out by a metal wiring 17. Numeral 18 designates an insulating layer preferably made from an intense-heat 11 conductive insulating material but normally made from Sio 2 Therefore, in this case, heat is pumped up-from the heat generating element 15 by the metal wiring 17, it is subsequently averaged by the intense-heat conduc- tive insulating layer 16, and it is efficiently discharged to the exterior by a heat discharge circuit or a cooling circuit (both not shown) provided on the layer 16.
Figure 21 shows a yet further embodiment using a.through-hole type heat flow circuit. On the substrate 14 is provided a semiconductor element 15 which generates heat according to its purposes. The substrate 14 may be of any material such as Si, GaAs, InP, Al 2 0 3' Sio 2 or the like which is suitable for'forming the heat generating element 15. In this case, the heat generating element 15 may be any semiconductor element such as MOS type transistor, bipolar type transistor, semiconductor laser, light emitting diode, etc. which has a property of a local, transient heat generating source.
Although the heat flow circuit is readily confi- gured into a planar type in the embodiment of Figur,e 19, the periphery of the heat generating element normally has undulations due to the presence of a multi-laye,r wiring or a mesa construction and this prevents direct provision of such a planar intense-heat conductive layer.
Therefore, in this embodiment, a through hole is formed in the insulating layer 18 up to a portion near the heat generating element, and an intenseheat conductive layer 19 is formed in the hole. The intense-heat conductive layer 19 may be of a metal unless it degrades C_ 12 the electric characteristic of the heat generating element 15. In most casesr the layer 19 in the form of such an intense-heat conductive layer is designed more easily, and may be configured to directly contact the heat generating element 15. The intense-heat conductive insulating layer 15 is made from AlN, BN, etc. for example.
In the example of Figure 21, a further through hole is provided in the substrater and an intense-heat conductive layer 20 is formed therein, so that heat is removed from the substrate side as well. However, the device is effective, with the through hole type heat flow circuit 19 or 20 alone.
The intense-heat conductive layer 20 may be of a metal unless it degrades the electric characteristic of the heat generating element 15. In most cases, the layer 20 in the form of an intense-heat conductive insulating layer is designed more easily, and may be configured to directly contact the heat generating element 15. The intense-heat conductive insulating, layer 20 is made of AlN, BN, etc. for example.
A heat discharge circuit or a cooling circuit (both not shown), which is provided next to the layers 19 and 20, efficiently discharges the heat to the exterior before the heat extends to the entire chip.
Figure 22 shows a yet further embodiment using a heat discharge circuit in the form of an air cooling fin.
A chip 21 includes the aforementioned heat flow circuitr and the heat generating element in the chip is 1 13 a semiconductor element such as MOS type transistor, bipolar type transistor, semiconductor laser, light emitting diode, etc. which generates heat locally and transiently due to its high speed operation. In order to connect the chip 21 to a heat radiating fin 24, it is designed to remove heat from both the front and back sides of the chip. One side of the chip is attached to an intense-heat conductive plate 22 (preferably of an insulator such as AlN, BN, etc. in most cases, or an Al or Cu plate, etc. if a metal is employable), and heat is transmitted to the heat radiating fin 22. The other side of the chip is covered by the intense-heat conduc tive layer 23 (of AlN, BN, etc. for example) to fill a gap between the intense-heat conductive plate 26 and itself, and heat is transmitted to a heat radiating fin 27.
Numeral 25 designates a mount board. Since the local, transient heat generated in the chip is discharged to the exterior in this fashion before the heat extends in the transversal direction of the chip, high speed operation is stabilized.
Figure 23 shows an embodiment of a heat discharge or cooling circuit. As is used in the embodiment of Figure 22, numeral 21 refers to a chip, 22 to an intense heat conductive plate, 23 to an intense-heat conductive layer, 24 and 27 to heat radiating fins, and 25 to a mount -board. In this embodiment, coolant 28 flows along a coolant circulating tube 29. The coolant 28 may be any T tg-7. 4.) material suitable for cooling, such as FreonX water, etc.
14 Thus the embodiment can efficiently remove from the chip a much more amount of heat than in the air cooling, and ensures a more stable high speed operation.
As described above, according to the invention where a semiconductor element itself or a semiconductor chip includes a heat flow circuit which is responsive transiently and capable of removing heat from small regions, the integrating density of electronic circuits is increased, high speed operation is stabilized, and functions of the semiconductor element are remarkably enhanced.
--- 1 1

Claims (14)

  1. WHAT IS CLAIMED IS:
    A semiconductor device comprising at least one insulating layer in the form of an intense-heat conductive insulating layer, so that heat in a heat generating portion is removed by a heat flow circuit including said intense-heat conductive insulating layer.
  2. 2. The semiconductor device according to claim 1 wherein said semiconductor device is a MOS FET element.
  3. 3. The semiconductor device according to claim 1 wherein said semiconductor device is a SOI-arranged MOS FET element.
  4. 4. The semiconductor de.vice according to claim 1, 2 or 3 wherein said intense-heat conductive insulating layer is an A1N layer or a BN layer.
  5. 5. The semiconductor device according to claim,2 or 3 wherein a gate insulating layer of said MOS FET element or SOI-arranged MOS FET element is an intense-heat conductive insulating layer.
  6. 6. The semiconductor device according to claim 1 wherein said semiconductive device is a chip consisting of at least one semiconductor element provided on a substrate, wherein said intense-heat conductive insulating layer is at least locally opposed to said semiconductor element, and wherein said heat flow 16 circuit including said intense-heat conductive insulating layer removes heat generated by said semiconductor element.
  7. 7. The semiconductor device according to claim 6 wherein said intenseheat conductive semiconductor layer is in a surface contact with said semiconductor element.
  8. 8. The semiconductor device according to claim 7 wherein a heat absorbing metal wiring is provided between said intense-heat conductive insulating layer and said semiconductor element.
  9. 9. The semiconductor device according to claim 1 wherein said semiconductor device is a chip consisting of at least one semiconductor element provided on a substrate and an insulating layer provided on said element, wherein said intense-heat conductive insulating layer is provided in a through hole formed in said insulating layer so as to reach at least a portion near said semiconductor element, and wherein heat generated by said semiconductor element is removed by said heat flow circuit including said intense-heat conductive insulating layer.
  10. 10. The semiconductor device according to claim 6 wherein said intenseheat conductive insulating layer is formed in a through hole provided in said substrate so as to reach at least a portion near said semiconductor element.
    17 7
  11. 11. The semiconductor device according to claim 6, 8, 9 or 10 wherein said intense-heat conductive insulating layer is made from A1N or BN.
  12. 12. The semiconductor device according to claim 6, 7, 8, 9, 10 or 11 wherein a heat radiating or cooling circuit is provided on said intenseheat conductive insulating layer.
  13. 13. The semiconductor device according to claim 6, 7, 8, 9, 10, 11 or 12 wherein a fin is provided on an intense-heat conductive plate attached to one side of said chip, while an intense-heat conductive plate is provided at the other side of said chip via an intense-heat conductive layer and a fin is provided on said intense-heat conductive plate.
  14. 14. The semiconductor device according to claim 13 wherein said fin is cooled by a coolant.
    1 Published 1 Mat The Patent Office. State House. 86 7 1 High Hc)burn. Loondon WC 1 R 47P Further copies maybe ob-nedf!rom The PstantOffloe. Sales Branch. St Mary Cray. Orpington, K3nt 13RZ 3RD. Printed by Multiplex techniques ltd. St Mary Cray. Kent. Com 187
GB8918867A 1988-08-23 1989-08-18 Cooling semiconductor devices Expired - Fee Related GB2222721B (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP20976488A JPH0258254A (en) 1988-08-23 1988-08-23 Semiconductor element
JP63209765A JPH07120735B2 (en) 1988-08-23 1988-08-23 Semiconductor chip

Publications (3)

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GB8918867D0 GB8918867D0 (en) 1989-09-27
GB2222721A true GB2222721A (en) 1990-03-14
GB2222721B GB2222721B (en) 1993-07-28

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DE (1) DE3927866A1 (en)
FR (1) FR2636777B1 (en)
GB (1) GB2222721B (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6620045B2 (en) 2001-04-20 2003-09-16 King Show Games, Llc System and method for executing trades for bonus activity in gaming systems
US7687901B2 (en) 2005-01-24 2010-03-30 Toyota Jidosha Kabushiki Kaisha Heat dissipating fins opposite semiconductor elements
US7704142B2 (en) 2001-04-20 2010-04-27 King Show Games, Inc. System and method for facilitating trades for bonus activity in gaming systems

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5057908A (en) * 1990-07-10 1991-10-15 Iowa State University Research Foundation, Inc. High power semiconductor device with integral heat sink
EP0520294B1 (en) * 1991-06-24 1998-08-26 Siemens Aktiengesellschaft Semiconductor device and method of manufacturing the same
US5396403A (en) * 1993-07-06 1995-03-07 Hewlett-Packard Company Heat sink assembly with thermally-conductive plate for a plurality of integrated circuits on a substrate
FR2754390A1 (en) * 1996-10-07 1998-04-10 Gec Alsthom Transport Sa POWER MODULE WITH ELECTRICAL SEMICONDUCTOR POWER COMPONENTS AND HIGH POWER SWITCH COMPRISING AT LEAST ONE SUCH POWER MODULE

Citations (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB1265007A (en) * 1968-12-09 1972-03-01
GB1320924A (en) * 1969-07-22 1973-06-20 Gen Electric Semiconductor device with thermally conductive dielectric barrier
EP0015053A1 (en) * 1979-01-27 1980-09-03 LUCAS INDUSTRIES public limited company A method of manufacturing a semi-conductor power device assembly and an assembly thereby produced
EP0040552A1 (en) * 1980-05-20 1981-11-25 De Beers Industrial Diamond Division (Proprietary) Limited Heat sinks
EP0153618A2 (en) * 1984-02-24 1985-09-04 Kabushiki Kaisha Toshiba Method for preparing highly heat-conductive substrate and copper wiring sheet usable in the same
EP0153737A2 (en) * 1984-02-27 1985-09-04 Kabushiki Kaisha Toshiba Circuit substrate having high thermal conductivity
EP0201170A1 (en) * 1985-04-12 1986-11-12 Raymonde Gene Clifford Artus Heat sink
EP0253295A1 (en) * 1986-07-09 1988-01-20 Tektronix, Inc. Thermally enhanced LSI integrated circuit package
EP0286690A1 (en) * 1986-08-13 1988-10-19 Hitachi Metals, Ltd. Aluminum nitride and semiconductor substrate formed therefrom

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3686748A (en) * 1970-04-13 1972-08-29 William E Engeler Method and apparatus for providng thermal contact and electrical isolation of integrated circuits
DE2030809A1 (en) * 1970-06-23 1971-12-30 Semikron Gleichrichterbau Semiconductor arrangement
US4236167A (en) * 1978-02-06 1980-11-25 Rca Corporation Stepped oxide, high voltage MOS transistor with near intrinsic channel regions of different doping levels
JPS56101777A (en) * 1980-01-18 1981-08-14 Futaba Corp Mos type semiconductor device
US4256792A (en) * 1980-01-25 1981-03-17 Honeywell Inc. Composite electronic substrate of alumina uniformly needled through with aluminum nitride
US4620215A (en) * 1982-04-16 1986-10-28 Amdahl Corporation Integrated circuit packaging systems with double surface heat dissipation
JPS6066843A (en) * 1983-09-22 1985-04-17 Hitachi Ltd Integrated circuit package
JPS61212045A (en) * 1985-03-18 1986-09-20 Hitachi Ltd Semiconductor device
JPH07107921B2 (en) * 1985-11-15 1995-11-15 富士通株式会社 Plastic / Package type semiconductor device
GB2214719B (en) * 1988-01-26 1991-07-24 Gen Electric Co Plc Housing for electronic device

Patent Citations (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB1265007A (en) * 1968-12-09 1972-03-01
GB1320924A (en) * 1969-07-22 1973-06-20 Gen Electric Semiconductor device with thermally conductive dielectric barrier
EP0015053A1 (en) * 1979-01-27 1980-09-03 LUCAS INDUSTRIES public limited company A method of manufacturing a semi-conductor power device assembly and an assembly thereby produced
EP0040552A1 (en) * 1980-05-20 1981-11-25 De Beers Industrial Diamond Division (Proprietary) Limited Heat sinks
EP0153618A2 (en) * 1984-02-24 1985-09-04 Kabushiki Kaisha Toshiba Method for preparing highly heat-conductive substrate and copper wiring sheet usable in the same
EP0153737A2 (en) * 1984-02-27 1985-09-04 Kabushiki Kaisha Toshiba Circuit substrate having high thermal conductivity
EP0201170A1 (en) * 1985-04-12 1986-11-12 Raymonde Gene Clifford Artus Heat sink
EP0253295A1 (en) * 1986-07-09 1988-01-20 Tektronix, Inc. Thermally enhanced LSI integrated circuit package
EP0286690A1 (en) * 1986-08-13 1988-10-19 Hitachi Metals, Ltd. Aluminum nitride and semiconductor substrate formed therefrom

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6620045B2 (en) 2001-04-20 2003-09-16 King Show Games, Llc System and method for executing trades for bonus activity in gaming systems
US7704142B2 (en) 2001-04-20 2010-04-27 King Show Games, Inc. System and method for facilitating trades for bonus activity in gaming systems
US9536380B2 (en) 2001-04-20 2017-01-03 Bradley Berman System and method for facilitating trades for bonus activity in gaming systems
US7687901B2 (en) 2005-01-24 2010-03-30 Toyota Jidosha Kabushiki Kaisha Heat dissipating fins opposite semiconductor elements

Also Published As

Publication number Publication date
FR2636777A1 (en) 1990-03-23
GB2222721B (en) 1993-07-28
FR2636777B1 (en) 1994-02-11
GB8918867D0 (en) 1989-09-27
DE3927866A1 (en) 1990-03-08

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