JPH0258254A - Semiconductor element - Google Patents

Abstract

PURPOSE:To obtain a semiconductor element provided with a heat flow circuit which responds to a transient state and can eliminate heat from a minute region, by forming at least one insulating layer by using a high thermal conduction insulating layer, and constituting it in the manner in which the heat in a heat generating part is eliminated by the heat flow circuit containing the high thermal conduction insulating layer. CONSTITUTION:At least one insulating layer of a semiconductor element is formed by using a high thermal conduction insulating layer, and constituted in the manner in which the heat in a heat generating part is eliminated by a heat flow circuit containing the high thermal conduction insulating layer. For example, an MOS FET element is constituted of the following; a substrate 1 composed of p-Si, a channel 2, a gate electrode 3 composed of polycrystalline Si, a gate insulating film 4 composed of a silicon oxide film SiO2, a source or drain composed of N<+> type Si, a wiring 6 composed of Al, and high thermal conduction insulating layers 11, 12 composed of AlN, BN, etc. Since the semiconductor element itself is provided with the heat flow circuit which responds to a transient state and can eliminate heat from a minute region, the integration degree of an electronic circuit is increased, and the high speed operation is stabilized.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a semiconductor device, and in particular to realizing an ultra-high speed, ultra-highly integrated electronic circuit by making the semiconductor device itself have a structure suitable for heat dissipation/cooling. Regarding improvements for.

[Summary of the Invention] One or more insulating layers of a semiconductor element are formed of a highly thermally conductive insulating layer, and heat from a heat generating portion of the element is removed by a heat flow circuit including the insulating layer.

[Prior Art] Semiconductor integrated circuits are being developed in accordance with the demands for ultra-high speed and ultra-high density.
Although integration has progressed over the years, the degree of integration of integrated circuits that require high power consumption for high-speed operation is already being limited by heat dissipation limits.

In the currently used semiconductor integrated circuits, for example, an example of a logic circuit has a degree of integration of about 150 gates per chip, but the power consumption is about 1 mW per gate, so it generates about IW per chip. This amount of heat is close to the heat dissipation limit of normal air cooling, and it will be difficult to integrate the device using only miniaturization technology in the future.

[Problems to be Solved by the Invention] However, with the demand for higher performance and higher speed of semiconductor integrated circuits, the power consumption per chip is rapidly increasing.

Most of the power consumed becomes heat, and this generated heat increases the temperature of the entire chip, causing deterioration of element characteristics and reliability. However, the part where heat is generated is extremely small. Since this is an operating region and the operating speed is very high, local and transient temperature changes become a problem. Therefore, conventional heat dissipation circuits that handle static and large areas are completely inadequate, and there is a need for a high-speed heat flow circuit that takes into account the transient state of the element during operation and takes into consideration even the smallest areas.

First, problems in heat dissipation of conventional semiconductor devices will be illustrated.

9 to 13 show conventional examples of MO3FET elements using Si.

FIG. 9 shows a typical structure of a conventional MOS FET element. One MOS because the structure is symmetrical
This shows a 1/4 portion of the FET element. In the same figure, 1
is a substrate, for example made of p-8i. 2 is the channel,
3 is a gate electrode, and this gate electrode is made of, for example, polycrystalline Si.
Consists of. 4 is a gate insulating film, for example, a silicon oxide film Sio2. 5 is the source or drain, for example n
6 is a wiring made of, for example, Al1. 7 is an insulating layer, made of, for example, Sin. 8 is an insulating layer, 1 is made of, for example, Sio2. In this typical example, the gate length is , 1.3 μm, and the gate width is 5 μm.The driving pulse current has a clock frequency of 5 MHz and a pulse width of 10
A standard one of 0 nsec is used.

The channel under the gate has a thickness of about 8 nm, and due to the above pulse current, Joule heat is generated near the channel at a heat generation rate of 2.9 mW.

The initial temperature of the entire device is 20''C, and the surface of the insulating layer 8 radiates heat by natural convection (heat transfer coefficient 1 (V'w/d°C)).

FIG. 10 shows the temporal change in temperature around the channel of the MO5FET element. Pulse current ON/OFF
In response to the change in , the temperature around the channel changes transiently on the order of n9ee in a local region on the order of μm.

FIG. 11 shows the temperature distribution in the X-Y plan view shown in FIG. 12 after 1OOnsec, that is, immediately after the pulse current is turned off.

At this time, the temperature rise in channel 2 is approximately 4°C, but in the gate insulating film 4 it is approximately 100°C in the depth direction (Y direction).
Considering that a very large temperature gradient of /μm is occurring and that the temperature change responds by several nanometers, the resulting local transient thermal stress is extremely large.

FIG. 12 similarly shows the temperature distribution in the X-Y plane view after 110 nsec, that is, after 10 nsee after the pulse current was cut off.

After the pulse current is cut off, the temperature near the channel drops rapidly. In this way, conventional MOS FET
In the device structure, there is a large local and transient temperature change near the channel, and in order to eliminate this, a new heat flow circuit structure is required.

Figures 14 to 18 show SOI (Silicon
1 shows a conventional example of a MOS FET element with an onInsulator structure.

In the MOS FET element with the SOT structure shown in FIG. 14, 9 is an insulating layer for SOI, and 1 is, for example, an S
This is the i02 layer. 10 is a semiconductor active layer for SO2,
For example, p-3i, thickness 0.3 μm, area 5 x 7 μm2
A typical example is shown below. The other structure is the MOS shown in Figure 9.
It is similar to a FET device. The elements in Figure 14 include:
A pulse current similar to the example shown in FIGS. 9 to 13 is applied.

FIG. 15 shows the temporal change in temperature around the silicon active layer 10 and channel 2 in the above device. As expected, the temperature around channel 2 changes locally and transiently in response to changes in the ON and OFF states of the pulse current. fluctuates wildly.

FIG. 16 shows the temperature distribution in the portion shown in FIG. 18 after l OOn see, that is, immediately after the pulse current is cut off. In this SOI structure MO5FET element, the temperature around the channel 2 becomes much higher than in the above-mentioned MOS FET element on the SL substrate.

This is because the thermal conductivity of the insulating film (SiO2) 9 is about two orders of magnitude lower than that of Si, which prevents heat radiation to the substrate and causes heat to accumulate in the silicon active layer 10.

The temperature of the channel 2 at 100 nsec after pulse application is about 30°C, which is about 6°C higher than that of the MO5FET device on the Si substrate, and the width of the gate insulating film 9 has a temperature gradient of about 170°C/μm in the Y direction. is completed, and the above S
MO3FET on i board! Even greater heat stress occurs than in the case of children.

FIG. 17 shows the X-
When compared with FIG. 13 above, which shows the temperature distribution on the Y plane, heat remains.

Therefore, in the case of the SOI structure, heat is prevented from escaping from the channel 2 to the Si substrate by the insulating layer 9, so a new heat flow circuit structure is required to remove this heat.

[Object of the Invention] In consideration of the above points, an object of the present invention is to provide a semiconductor element equipped with a heat flow circuit that responds transiently and can remove heat from a minute area.

[Means for solving problem i11] The semiconductor device of the present invention achieves the above object.

At least the insulating layer is formed of a highly thermally conductive insulating layer.

The gist of the present invention is that the heat of the heat generating portion is removed by a heat flow circuit including the above-mentioned highly thermally conductive insulating layer.

[Function] Even if there is a transient or local temperature rise in the heat generating portion such as the channel, it is quickly removed by the heat flow circuit including the highly thermally conductive insulating layer.

[Example] Hereinafter, each example of the present invention will be described with reference to the drawings.

First, the first embodiment shown in FIGS. 1 to 4 has a new heat flow circuit structure in order to solve the problems of conventional MOS FET elements.

The insulating layers 7 and 8, which obstructed the heat flow circuit in the conventional MOS FET device shown in FIG. 9, are replaced with highly thermally conductive insulating layers 11 and 1, as shown in FIG.
Replaced with 2. The insulating layer 4 is made of conventional Sin in order to maintain MO3 characteristics.

4 may also be used as a highly thermally conductive insulating layer as long as it does not deteriorate the MO5 characteristics. In this case, the highly thermally conductive insulating layer is AQN
, BN, etc., but other materials may be used as long as they have thermal conductivity comparable to metals and are insulators.
It is effective even if only one of them is a highly thermally conductive insulating layer and the other is a normal insulating layer.

One specific example of the characteristics of this embodiment is shown in FIGS. 2 to 4. In this case, AflN is used as the high thermal conductive insulating layer 11.
12, and the structure shown in FIG. 4 was obtained. Figure 2 shows that when the same pulse current used in the conventional example is applied, 100n
The temperature distribution after sec is shown.

Comparing FIG. 11 of the conventional example and FIG.
The effect of the heat flow circuit of this structure is evident.

FIG. 3 shows the temperature distribution after 110 nsec (10 nsec after the pulse ends) in this example. Compared to the conventional structure shown in FIG. 12, in FIG. 3, the heat is removed from the vicinity of channel 2 after 10 n seconds after the pulse current is cut off, indicating that the current circuit of this embodiment is simple and effective. Something huge is happening.

Note that the above method can also be applied to a semiconductor element having a three-dimensional multilayer structure.

The second embodiment shown in FIGS. 5 to 8 will now be described.

This is a new heat flow circuit structure to solve the problems of the conventional SOI structure MOS FET element.

In this embodiment, as shown in FIG. 5, the insulating layers 7, 8.9, which obstruct the heat flow circuit in the MO5FET element with the S○ structure shown in FIG. They were replaced with insulating layers 11, 12, and 13. The insulating layer 4 is MO
In order to maintain the electrical characteristics of S, conventional Si is used, but the insulating layer 4 may also be a highly thermally conductive insulating layer as long as it does not deteriorate the MOS characteristics.

In this case, the highly thermally conductive insulating layer is AQN.

6. BN etc., but other materials may be used as long as they have thermal conductivity comparable to metals and are insulators.6. In addition, the insulating layer 11,
It is effective even if one or two of 12.13 are high thermally conductive insulating layers and the others are ordinary insulating layers. One specific example of the characteristics of this embodiment is shown in FIGS. 6 to 8. In this case, as shown in FIG. did.

FIG. 6 shows the temperature distribution in the portion shown in FIG. 8 after 100 nsec when the same pulse current used in the conventional example was applied.

Comparing FIG. 16 of the conventional example and FIG. 6 of the present example, the temperature near the channel 2, gate insulating film 4, and gate electrode 3 does not rise, and the effect of the heat flow circuit of this structure is evident. .

FIG. 7 shows the temperature distribution after 150 nsec (50 nsec after the above-mentioned pulse current is cut off) of the characteristics of this example.

If you compare it with the conventional structure shown in Fig. 17, in Fig. 7.

Heat is removed from the vicinity of channel 2 only 50 nsees after the pulse current is cut off, demonstrating that the heat flow circuit of this embodiment is simple and extremely effective.

[Effects of the Invention] As is clear from the above explanation, according to the present invention, the semiconductor element itself responds transiently and is equipped with a heat flow circuit that can remove heat from a minute area, thereby improving the efficiency of the 11-child circuit. The degree of integration increases, high-speed operation becomes stable, and the functionality of semiconductor devices can be dramatically improved.

[Brief explanation of the drawing]

1 and 4 are schematic diagrams showing one embodiment of a MOS FET element according to the present invention, FIGS. 2 and 3 are temperature distribution diagrams of the embodiment, respectively, and FIGS. 5 and 8 are schematic diagrams showing an embodiment of a MOS FET element according to the present invention. by S
6 and 7 are temperature distribution diagrams of the embodiment, and FIGS. 9 to 13 each illustrate the problems of conventional MOS FET elements. The explanatory diagrams, FIGS. 14 to 18, are diagrams for explaining the problems of the conventional SOI structure MOS FET element, respectively. 1...Substrate, 2...Channel, 3...Gate electrode, 4...
...Gate insulating film, 5...Drain or source, 6...Wiring, 7...
...Insulating layer, 8...Insulating layer, 9.
...Insulating layer (for SOI), 1o...
...Semiconductor layer (for SOI), 11...
・High thermal conductive insulating layer, 12... High thermal conductive insulating layer, 13... High thermal conductive insulating layer (
for SOI). Figure 1 Patent applicant Mikoshiba (one other person) attorney
Patent Attorney Nagai 1) Takeshi Part 5 Figure 9 Figure 10 End-to-end (Figure N Figure 14

Claims (5)

[Claims] (1) A semiconductor device characterized in that at least one insulating layer is formed of a highly thermally conductive insulating layer, and the heat from the heat generating part is removed by a heat flow circuit including the highly thermally conductive insulating layer. element. (2) The semiconductor device according to claim 1, wherein the semiconductor device is a MOSFET device. (3) The semiconductor device according to claim 1, wherein the semiconductor device is a MOSFET device having an SOI structure. (4) The semiconductor device according to claim (1), (2) or (3), wherein the highly thermally conductive insulating layer is an AlN or BN layer. (5) MOSFET element or SOI structure MOSFET
4. The semiconductor device according to claim 2, wherein the gate insulating film of the device is formed of a highly thermally conductive insulating film.