JPH03171657A - Semiconductor device - Google Patents

Semiconductor device

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Publication number
JPH03171657A
JPH03171657A JP31030989A JP31030989A JPH03171657A JP H03171657 A JPH03171657 A JP H03171657A JP 31030989 A JP31030989 A JP 31030989A JP 31030989 A JP31030989 A JP 31030989A JP H03171657 A JPH03171657 A JP H03171657A
Authority
JP
Japan
Prior art keywords
resistor
semiconductor
polysilicon
protrusion
semiconductor device
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP31030989A
Other languages
Japanese (ja)
Inventor
Hirokazu Yasuda
博和 安田
Nobutaka Goto
後藤 信隆
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Kyushu Fujitsu Electronics Ltd
Fujitsu Ltd
Original Assignee
Kyushu Fujitsu Electronics Ltd
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Kyushu Fujitsu Electronics Ltd, Fujitsu Ltd filed Critical Kyushu Fujitsu Electronics Ltd
Priority to JP31030989A priority Critical patent/JPH03171657A/en
Publication of JPH03171657A publication Critical patent/JPH03171657A/en
Pending legal-status Critical Current

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  • Semiconductor Integrated Circuits (AREA)
  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)

Abstract

PURPOSE:To enable heat released from a polycrystalline semiconductor resistor to be effectively dissipated so as to effectively prevent a hot spot from being generated by a method wherein a heat dissipating means is provided to the polycrystalline semiconductor resistor. CONSTITUTION:The ends of a polysilicon resistor 1 are brought into ohmic contact with a metal wiring 3 of Al or the like through contact windows 4 respectively. A conductive protrusion 2 is provided to a part of the resistor 1. The protrusion 2 is conductive and higher than a surrounding insulator in thermal conductivity. Joule heat released from the resistor 1 is dissipated through the intermediary of the protrusion 2. A protrusion serving as a heat radiator is properly provided, whereby a part of the resistor 1 where a current flows is prevented from being heated, and a hot spot is restrained from occurring.

Description

【発明の詳細な説明】 [概要] 多結晶半導体たとえばポリシリコンを電気抵抗体として
用いた半導体装置に関し、 ポリシリコンを電気抵抗体として使用する半導体装置に
′おいて、ホットスポットによる金属配線のエレクトロ
マイグレーションないしは抵抗体の抵抗値の変化の問題
を解決し、信頼性の高い半導体装置を提供することを目
的とし、 半導体基板と、前記半導体基板の上に形威された第1の
絶縁膜と、前記絶縁膜の上に形成され、1対のt極間に
接続される電流通路を画定する多結晶半導体抵抗体と、
前記多結晶半導体抵抗体の上に形成された第2の絶縁膜
とを有し、前記多結晶半導体抵抗体はそのl部に放熟の
ための突起部を設けているように梢成する. [産業上の利用分野〕 本発明は半導体装置に関し、特に多結晶半導体たとえは
ポリシリコンを電気抵抗体として用いた半導体装置に関
する. 本明細書において「多結晶半導体」とは、単結晶半導体
と対比した概念を示し、いわゆる「アモルファス半導体
」を含む. [従来の技術J 半導体集積回v8装置の製造において、抵抗素子を不純
物の拡散工程を利用してシリコン基板内に形成すること
が行われる.たとえば、n型半導体層中にp型ストライ
プ領域を拡散し、その両端に1対の金属電極を接続する
.n型半導体層とp型ストライプ領域との間のpntH
合を逆バイアスするようにn型半導体層をバイアスし、
1対の金属t極間に電流を流すようにするとp型ストラ
イプ領域はほぼ一定の抵抗値を有する抵抗素子として用
いることができる.抵抗素子においては、電流がその内
を流れることによりジュール熱が発生する.上述のよう
なバルク拡散抵抗は、周囲を熱伝導率の高いシリコンに
よって囲まれているので、発生した熱は周囲のバルクシ
リコンに伝達されて放熱される.このため、抵抗素子か
らの発熱が特に問題となることはなかった. ところで、半導体集積回路装置の集積度の向上につれて
集積回路の高密度化が促進されている.このため、回路
を構成する能動素子、受動素子は益々小型化することが
望まれている.抵抗素子もより小型化すること、より高
抵抗化すること等が望まれている.近年、多結晶シリコ
ン(ポリシリコン)を用いた抵抗の利用が進められてい
る.ポリシリコンは基板上に形成でき、基板の面積利用
率を上げることができる. たとえば、いわゆるエスパー(ESPER)と呼ばれる
綱造とそのプロセスが開発された.この構造においては
、多結晶半導体であるポリシリコンでエミッタ引出し電
極、ベース引出し電極を形或する.このポリシリコンプ
ロセスで同時に抵抗体を形成することができる.高抵抗
のポリシリコン抵抗体をエミッタ(またはベース)の引
出し電極形戊と同時に形或して、負荷抵抗等として用い
る.多結晶の利用によって、高抵抗率領域が形成でき、
周囲が酸化膜等によって覆われるので拡散抵抗のような
pn接合によるアイソレーションが不要となる.このよ
うに、小型化にa適という利点があり、高密度化の観点
からポリシリコン抵抗の採用が盛んになっている. [発明が解決しようとする課題1 ところが、ポリシリコン抵抗体は熱伝専率の悪いシリコ
ン酸化膜上に形成されるので、抵抗体の完然により局所
的高温部であるホットスポットが発生する.このホット
スポットは抵抗体の上に絶縁層を介して配線される上層
配線、たとえば^1配線を過度に加熱し、エレクトロマ
イグレーションによる^1配線の断線を引き起こし易く
する.これは半導体装置の寿命を短くし、信頼性を低下
する.さらに、ホットスポットによる抵抗体の温度上昇
は抵抗体自身の抵抗値の変動をもたらす.半導体抵抗は
一般に温度が上昇すると抵抗値は減少し、温度が下がる
と抵抗値は上昇して元の値に戻る.しかし、高温になり
すぎると温度が下がっても抵抗値が元の値に戻らず(一
般に高くなる)、抵抗値の経時変化を引き起こす.これ
らの現象は製造された半導体装置の信頼性を低下させる
原因となり好ましくない. 図面を参照して、以下に具体的にエレクトロマイグレー
ションを説明する. 第7図(A)に、従来のポリシリコン抵抗体を使用した
半導体装置の楕遣の平面図を、第7図(B)に第7図(
A)のII−II’線に沿う断面図を示す.第7図にお
いて、ポリシリコン抵抗体71はその両端部がコンタク
ト窓74で金属配線(^1)73とオーミックコンタク
トされる.ポリシリコン抵抗体71と交差するように他
の^1配線76が抵抗体7lの上の酸化シリコンの絶縁
層79上に形成される.抵抗体71の上下の層78、7
9は酸化シリコン層であるので熱伝導が悪く、抵抗体7
1がジュール熟により加熱されると、ホットスポットを
形成する.やがてその熱は上部のA1配線76を加熱す
る.加熟されたA1配線76に電流か流れるとエレクト
ロマイグレーションが発生し、次第に八lt極76はや
せ細り、ついには第8図に示すように断線状態に至る.
同様に、76配線のない場合でのA1配線76゜でもエ
レクトロマイグレーションが発生する. 本発明の目的は多結晶半導体、特にポリシリコンを電気
抵抗体として使用する半導体装置において、ホットスポ
ットによる金属配線のエレクトロマイグレーションない
しは抵抗体の抵抗値の変化の問題を解決し、信頼性の高
い半導体装置を提供することである. [課題を解決するための手段] 本発明によれば、半導体基板上に形或する多結晶半導体
抵抗素子に放熟手段を設ける.第1図は本発明の原理説
明図である.ポリシリコン抵抗体1はその両端部がコン
タクト窓4を介して^1等の金属配線3とオーミックに
コンタクトされている.抵抗体1はその1部に導電性の
突起部2を設けて形戒される.なお、第1図(B)に第
1図(A)のI−I’線に沿う断面図を示す.Si等の
半導体基板7上に酸化膜8が形成され、その上にポリシ
リコンの抵抗体1が形成されている.ポリシリコン抵抗
体1の両端には^1等の配線層3かオーミックに接触し
ている.これらの導電体1、3を覆って絶縁膜9が形威
されている.絶縁膜9上には他の配線6、6゜が形成さ
れている.[作用] 突起部2は樺電性であり、周囲の絶縁物より高い熟伝専
率を有する. 抵抗体1で発生するジュール熟はこの突起部2を介して
放熟される.放熱体の役目をする突起部を適当に設ける
ことにより、抵抗体1内の電流が流れる部分の加熟が防
止され、ホットスポットの発生が防止される.その突起
部2の寸法や形状あるいは面積はそれぞれの半導体装置
で必要な放熱量に応じて適宜調整される.高密度化に有
利な多結晶半導体抵抗素子を使用した楕造を採用しつつ
、多結晶半導体抵抗素子中にホットスポットが発生する
ことを防止して、エレクトロマイグレーションによる金
属配線の断線や抵抗体の抵抗値の変化を防止することが
できる. [実施例] 以下図面を参照して、本発明の実施例を説明する.なお
、以下にのべる実膝例の図では、第1図(B)で示した
上層の^1配線6、6゜は図面の簡略化のために省略し
てある. 第2図は本発明の実施例による半導体装置の梢戊を示す
平面図である.その断面構造は第1図(B)のものと同
様である.従来の技術と同様の製造プロセスで製造でき
る.シリコン基板の表面を熱酸化すること等により基板
上に酸化シリコン層を形成し、その上に熱分解CVD、
プラズマCVD等によりポリシリコン層を形成する.こ
のポリシリコン層からポリシリコン抵抗体21をパタニ
ングする.この時、同時にポリシリコン抵抗体21から
突出する突起部22もパターニングする.ポリシリコン
抵抗体21上に絶縁膜が形成され、ポリシリコン抵抗体
21の両端部分で絶縁展にコンタクト窓が開口される.
この上にA1等の配線層23が形威され、バターニング
される.ポリシリコン抵抗体21はその両端部がコンタ
クト窓24で^1金属配線23とオーミツクコンタクト
される.ポリシリコン抵抗体21はコンタクト窓24で
挾まれる〈電流の流れる〉中間部の側部に突起部22を
設けてパターニングされている.突起部22は他端を浮
潜状態のまま、1端でのみ電流路に接続され、突出して
いるので、電流路〈抵抗)としては、実質的に機能しな
い.しかし、物理的、熱的に連続しているのでポリシリ
コン抵抗体21中の発熟に対する放熱体としては作用し
、ポリシリコン抵抗体21におけるホットスボ・ントの
発生を防止する. なお、ポリシリコン抵抗体21の長さQと幅Wは抵抗値
等により変化するが、たとえばe=10”−20μm,
w=2μmである.突起部22の幅Sは、たとえば約1
〜2μmで、その先端の幅広部分は数μm角の寸法であ
る.なお、左側のコンタクト窓24から左開にさらにポ
リシリコン抵抗体21に連続して、延長拡大された突起
部25が図示されている.この突起部25も1r4のみ
で電流通路に接続され、他端は浮潴状態にあるので、電
流導体としては実質的に寄与せず、突起部22と同様な
放熱体として働く.第2図では放熱体となるポリシリコ
ン抵抗体の突起部22と25を両方形成した例を図示し
たが、いずれかの一方の放熟体のみでもよく、また、図
示のように両方の放熱体を形威してもよい.但し、突起
部25のみの場合には、ジュール熱の発生部より離れて
いるので熱抵抗が高くなり易い.放熱面積は突起部22
の場合より広くするのが望ましい. 第3図には、本発明の別の実施例の半導体装置の構造を
示す.この実施例では、たとえば電源VCCに接続され
る^1金属配線36から2つのポリシリコン抵抗体31
a、3lbを介してA1金属配線33a、33bに電圧
を供給する楕造である.ポリシリコン抵抗体31a、3
lbは突起部となるポリシリコン共通部32に連続して
いる.金属配線36はコンタクト窓35を介してポリシ
リコン共通部32とオーミックコンタクトされる.ポリ
シリコン共通部32は電気抵抗を構成するための帯状領
域31a、3lbに接続され、十分な放熱作用を持たせ
るように十分広く形成されている.第3図では1つのポ
リシリコン共通部32が2つの帯状領域31a、3lb
に接続しているが、それ以上の帯状領域を並列に接続し
てもよい.コンタクト窓35を各帯状領域31a、3l
bに十分近付け、図中縦方向に細長い形状の1つの窓領
域としてもよい.共通部32のみでは十分な放熱性能が
得られない場合には、さらに第2図のように、抵抗体3
1aあるいは3lbの中間部に突起部を形成して放熱を
促進してもよい. 第4図(A)、(B)、(C)はそれぞれ本発明のさら
に他の実施例の半導体装置のポリシリコン抵抗体の部分
の構造を示す.いずれもポリシリコン抵抗体の中間部の
側部に突起部を複数形成して、放熱体を形成する楕造で
ある. 第4図(A)のものは、ポリシリコン抵抗体41の同一
箇所の両開に放熱用の突起部42a、42bを形成して
いる.たとえば、ポリシリコン抵抗体41の中央位置か
ら両側に突出させる.第4図(B)のものは、ポリシリ
コン抵抗体41の片開に放熱用の突起部42a、42b
を形成している.片側には他の構造等が存在して放熱用
の突起部を作りにくい場合等に採用できる.第4図(C
)のものは、ポリシリコン抵抗体41の両側に放熱用の
突起部42a〜42eを互い違いになるように形成して
いる.ポリシリコン抵抗体の長さ方向に沿ってなるべく
均等に放熟手段を設けたい場合等に採用できる. 以上述べた構造の半導体装置は全てポリシリコン抵抗体
のバターニングの際のパターンを変更するのみで、他は
従来と同様の製造法で製造可能である. 次に2第5図は本発明の半導体装置のさらに他の実施例
を示す.ポリシリコン抵抗体5lは両端部が金属配線5
3とコンタクト窓54でオーミックコンタクトされる.
さらに、金属ダミー電極52a、52bがポリシリコン
抵抗体51の中間部の上に形成され、抵抗体51とコン
タクト窓55a、55bにおいてコンタクトされる.こ
のダミ−t極52a、52bは酸化シリコン層上にポリ
シリコン抵抗体5lを形成した後、シリコン酸化膜を形
成し、このシリコン酸化膜にコンタクト窓54を開ける
際にコンタクト窓55a、55bも開口し、A1金属層
を形或して金属配線53を形成する工程で同時にダミー
電極52a、52bもパターニングすることで形成でき
る.ダミー電極52a、52bは1m所でのみポリシリ
コン抵抗体51とコンタクトするので、電流通路として
は作用せず、熱的コンタクトを介して放熱体として作用
し、抵抗体51でのホットスポットの発生を防止する.
タミー電極の本数や大きさは、必要な放熱量を考慮して
決定される.なお、熱伝導が低下するが、コンタクト窓
55aを省略することも可能である. 第6図(A)、(B)は本発明の半導体装置のさらに別
の実施例を示す.第1図(B)と同様のポリシリコン抵
抗体の長さ方向に沿った断面図で説明する.第6図の実
施例においては、ポリシリコン抵抗体61に放熱体を設
ける代わりに、放熱手段として熱伝導の非常によいシリ
コン基板にポリシリコン抵抗体61自体を近接させて放
熱しようとするものである. 第6図(A>において、シリコン基板67の上に熱酸化
等によって酸化シリコン層68が形成される.rli化
シリコン層68の1部を選択エッチングし、続いて薄い
酸化膜を形成すること等によって、酸化シリコン層68
の厚みを部分的に他よりも薄くする.さらに、酸化シリ
コン層68の上にポリシリコン抵抗体61を形成し、絶
縁膜69で被覆する.コンタクト窓を開口した後、ポリ
シリコン抵抗体61にオーミックコンタクトする金属配
fi63とその他の配線66を^1スパッタリング等に
よって形成し、パターニング後、PSG等の絶縁層69
゜で覆う.さらにその上に、他の金属配線66゜を形成
する.従って、ポリシリコン抵抗体61は酸化シリコン
層68の薄い部分でシリコン基板67に接近する.抵抗
体61とシリコン基板67との間は、熱抵抗が低くなる
ので、酸化シリコン層68の薄い部分でポリシリコン抵
抗体6lで発生した熟は容易にシリコン基板67に放熱
される.その結果、゛ホットスポットの発生が防止され
る. 第6図(B)の実施例では、基本的には第6図(A)と
同様に製造されるが、第6図(B)では、シリコン基板
67の上のシリコン酸化層68の1部は完全に除去され
て、シリコン基板67が露出される.従って、ポリシリ
コン抵抗体61から基板67への放熱はさらによくなる
.但し、ポリシリコン抵抗体61と接触する基板67の
接触部は接触しても半導体装置の機能として問題のない
領域にする.たとえば、その接触部分を電気的に浮いた
領域、たとえばpn接合や誘電体領域によって電気的に
分離された分離領域とする.以上実施例に沿って、本発
明を説明したが、本発明はこれらに限定されるものでは
ない.たとえば、種々の改良、変更、組み合わせ等が可
能なことは当業者に自明であろう. たとえば、金属配線としてA1以外の金属を用いること
、ダミー電極.としてポリシリコン領域を用いること、
ポリシリコン抵抗体を金属配線の上に形成すること等が
可能なことは当業者に自明であろう. [発明の効果〕 以上説明したように、本発明によれば、多結晶半導体抵
抗体に放熱手段を設けたことにより、多結晶半導体抵抗
体で発生する熱が効果的に放熱される.このため、ホッ
トスポットの発生が効果的に防止できる. ホットスポット発生の防止により、エレクトロマイグレ
ーションによる配線の経時変化または抵抗体の抵抗値の
経時変化を防止できる.小型化が容易で、しかも信頼性
の高い半導体装置を提供することができる.
[Detailed Description of the Invention] [Summary] Regarding a semiconductor device using a polycrystalline semiconductor, such as polysilicon, as an electrical resistor, in a semiconductor device using polysilicon as an electrical resistor, there is A semiconductor substrate, a first insulating film formed on the semiconductor substrate, a polycrystalline semiconductor resistor formed on the insulating film and defining a current path connected between a pair of t-poles;
and a second insulating film formed on the polycrystalline semiconductor resistor, and the polycrystalline semiconductor resistor is formed so as to have a protrusion for loosening at its l portion. [Industrial Application Field] The present invention relates to a semiconductor device, and particularly to a semiconductor device using a polycrystalline semiconductor, such as polysilicon, as an electrical resistor. In this specification, the term "polycrystalline semiconductor" refers to a concept in contrast to single-crystalline semiconductors, and includes so-called "amorphous semiconductors." [Prior Art J] In the manufacture of semiconductor integrated circuit v8 devices, resistance elements are formed in a silicon substrate using an impurity diffusion process. For example, a p-type stripe region is diffused into an n-type semiconductor layer, and a pair of metal electrodes are connected to both ends of the p-type stripe region. pntH between the n-type semiconductor layer and the p-type stripe region
biasing the n-type semiconductor layer so as to reverse bias the
When a current is caused to flow between a pair of metal t-poles, the p-type stripe region can be used as a resistance element having a nearly constant resistance value. Joule heat is generated in a resistive element when current flows through it. The bulk diffused resistor as described above is surrounded by silicon with high thermal conductivity, so the generated heat is transferred to the surrounding bulk silicon and radiated. For this reason, heat generation from the resistive element did not pose a particular problem. Incidentally, as the degree of integration of semiconductor integrated circuit devices improves, the density of integrated circuits increases. For this reason, it is desired that the active and passive elements that make up the circuit become smaller and smaller. It is also desired that resistive elements be made smaller and have higher resistance. In recent years, the use of resistors using polycrystalline silicon (polysilicon) has been progressing. Polysilicon can be formed on a substrate, increasing the area utilization of the substrate. For example, a steel structure called ESPER and its process were developed. In this structure, the emitter lead electrode and base lead electrode are formed from polysilicon, which is a polycrystalline semiconductor. This polysilicon process can simultaneously form a resistor. A high-resistance polysilicon resistor is formed at the same time as the emitter (or base) extraction electrode, and used as a load resistor. By using polycrystals, high resistivity regions can be formed,
Since the surrounding area is covered with an oxide film, etc., isolation using a pn junction such as a diffused resistor is not required. As described above, polysilicon resistors have the advantage of being suitable for miniaturization, and from the viewpoint of high density, polysilicon resistors are increasingly being used. [Problem to be Solved by the Invention 1] However, since the polysilicon resistor is formed on a silicon oxide film that has poor heat conductivity, hot spots, which are localized high-temperature areas, occur due to the resistor's completeness. This hot spot excessively heats the upper layer wiring, such as the ^1 wiring, which is wired above the resistor via an insulating layer, making it easy to cause disconnection of the ^1 wiring due to electromigration. This shortens the lifespan of semiconductor devices and reduces reliability. Furthermore, the rise in temperature of the resistor due to hot spots causes fluctuations in the resistance value of the resistor itself. Generally speaking, the resistance value of a semiconductor resistor decreases as the temperature rises, and as the temperature decreases, the resistance value increases and returns to its original value. However, if the temperature becomes too high, the resistance value will not return to its original value (generally becomes higher) even when the temperature drops, causing a change in resistance value over time. These phenomena are undesirable because they cause a decrease in the reliability of manufactured semiconductor devices. Electromigration will be specifically explained below with reference to the drawings. FIG. 7(A) is a plan view of a semiconductor device using a conventional polysilicon resistor, and FIG. 7(B) is a plan view of a semiconductor device using a conventional polysilicon resistor.
A sectional view taken along line II-II' of A) is shown. In FIG. 7, both ends of a polysilicon resistor 71 are in ohmic contact with metal wiring (^1) 73 through contact windows 74. Another ^1 wiring 76 is formed on the silicon oxide insulating layer 79 above the resistor 7l so as to intersect with the polysilicon resistor 71. Upper and lower layers 78, 7 of the resistor 71
Since 9 is a silicon oxide layer, heat conduction is poor, and resistor 7
1 forms a hot spot when heated by Joule ripening. Eventually, the heat heats the A1 wiring 76 at the top. When a current flows through the matured A1 wiring 76, electromigration occurs, and the 8lt pole 76 gradually becomes thinner and eventually becomes disconnected as shown in FIG.
Similarly, electromigration occurs even when the A1 wiring is 76° without the 76 wiring. The purpose of the present invention is to solve the problems of electromigration of metal wiring due to hot spots or changes in the resistance value of the resistor in semiconductor devices that use polycrystalline semiconductors, particularly polysilicon, as electrical resistors, and to provide highly reliable semiconductor devices. The purpose is to provide equipment. [Means for Solving the Problems] According to the present invention, a ripening means is provided in a polycrystalline semiconductor resistance element formed on a semiconductor substrate. Figure 1 is a diagram explaining the principle of the present invention. Both ends of the polysilicon resistor 1 are in ohmic contact with a metal wiring 3 such as ^1 through a contact window 4. The resistor 1 is shaped by providing a conductive protrusion 2 on one part thereof. Note that FIG. 1(B) shows a cross-sectional view taken along line II' in FIG. 1(A). An oxide film 8 is formed on a semiconductor substrate 7 made of Si or the like, and a resistor 1 made of polysilicon is formed thereon. Both ends of the polysilicon resistor 1 are in ohmic contact with a wiring layer 3 such as ^1. An insulating film 9 is formed to cover these conductors 1 and 3. Other wiring lines 6 and 6° are formed on the insulating film 9. [Function] The protrusion 2 is birch conductive and has a higher electrical strength than the surrounding insulators. The Joule ripening generated in the resistor 1 is released through this protrusion 2. By appropriately providing the projections that serve as heat radiators, the portions of the resistor 1 through which current flows are prevented from ripening, and the generation of hot spots is prevented. The dimensions, shape, and area of the protrusion 2 are adjusted as appropriate depending on the amount of heat dissipation required for each semiconductor device. While adopting an elliptical structure using polycrystalline semiconductor resistive elements that is advantageous for high density, it prevents hot spots from occurring in the polycrystalline semiconductor resistive elements and prevents disconnection of metal wiring due to electromigration and damage to resistors. Changes in resistance can be prevented. [Examples] Examples of the present invention will be described below with reference to the drawings. In the drawings of the actual knee example shown below, the upper layer ^1 wiring 6, 6° shown in Fig. 1(B) is omitted for the sake of simplification of the drawings. FIG. 2 is a plan view showing the top of a semiconductor device according to an embodiment of the present invention. Its cross-sectional structure is similar to that in Figure 1 (B). It can be manufactured using the same manufacturing process as conventional technology. A silicon oxide layer is formed on the substrate by thermally oxidizing the surface of the silicon substrate, and then thermal decomposition CVD,
A polysilicon layer is formed by plasma CVD or the like. A polysilicon resistor 21 is patterned from this polysilicon layer. At this time, the protrusion 22 protruding from the polysilicon resistor 21 is also patterned. An insulating film is formed on the polysilicon resistor 21, and contact windows are opened in the insulation at both ends of the polysilicon resistor 21.
A wiring layer 23 such as A1 is formed on this layer and patterned. Both ends of the polysilicon resistor 21 are in ohmic contact with the ^1 metal wiring 23 through contact windows 24. The polysilicon resistor 21 is patterned with protrusions 22 provided on the sides of the middle part (where current flows) sandwiched by the contact windows 24. Since the projection 22 is connected to the current path only at one end and protrudes while the other end remains floating, it does not substantially function as a current path (resistance). However, since it is physically and thermally continuous, it acts as a heat dissipator against the growth in the polysilicon resistor 21 and prevents the occurrence of hot spots in the polysilicon resistor 21. Note that the length Q and width W of the polysilicon resistor 21 vary depending on the resistance value, etc., but for example, e=10"-20 μm,
w=2μm. The width S of the protrusion 22 is, for example, about 1
~2 μm, and the wide part at the tip is several μm square. Note that an extended and enlarged protrusion 25 is shown extending from the left contact window 24 to the left and continuing to the polysilicon resistor 21. This protrusion 25 is also connected to the current path only through 1r4, and the other end is in a floating state, so it does not substantially contribute as a current conductor, but functions as a heat sink similar to the protrusion 22. Although FIG. 2 shows an example in which both protrusions 22 and 25 of the polysilicon resistor serving as a heat sink are formed, only one of the protrusions 22 and 25 may be formed, or both heat sinks may be formed as shown in the figure. You can also express it. However, in the case of only the protrusion 25, the thermal resistance tends to be high because it is located away from the Joule heat generation area. The heat dissipation area is the protrusion 22
It is desirable to make it wider than in the case of . FIG. 3 shows the structure of a semiconductor device according to another embodiment of the present invention. In this embodiment, for example, two polysilicon resistors 31 are connected to the ^1 metal wiring 36 connected to the power supply VCC.
This is an elliptical structure that supplies voltage to the A1 metal wirings 33a and 33b through the A1 metal wiring lines 33a and 33b. Polysilicon resistor 31a, 3
lb is continuous with the polysilicon common portion 32 which becomes the protrusion. The metal wiring 36 is in ohmic contact with the polysilicon common portion 32 via the contact window 35. The polysilicon common portion 32 is connected to the band-shaped regions 31a and 3lb for forming electrical resistance, and is formed sufficiently wide to provide sufficient heat dissipation. In FIG. 3, one polysilicon common portion 32 is divided into two strip regions 31a and 3lb.
However, more strip-shaped areas may be connected in parallel. The contact window 35 is connected to each strip area 31a, 3l.
It may be placed sufficiently close to b, and it may be one window area that is elongated in the vertical direction in the figure. If sufficient heat dissipation performance cannot be obtained with the common portion 32 alone, as shown in FIG.
A protrusion may be formed in the middle part of 1a or 3lb to promote heat dissipation. FIGS. 4A, 4B, and 4C each show the structure of a polysilicon resistor portion of a semiconductor device according to still another embodiment of the present invention. Both have an elliptical shape with multiple protrusions formed on the sides of the middle part of the polysilicon resistor to form a heat sink. In the case shown in FIG. 4A, heat dissipation protrusions 42a and 42b are formed at both ends of the polysilicon resistor 41 at the same location. For example, it may be made to protrude from the center of the polysilicon resistor 41 to both sides. The one shown in FIG. 4(B) has protrusions 42a and 42b for heat dissipation on one side of the polysilicon resistor 41.
is formed. This can be used when there is another structure on one side and it is difficult to create a protrusion for heat dissipation. Figure 4 (C
), heat radiation protrusions 42a to 42e are formed alternately on both sides of a polysilicon resistor 41. This can be used when it is desired to provide the ripening means as evenly as possible along the length of the polysilicon resistor. All of the semiconductor devices with the structure described above can be manufactured using conventional manufacturing methods, except for changing the patterning pattern of the polysilicon resistor. Next, FIG. 2 shows still another embodiment of the semiconductor device of the present invention. The polysilicon resistor 5l has metal wiring 5 at both ends.
3 and the contact window 54 make ohmic contact.
Furthermore, metal dummy electrodes 52a, 52b are formed on the intermediate portion of polysilicon resistor 51 and are contacted with resistor 51 at contact windows 55a, 55b. These dummy T-poles 52a and 52b are formed by forming a polysilicon resistor 5l on a silicon oxide layer, and then forming a silicon oxide film, and when opening a contact window 54 in this silicon oxide film, contact windows 55a and 55b are also opened. However, the dummy electrodes 52a and 52b can be formed by patterning at the same time as the process of forming the A1 metal layer and forming the metal wiring 53. Since the dummy electrodes 52a and 52b are in contact with the polysilicon resistor 51 only at a distance of 1 m, they do not act as current paths, but act as heat sinks through thermal contact, thereby preventing the generation of hot spots in the resistor 51. To prevent.
The number and size of tummy electrodes are determined by considering the required amount of heat dissipation. Note that it is also possible to omit the contact window 55a, although heat conduction will be reduced. FIGS. 6(A) and 6(B) show still another embodiment of the semiconductor device of the present invention. This will be explained using a cross-sectional view along the length of a polysilicon resistor similar to FIG. 1(B). In the embodiment shown in FIG. 6, instead of providing a heat dissipation body for the polysilicon resistor 61, the polysilicon resistor 61 itself is placed close to a silicon substrate with very good thermal conductivity as a heat dissipation means to dissipate heat. be. In FIG. 6 (A>), a silicon oxide layer 68 is formed on a silicon substrate 67 by thermal oxidation or the like. A part of the rli silicon layer 68 is selectively etched, and then a thin oxide film is formed. The silicon oxide layer 68
Make the thickness of some parts thinner than others. Further, a polysilicon resistor 61 is formed on the silicon oxide layer 68 and covered with an insulating film 69. After opening the contact window, a metal wiring 63 and other wiring 66 that make ohmic contact with the polysilicon resistor 61 are formed by sputtering or the like, and after patterning, an insulating layer 69 such as PSG is formed.
Cover with °. Furthermore, another metal wiring 66° is formed on top of that. Therefore, the polysilicon resistor 61 approaches the silicon substrate 67 through the thin portion of the silicon oxide layer 68. Since the thermal resistance between the resistor 61 and the silicon substrate 67 is low, heat generated in the polysilicon resistor 6l in the thin portion of the silicon oxide layer 68 is easily radiated to the silicon substrate 67. As a result, the occurrence of hot spots is prevented. The embodiment of FIG. 6(B) is basically manufactured in the same manner as that of FIG. 6(A), but in FIG. 6(B), a part of the silicon oxide layer 68 on the silicon substrate 67 is manufactured. is completely removed to expose the silicon substrate 67. Therefore, heat radiation from the polysilicon resistor 61 to the substrate 67 is further improved. However, the contact portion of the substrate 67 that comes into contact with the polysilicon resistor 61 is designed to be an area where contact will not cause any problem in terms of the functionality of the semiconductor device. For example, the contact portion may be an electrically floating region, such as a pn junction or an isolation region electrically separated by a dielectric region. Although the present invention has been described above with reference to Examples, the present invention is not limited thereto. For example, it will be obvious to those skilled in the art that various improvements, changes, combinations, etc. are possible. For example, using a metal other than A1 as the metal wiring, dummy electrodes. using a polysilicon region as
It will be obvious to those skilled in the art that it is possible to form a polysilicon resistor on top of metal wiring. [Effects of the Invention] As explained above, according to the present invention, heat generated in the polycrystalline semiconductor resistor is effectively radiated by providing the heat radiation means in the polycrystalline semiconductor resistor. Therefore, the occurrence of hot spots can be effectively prevented. By preventing the occurrence of hot spots, it is possible to prevent changes in wiring over time or changes in the resistance value of resistors over time due to electromigration. It is possible to provide a semiconductor device that is easy to downsize and has high reliability.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図(A)、(B)は本発明の原理説明図であり、第
l図(A>は平面図、第1図(B)は断面図、 第2図は本発明の実施例による半導体装置の構造を示す
平面図、 第3図は本発明の他の実施例による半導体装置の構造を
示す平面図、 第4図(A)〜(C)は本発明のさらに他の実施例によ
る半導体装置の梢造を示す平面図、第5図は本発明のさ
らに他の実施例による半導体装置の横造を示す平面図、 第6図(A)、(B)は本発明のさらに他の実施例によ
る半導体装置の梢遣を示す断面図、第7図(A)、(B
)は従来の技術による半導体装置の楕造を示す平面図と
断面図、 第8図は従来の技術による半導体装置のポリシリコン抵
抗体上方の金属配線が断線した状態を示す図である. 図において、 1,21.31a, 71 2  22,25, 3,  23. 73 4 74 6. 6゜ 24 , 3lb.  41.  51, ポリシリコン抵抗体 32.42a〜42e ポリシリコン突起部 33a,33b,36,53.63 金属配線ないし電極 34a..34b,35、54,55、コンタクト窓 66,66゜76.76’ 他の配線 半導体基板 酸化膜 絶縁膜 ダミーt極 6 1 , (A)平面図 (B)断面図 第1図 実施例による半導体装置 第2図 実施例による半導体装置 第3図 実施例によるポリノリクン抵抗体 第4図 54.55:コンタクト窓 実施例による半導体装置 第5図 (B)その2 第6図
Figures 1 (A) and (B) are diagrams explaining the principle of the present invention, Figure 1 (A> is a plan view, Figure 1 (B) is a sectional view, and Figure 2 is an embodiment of the present invention FIG. 3 is a plan view showing the structure of a semiconductor device according to another embodiment of the present invention, and FIGS. 4(A) to (C) are according to still another embodiment of the present invention. FIG. 5 is a plan view showing a horizontal structure of a semiconductor device according to still another embodiment of the present invention, and FIGS. FIGS. 7A and 7B are cross-sectional views showing the top of the semiconductor device according to the embodiment.
) are a plan view and a cross-sectional view showing the elliptical structure of a semiconductor device according to the conventional technology, and Figure 8 is a diagram showing a state in which the metal wiring above the polysilicon resistor of the semiconductor device according to the conventional technology is disconnected. In the figure: 1, 21.31a, 71 2 22, 25, 3, 23. 73 4 74 6. 6゜24, 3lb. 41. 51, polysilicon resistor 32.42a-42e polysilicon protrusion 33a, 33b, 36, 53.63 metal wiring or electrode 34a. .. 34b, 35, 54, 55, contact window 66, 66° 76.76' Other wiring semiconductor substrate oxide film insulating film dummy t-pole 6 1 , (A) Plan view (B) Cross-sectional view Fig. 1 Semiconductor according to the embodiment 54.55: Semiconductor device according to the contact window embodiment FIG. 5 (B) Part 2 FIG. 6

Claims (1)

【特許請求の範囲】 (1)、半導体基板(7)と、 前記半導体基板の上に形成された第1の絶縁膜(8)と
、 前記絶縁膜(8)の上に形成され、1対の電極(3)間
に接続される電流通路を画定する多結晶半導体抵抗体(
1)と、 前記多結晶半導体抵抗体(1)の上に形成された第2の
絶縁膜(9)とを有し、 前記多結晶半導体抵抗体(1)はその1部に放熱のため
の突起部(2)を設けている 半導体装置。 (2)、前記突起部(2)は前記抵抗体(1)と同一材
料で該抵抗体と一体に形成され、その1端のみが前記電
流通路に電気的に接続された多結晶半導体領域を含む請
求項1記載の半導体装置。 (3)、前記突起部(2)は前記多結晶半導体抵抗体(
1)の1箇所と接触し、この接触部分以外の部分は絶縁
された金属体領域を含む請求項1記載の半導体装置。 (4)、半導体基板(67)と、 前記半導体基板(67)の上に形成された第1の絶縁膜
(68)と、 前記絶縁膜(68)の上に形成され、一対の配線(63
)間に接続された多結晶半導体抵抗体(61)と、 前記多結晶半導体抵抗体(61)の上に形成された第2
の絶縁膜(69)とを有し、 前記多結晶半導体抵抗体(61)はその1部において他
の部分よりも前記半導体基板(67)により接近する部
分を有する 半導体装置。 (5)、前記第1の絶縁膜(68)はその厚みが他の部
分より薄い部分を有し、 該薄い部分の上に前記多結晶半導体抵抗体 (61)が形成されている請求項4記載の半導体装置。 (6)、前記第1の絶縁膜(68)は一部が除去されて
前記半導体基板(67)が露出し、前記多結晶半導体抵
抗体(61)の一部が前記露出した半導体基板(67)
と接触して形成されている請求項4記載の半導体装置。
[Scope of Claims] (1) A semiconductor substrate (7), a first insulating film (8) formed on the semiconductor substrate, and a pair of insulating films formed on the insulating film (8). A polycrystalline semiconductor resistor (
1), and a second insulating film (9) formed on the polycrystalline semiconductor resistor (1), and the polycrystalline semiconductor resistor (1) has a heat dissipation layer in a part thereof. A semiconductor device provided with a protrusion (2). (2) The protrusion (2) is made of the same material as the resistor (1) and is formed integrally with the resistor, and only one end thereof has a polycrystalline semiconductor region electrically connected to the current path. 2. The semiconductor device according to claim 1. (3), the protrusion (2) is the polycrystalline semiconductor resistor (
2. The semiconductor device according to claim 1, wherein the semiconductor device includes a metal region that is in contact with one of the points in step 1) and is insulated from other parts than the contact portion. (4) a semiconductor substrate (67); a first insulating film (68) formed on the semiconductor substrate (67); and a pair of wiring lines (63) formed on the insulating film (68).
), and a second polycrystalline semiconductor resistor (61) formed on the polycrystalline semiconductor resistor (61).
an insulating film (69), wherein a portion of the polycrystalline semiconductor resistor (61) is closer to the semiconductor substrate (67) than other portions. (5) The first insulating film (68) has a portion that is thinner than other portions, and the polycrystalline semiconductor resistor (61) is formed on the thin portion. The semiconductor device described. (6) A portion of the first insulating film (68) is removed to expose the semiconductor substrate (67), and a portion of the polycrystalline semiconductor resistor (61) is removed from the exposed semiconductor substrate (67). )
5. The semiconductor device according to claim 4, wherein the semiconductor device is formed in contact with.
JP31030989A 1989-11-29 1989-11-29 Semiconductor device Pending JPH03171657A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP31030989A JPH03171657A (en) 1989-11-29 1989-11-29 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP31030989A JPH03171657A (en) 1989-11-29 1989-11-29 Semiconductor device

Publications (1)

Publication Number Publication Date
JPH03171657A true JPH03171657A (en) 1991-07-25

Family

ID=18003673

Family Applications (1)

Application Number Title Priority Date Filing Date
JP31030989A Pending JPH03171657A (en) 1989-11-29 1989-11-29 Semiconductor device

Country Status (1)

Country Link
JP (1) JPH03171657A (en)

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH04177871A (en) * 1990-11-13 1992-06-25 Nec Corp Semiconductor integrated circuit
JPH07176690A (en) * 1993-12-17 1995-07-14 Nec Corp Fabrication of semiconductor device
WO2005013368A1 (en) * 2003-07-31 2005-02-10 Fujitsu Limited Semiconductor device
KR100752907B1 (en) * 2005-11-25 2007-08-28 후지쯔 가부시끼가이샤 Semiconductor device
US8298904B2 (en) 2011-01-18 2012-10-30 International Business Machines Corporation Compact thermally controlled thin film resistors utilizing substrate contacts and methods of manufacture
US8652922B2 (en) 2011-01-18 2014-02-18 International Business Machines Corporation Compact thermally controlled thin film resistors utilizing substrate contacts and methods of manufacture
US10134511B2 (en) 2015-03-26 2018-11-20 Seiko Epson Corporation Resistance element, electrostatic protection circuit, temperature detection circuit, and electro-optic apparatus

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01202854A (en) * 1988-02-09 1989-08-15 Fujitsu Ltd Semiconductor integrated circuit

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01202854A (en) * 1988-02-09 1989-08-15 Fujitsu Ltd Semiconductor integrated circuit

Cited By (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH04177871A (en) * 1990-11-13 1992-06-25 Nec Corp Semiconductor integrated circuit
JPH07176690A (en) * 1993-12-17 1995-07-14 Nec Corp Fabrication of semiconductor device
WO2005013368A1 (en) * 2003-07-31 2005-02-10 Fujitsu Limited Semiconductor device
JPWO2005013368A1 (en) * 2003-07-31 2006-09-28 富士通株式会社 Semiconductor device
US7365397B2 (en) 2003-07-31 2008-04-29 Fujitsu Limited Semiconductor device
JP4493596B2 (en) * 2003-07-31 2010-06-30 富士通マイクロエレクトロニクス株式会社 Semiconductor device
KR100752907B1 (en) * 2005-11-25 2007-08-28 후지쯔 가부시끼가이샤 Semiconductor device
US8298904B2 (en) 2011-01-18 2012-10-30 International Business Machines Corporation Compact thermally controlled thin film resistors utilizing substrate contacts and methods of manufacture
US8541864B2 (en) 2011-01-18 2013-09-24 International Business Machines Corporation Compact thermally controlled thin film resistors utilizing substrate contacts and methods of manufacture
US8652922B2 (en) 2011-01-18 2014-02-18 International Business Machines Corporation Compact thermally controlled thin film resistors utilizing substrate contacts and methods of manufacture
US10134511B2 (en) 2015-03-26 2018-11-20 Seiko Epson Corporation Resistance element, electrostatic protection circuit, temperature detection circuit, and electro-optic apparatus

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