JPH07120704B2 - Method for manufacturing semiconductor device - Google Patents

Description

The present invention relates to a method for manufacturing a semiconductor device using dielectric isolation, and more particularly to a trench isolation method.

[Conventional technology]

Conventionally, the trench isolation process is shown in FIG.
As shown in (c), an N ⁺ type Umegome layer 2 and an N type epitaxial layer 3 are formed on a P type Si substrate 1, and then a groove 5 for isolation is formed, and an oxide film 4 is formed inside the groove. Then, a P ⁺ type channel stopper 7 is formed on the P type Si substrate 1 at the bottom of the groove by using the ion implantation method.

Further, after filling the inside of this groove with polysilicon 8, an oxide film 9 is formed on the surface of this polysilicon to form a P-type base layer.
A method of forming a semiconductor element by forming the 10, N ⁺ type emitter layer 11 and the electrode 12 has been adopted.

[Problems to be solved by the invention]

In the conventional isolation process described above, when the P ⁺ type channel stopper 7 is formed in the P type Si substrate 1 at the bottom of the groove 5 by the ion implantation method, the angle of ion implantation is over the entire surface of the Si substrate 1 and the Si substrate 1 is formed. On the other hand, it is difficult to implant completely vertically, and the P-type region 21 is formed in the N-type epitaxial layer. The P-type region 21 collides with the N ⁺ -type buried layer 2 to cause a withstand voltage failure and increase the base-collector capacitance, which has been a serious problem for speeding up the NPN transistor.

An object of the present invention is to solve such a problem, and by forming polysilicon on the groove side surface, it is possible to prevent boron from being injected into the epitaxial layer on the groove side surface, and therefore, withstand voltage failure and base. It is an object of the present invention to provide a method of manufacturing a semiconductor device that can prevent an increase in collector-to-collector capacitance.

[Means for solving problems]

According to the method of manufacturing a semiconductor device of the present invention, a high-concentration layer of another conductivity type is formed on a semiconductor substrate of one conductivity type, and another high-concentration impurity is introduced to form a high-concentration layer. A first step of forming an epitaxial layer containing a low concentration impurity of another conductivity type on the concentration layer, and forming a groove from the surface of the epitaxial layer to the semiconductor substrate, and forming a groove in the epitaxial layer by the groove. A second step of separating into an insulating region, a third step of forming an insulating film on the surface of the epitaxial layer and inside the groove, and a third step of forming a nitride film only on the side surface of the groove on the insulating film inside the groove; A fourth step of forming a high concentration layer of one conductivity type on the semiconductor substrate at the bottom of the groove by implantation, and filling the inside of the groove with polycrystalline silicon and forming an insulator on the polycrystalline silicon. , In the island area Characterized in that it comprises a fifth step of forming a conductive element.

〔Example〕

 Next, the present invention will be described with reference to the drawings.

1A to 1C are cross-sectional views illustrating a reference example related to the present invention in the order of steps.

First, impurities such as As and Sb are diffused on the surface of the P-type Si substrate 1 to obtain an impurity concentration of about 10 ¹⁹ to 10 ²⁰ cm ⁻³ and a depth of about 1 μm.
The N ⁺ type buried layer 2 is formed. Next, the N-type epitaxial layer 3 having a thickness of about 1 Ω · cm is formed to have a thickness of about 1.5 to 2 μm. A groove 5 for insulation separation is formed by etching until it reaches the P-type Si substrate 1, and an oxide film 4 is further formed by a thermal oxidation method or a chemical vapor deposition method (FIG. 1 (a)). .

Then, polysilicon is formed on the surface of the air plate to a thickness not completely filling the groove 5, and polysilicon 6 is formed only on the side surface of the groove by anisotropic dry etching, and ¹¹ B ⁺ is ion-implanted. As a result, the P ⁺ type channel stopper 7 is formed on the P type Si substrate 1 at the bottom of the groove (FIG. 1 (b)).

At this time, since it is difficult to implant ions completely perpendicularly to the substrate 1, the ions are also implanted into the side surfaces of the trench, but by making the polysilicon and the oxide film have appropriate thicknesses, it is possible to Can be prevented from being ion-implanted.

After that, the inside of the groove is filled with polysilicon 8 to form an oxide film 9 on the surface of the polysilicon 6, and then a P-type base layer 10, an N ⁺ -type emitter layer 11 and an electrode 12 are formed on the N-type epitaxial layer 3. An NPN transistor is formed (Fig. 1 (c)).

Further, although the NPN transistor has been described in FIG. 1, it is obvious that other elements such as a PNP transistor, a resistor, a CMOS, etc. can be applied.

2 (a) to (c) are cross-sectional views illustrating an embodiment of the present invention in the order of steps. In this embodiment, similarly to the reference example shown in FIG. 1, after forming the separation groove 5, a nitride film is formed on the surface of the substrate 1 and the side surface of the groove 5 is formed by anisotropic dry etching. Only the nitride film 15 is formed.

Thereafter, similarly to the reference example, ¹¹ B ⁺ is ion-implanted to form a P ⁺ type channel stopper 7, polysilicon 8 is filled in the groove, and a semiconductor element is formed in the N type epitaxial layer 3.

In this embodiment, the side surface inside the groove is made of an oxide film and a nitride film, which is advantageous in reducing the parasitic capacitance.

〔The invention's effect〕

As described above, according to the present invention, when the P ⁺ -type channel stopper is formed by ion implantation, boron is prevented from being implanted into the N-type epitaxial layer on the side surface of the groove, thereby preventing breakdown voltage and further improving parasitic capacitance. The effect of increasing the speed of the semiconductor element is obtained by preventing the increase of

[Brief description of drawings]

1 (a) to 1 (c) are cross-sectional views of an element for explaining the present invention in the order of steps, FIGS. 2 (a) to 2 (c) are cross-sectional views in the order of steps of one embodiment of the present invention, and FIG. (a)-(c) is sectional drawing which showed the conventional manufacturing method in order of process. 1 ... P-type Si substrate, 2 ... N ⁺ type buried layer, 3 ... N-type epitaxial layer, 4 ... Oxide film, 5 ... Groove, 6,8 ... Polysilicon, 7 ... P ⁺ Type channel stopper, 9 ... Oxide film, 10 ... P-type base layer, 11 ... N ⁺ type emitter layer, 12 ...
... electrode, 15 ... nitride film, 21 ... P-type region.

Claims (1)

[Claims] 1. A high-concentration layer is formed by introducing a high-concentration impurity of another conductivity type onto a semiconductor substrate of one conductivity type, and an epitaxial layer containing a low-concentration impurity of another conductivity type on the high-concentration layer. Forming a groove from the surface of the epitaxial layer to reach the semiconductor substrate, and separating the epitaxial layer into island regions by the groove; A third step of forming an insulating film inside the groove and further forming a nitride film only on the side surface of the groove on the insulating film inside the groove, and a high conductivity of one conductivity type on the semiconductor substrate at the bottom of the groove by ion implantation. A fourth step of forming a concentration layer, and a fifth step of filling the inside of the groove with polycrystalline silicon, forming an insulator on the polycrystalline silicon, and then forming a semiconductor element in the island region. Specially including The method of manufacturing a semiconductor device according to.