JPH07118702B2 - Data receiver - Google Patents

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data receiving device used for digital mobile communication and the like.

2. Description of the Related Art FIG. 2 shows the configuration of a conventional data receiving device. In FIG. 2, reference numeral 21 is a reception signal input terminal, and 22 is a reference signal oscillation circuit. A phase detection circuit 23 is connected to the reception signal input terminal 21 and the reference signal oscillation circuit 22. Reference numeral 24 is a clock reproduction circuit, which is connected to the phase detection circuit 23. A decoding circuit 25 is connected to the phase detection circuit 23 and the clock recovery circuit 24. Reference numeral 26 is a decoded data output terminal, which is connected to the decoding circuit 25. Reference numeral 27 is a reference frequency control circuit, which is connected to the phase detection circuit 23, the clock recovery circuit 24, and the reference signal oscillation circuit 22.

Next, the operation of the above conventional example will be described. In FIG. 2, when a received signal is input from the received signal input terminal 21, the reference signal oscillator circuit 22 outputs a frequency reference signal that is substantially equal to the carrier frequency of the received signal. The phase detection circuit 23 receives signals from the reception signal input terminal 21 and the reference signal oscillation circuit 22, extracts phase information contained in the reception signal, and outputs a quantized value of the phase information. The clock recovery circuit 24 detects the optimum identification time from the output of the phase detection circuit 23 and outputs it.
The decoding circuit 25 identifies the phase of the received signal from the output of the phase detection circuit 23 and the output of the clock recovery circuit 24 at the optimal identification time, and the phase is the most significant compared with the ideally transmitted phase. A code with a small phase difference is output as decoded data. The reference frequency control circuit 27 receives signals from the phase detection circuit 23 and the clock recovery circuit 24, similarly to the decoding circuit 25,
Two-stage determination is made as to whether the phase of the received signal is ideally transmitted at the optimum identification time, that is, "phase lead" or "phase delay". Then, as a result of the above determination, when the state is deflected to either state, the oscillation frequency of the reference signal oscillation circuit 2 is changed so as to cancel the state.

As described above, also in the above-mentioned conventional data receiving apparatus, it is possible to decode the data by causing the oscillation frequency of the reference signal oscillation circuit to follow the carrier frequency of the received signal.

However, in the above conventional data receiving apparatus, the frequency difference between the carrier frequency of the received signal and the oscillation frequency of the reference signal oscillation circuit 22 is in the "phase lead" state and the "phase delay" state. Since the reference signal oscillation circuit 22 is controlled so as to cancel the frequency difference by performing the discrimination in two stages, there is a problem that it takes a lot of time to obtain the matched frequency when the frequency difference is large.

The present invention solves such conventional problems,
An object of the present invention is to provide an excellent data receiving apparatus capable of instantaneously matching frequencies by performing control in proportion to the magnitude of frequency difference by adding phase likelihood information to conventional two-stage discrimination. It is what

Means for Solving the Problems To achieve the above object, the present invention provides a reference signal oscillation circuit having a frequency variable function for oscillating a frequency substantially equal to the carrier frequency of a received signal, and the output and reception of the reference signal oscillation circuit A phase detection circuit that detects the phase difference from the signal and quantizes and outputs the phase information of the received signal, and a clock regeneration circuit that obtains the optimum identification time from the output signal of the phase detection circuit,
A decoding circuit that determines the output of the phase detection circuit based on the optimum identification time and decodes the data, and the phase difference between the phase information obtained at the identification time and the phase information that should originally be transmitted are checked and transmitted. The phase likelihood detection circuit that outputs the likelihood of the data and whether the phase information obtained at the identification time is in the "leading" state or the "lagging" state with respect to the phase information to be originally transmitted Judgment, weighting “lead” or “lag” by the output of the phase likelihood detection circuit, and providing a reference frequency control circuit that detects and outputs the frequency difference from the deflection of “lead” or “lag” The carrier frequency of the received signal is tracked by rapidly detecting the difference between the carrier frequency and the frequency output from the reference signal oscillation circuit and changing the oscillation frequency of the reference signal oscillation circuit to eliminate the difference. Thing .

Action The present invention has the following actions due to the above configuration. That is, when the carrier frequency of the received signal and the oscillation frequency of the reference signal oscillation circuit are different and are in the "leading" or "lagging" state with respect to the ideal phase information,
"Advance" or "Delay" is weighted by the output of the phase likelihood detection circuit to detect the frequency difference promptly and to match the oscillation frequency of the reference signal oscillation circuit with the carrier frequency of the received signal at high speed. it can.

Embodiment FIG. 1 shows the structure of an embodiment of the present invention. In FIG. 1, reference numeral 1 is a reception signal input terminal. Reference numeral 2 is a reference signal oscillator circuit. Reference numeral 3 is a phase detection circuit, which is connected to the reception signal input terminal 1 and the reference signal oscillation circuit 2. Reference numeral 4 is a clock reproduction circuit, which is connected to the phase detection circuit 3. A decoding circuit 5 is connected to the phase detection circuit 3 and the clock recovery circuit 4. Decoded data output terminal 6 is connected to the decoding circuit 5. A phase likelihood detection circuit 7 is connected to the phase detection circuit 3 and the clock recovery circuit 4. A reference frequency control circuit 8 is connected to the phase detection circuit 3, the clock recovery circuit 4, the phase likelihood detection circuit 7, and the reference signal oscillation circuit 2.

Next, the operation of the above embodiment will be described. In the above embodiment, when the received signal is input from the received signal input terminal 1, the reference signal oscillator circuit 2 outputs a frequency substantially equal to the carrier frequency of the received signal. The phase detection circuit 3 receives the signals from the reception signal input terminal 1 and the reference signal oscillation circuit 2, extracts the phase information contained in the reception signal, and outputs the quantized value of the phase information. The clock recovery circuit 4 is the phase detection circuit 3
The optimum identification time is detected from the output of and output. The decoding circuit 5 identifies the phase of the received signal from the output of the phase detection circuit 3 and the output of the clock recovery circuit 4 at the optimal identification time, and the phase has the smallest phase difference with respect to the ideally transmitted phase. The code is output as decoded data. The phase likelihood detection circuit 7 discriminates the phase of the received signal from the output of the phase detection circuit 3 and the output of the clock recovery circuit 4 at the optimal discrimination time, and selects the phase and the ideally transmitted phase. The absolute value of the phase difference with the phase with the smallest phase difference is quantized and output. The reference frequency control circuit 8 is similar to the phase likelihood detection circuit 7 in that the phase of the received signal is ideally transmitted from the phase detection circuit 3 and the clock recovery circuit 4 at the optimal identification time. Two-stage discrimination is made between the "phase lead" state and the "phase delay" state. If the result of determination is that the state is deflected to either state, the output of the phase likelihood detection circuit 7 is referenced, and the oscillation frequency of the reference signal oscillation circuit 2 is changed to cancel it. .

As described above, according to the above embodiment, when the carrier frequency of the received signal and the oscillation frequency of the reference signal oscillation circuit 2 are different, the frequency difference becomes the phase difference with the ideal phase information at the time of identification. It is possible to inform the reference frequency control circuit 8 of the magnitude of the frequency difference by using the information of the phase likelihood detection circuit 7, and based on that, the frequency difference is quickly eliminated, and the frequency matches the carrier frequency of the received signal. There is an advantage that the frequency can be output quickly from the reference signal oscillation circuit 2.

EFFECTS OF THE INVENTION As is apparent from the above embodiment, the present invention is in a “phase lead” state with respect to the ideal phase information when the carrier frequency of the received signal and the oscillation frequency of the reference signal oscillation circuit are different. It controls the oscillation frequency of the reference signal oscillator circuit by weighting whether it is in the "phase delay" state with the information of the phase likelihood, and quickly matches the oscillation frequency of the reference signal oscillator circuit with the carrier frequency of the received signal. It has the advantage that it can be done.

[Brief description of drawings]

FIG. 1 is a block diagram of a data receiving apparatus according to an embodiment of the present invention, and FIG. 2 is a block diagram of a conventional data receiving apparatus. 1,21 ... Received signal input terminal, 2,22 ... Reference signal oscillator circuit, 3,23
... Phase detection circuit, 4, 24 ... Clock recovery circuit, 5, 25 ... Decoding circuit, 6, 26 ... Decoded data output terminal, 7 ... Phase likelihood detection circuit, 8, 27 ... Reference frequency control circuit

Claims (1)

[Claims] 1. A reference signal oscillator circuit having a variable frequency function for oscillating a frequency substantially equal to a carrier frequency of a received signal, and a phase difference between the output of the reference signal oscillator circuit and the received signal is detected to detect the received signal. A phase detection circuit that quantizes and outputs the phase information, a clock recovery circuit that obtains the optimum identification time from the output signal of the phase detection circuit, and the output of the phase detection circuit is determined based on the optimum identification time to decode the data. The decoding circuit that performs the above, the phase likelihood detection circuit that checks the phase difference between the phase information obtained at the identification time and the phase information that should originally be transmitted, and outputs the likelihood of the transmitted data, and the phase likelihood detection circuit that is obtained at the identification time The phase information is judged to be "leading" or "lagging" with respect to the phase information to be originally transmitted, and "leading" or "lagging" is output by the output of the phase likelihood detection circuit.
And a reference frequency control circuit that detects and outputs the frequency difference from the "leading" or "lagging" deflection,
By rapidly detecting the difference between the carrier frequency of the received signal and the frequency output from the reference signal oscillation circuit, and changing the oscillation frequency of the reference signal oscillation circuit to eliminate the difference,
A data receiving apparatus that decodes data by following the carrier frequency of a received signal.