JPS63280546A - Demodulation circuit for digital signal - Google Patents

Abstract

PURPOSE:To obtain a demodulation output with high reliability by utilizing selectively a demodulation signal for one-bit integration detection circuit and a demodulation signal of a 2-bit integration detection circuit selectively. CONSTITUTION:An 2-bit integration detection circuit 2 comprising an identification circuit 21 branching and connecting an input digital signal at a terminal 4 in addition to a 1-bit integration detection circuit 1, an integration discharge circuit whose integration time is nearly 2-bit of the input digital signal as a filter 22 with an output signal of the circuit 21 is transmitted therethrough, and a threshold value generating circuit 23 controlling the identification threshold value to be given to the identification circuit 21 is provided. Then a selection circuit 3 selects either output signal of the 1-bit integration detection circuit 1 or the 2-bit integration detection circuit 2. Thus, even if the detected output is deteriorated due to inter-code interference or the like, an excellent code error rate characteristic is obtained.

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] The present invention is used for signal demodulation of digital communication systems. It is particularly suitable for use in digital wireless communication systems.

The present invention enables a digital wireless communication system to obtain good bit error rate characteristics even when the detection output is degraded due to code amount interference or the like.

[Conventional technology]

Conventionally, a 1-bit integral detection circuit and a 2-bit integral detection circuit have been used as demodulation circuits for narrowband digital frequency modulation signals with code amount interference.
Bit integral detection circuits are known.

The 1-bit integral detection circuit uses an integral discharge circuit whose integration time is approximately equal to the time of 1 bit of the digital signal as a filter through which the signal passes after detection, and uses a 1-bit decision feedback method to select between two discrimination levels. , is a circuit that selects the optimal discrimination level and performs sign determination. On the other hand, the 2-bit integral detection circuit utilizes an integral discharge circuit whose integration time is approximately equal to the time of 2 bits in a similar circuit, and uses a 2-bit decision feedback method to determine the optimal discrimination level from among the four branch levels. This is a circuit that selects the
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[Problem that the invention seeks to solve]

The above-described 1-bit integral detection circuit has a short pull-in time at the start of reception and is stable in operation, but its static characteristic of bit error rate is inferior to that of the 2-bit integral detection circuit. On the other hand, 2
Bit integral detection circuits have better static characteristics of code error rate than 1-bit integral detection circuits, but the pull-in time at the start of reception is long and demodulation cannot be performed if the initial setting value of the discrimination level is inappropriate. Each has advantages and disadvantages, depending on the situation.

The present invention selectively utilizes the advantages of two integral detection circuits,
It is an object of the present invention to provide a demodulation circuit that reduces the code error rate in a steady state and improves the characteristics when the reception signal strength fluctuates due to fading in the reception signal and when the reception rises.

[Means for solving problems]

A first aspect of the present invention is to obtain a highly reliable demodulated output by selectively using a demodulated signal of a 1-bit integral detection circuit and a demodulated signal of a 2-bit integral detection circuit.

A second aspect of the present invention is characterized in that the output of the 1-bit integral detection circuit is used as a control signal for the threshold generation circuit in order to shorten the time it takes for the 2-bit integral detection circuit to stabilize at the time of rising. It is something to do.

[Effect]

In the first invention, by selectively using either the output of the 1-bit integral detection circuit or the output of the 2-bit integral detection circuit, a highly reliable demodulated signal can be obtained regardless of the conditions.

In the second invention, it is possible to shorten the time it takes for the 2-bit integral detection circuit to become stable, and to use the highly reliable demodulated signal of the 2-bit focus detection circuit in steady state.

〔Example〕

Next, embodiments will be described with reference to the drawings.

FIG. 1 is a block diagram of an apparatus according to a first embodiment of the present invention. This device includes an identification circuit 11 to which an input digital signal arriving at a terminal 4 is connected, and a filter 12 through which the output signal of this identification circuit 11 passes, an integral discharge circuit whose integration time is approximately equal to one bit of the input digital signal. and a threshold generation circuit 13 that controls the discrimination threshold given to the discrimination circuit 11 based on the output of the filter 12.
A bit integration detection circuit 1 is provided.

Apart from this 1-bit integral detection circuit 1, this device includes an identification circuit 21 which branches the input digital signal of the terminal 4 and connects it to its input, and a filter 22 through which the output signal of this identification circuit 21 passes. an integral discharge circuit whose integral time is approximately equal to 2 bits of the input digital signal;
A 2-bit integral detection circuit 2 is provided which includes a threshold generation circuit 23 that controls the identification threshold given to the identification circuit 21 based on the output of the filter 22.

Furthermore, this device includes a selection circuit 3 for selecting an output signal from either the 1-bit integral detection circuit 1 or the 2-bit integral detection circuit 2. The output of this selection circuit 3 is sent to an output signal terminal 6, and a reliability parameter for switching and controlling this selection circuit is input to a terminal 5.

In this circuit, an input cathode signal is demodulated in parallel by a 1-bit integral detection circuit 1 and a 2-bit integral detection circuit 2. One of these two demodulated outputs is selected by the selection circuit 3 and sent to the output signal terminal 6.

Next, the reliability parameters given to the terminal 5 will be explained.The first example is shown in FIG.
In addition to the signal applied to the terminal 4, the receiving signal strength is extracted from the terminal 1, and the comparing circuit 32 uses this received signal strength as a comparison standard Vr.
Compare with ef. This comparison circuit 32 sends reliability parameters to the terminal 5 so that the 1-bit integral detection circuit 1 is selected when the received signal strength is high, and the 2-bit integral detection circuit 2 is selected when the received signal strength is low.

In other words, in general, in a radio wave propagation path where fading occurs,
This is because when the received signal strength is high, the error rate of the output signal of the 1-bit integral detection circuit is low, and vice versa when the received signal strength is low.

A second example of reliability parameters given to the terminal 5 is shown in FIG. This can be used for signals in which an error correction code or an error identification code is employed in the transmitted digital signal. That is, terminals 7 and 8 shown in FIG.
The output signal of the 1-bit integral detection circuit 1 and the output signal of the 2-bit integral detection circuit 2 explained in FIG. 1 are respectively branched and input to the circuit. For each signal, the error detection circuits 33 and 34 detect the error rate, and the outputs are compared in the comparison circuit 35.The selection circuit 3 shown in FIG. 1 selects the side with the smaller error rate. The reliability parameter is sent to the terminal 5 so as to do so.

FIG. 4 is a block diagram of an apparatus according to a second embodiment of the present invention. This device is characterized by the configuration of the 2-bit integral detection circuit 2. That is, the control input of the threshold generation circuit 23 of the 2-bit integral detection circuit 2 is connected to the 1-bit integral detection circuit 1.
and the output of the 2-bit integral detection circuit 2 are inputted via the selective combination circuit 24. The other configurations are the same as those explained in FIG. 1 above.

To explain the configuration of this selective coupling circuit 24, the first example is to select the output of the 1-bit integral detection circuit 1 only at startup, and select the output of the 2-bit integral detection circuit 2 after the operation has stabilized. It is something.

A timer circuit is provided in the selective coupling circuit 24, and the output of the 1-bit integral detection circuit 1 is selected for a certain period of time after the start of reception and is used as a control input of the threshold generation circuit 23.

That is, since the 2-bit integral detection circuit 2 has a large number of discrimination levels, it takes time for the threshold value to reach a stable value. Depending on the input digital signal and initial value, it may not be possible to set a stable point at the rise.

Therefore, as mentioned above, by using the output of the 1-bit integral detection circuit 1 at startup to pull the threshold generation circuit 23 to a nearly stable value, the 2-bit integral detection circuit 2 is stabilized in a short time, and after stabilization, This drawback can be compensated for by utilizing the characteristics of the 2-bit integral detection circuit, which has a small bit error rate.

A second example of the selective combination circuit 24 combines the output of the 1-bit integral detection circuit 1 and the output of the 2-bit integral detection circuit 2 with predetermined weighting, and outputs the output as the control input of the threshold generation circuit 23. It is. The weighting value can be arbitrarily set between 1:0 and θ:1.

When the weight on the output side of the 1-bit integral detection circuit 1 is set to zero, the circuit is similar to that described in FIG. 1.

Furthermore, setting the weight on the output side of the 2-bit integral detection circuit 2 to zero results in the same state as that at the time of startup described above.

This also makes it possible to compensate for the drawback that the 2-bit integral detection circuit has poor pull-in at startup.

In the embodiment shown in FIG. 4, the selection circuit 3 can be constructed so that the output signal terminal 6 is constantly connected to the 2-bit integral detection circuit 2 without providing this. That is,
Since the error rate of the 2-bit integral detection circuit 2 is small once it reaches stable operation, if the threshold generation circuit 23 is stabilized using the output of the 1-bit integral detection circuit 1 at startup, the 2-bit It is also sufficiently practical to use the output of the integral detection circuit 2.

〔Effect of the invention〕

As explained above, the 1-bit integral detection circuit and the 2-bit integral detection circuit can be used in combination to compensate for their drawbacks.

That is, in the first invention, it is possible to use the more reliable output of the two integral detection circuits according to the conditions at that time.

In the second invention, it is possible to use a highly reliable demodulated signal by shortening the time required for the 2-bit integral detection circuit to stabilize at the time of its rise.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of an apparatus according to a first embodiment of the present invention. FIG. 2 is a block diagram of a second example for generating reliability parameters. FIG. 3 is a block diagram of a second example of generating reliability parameters. FIG. 4 is a block diagram of an apparatus according to a second embodiment of the present invention. 1... 1-bit integral detection circuit, 2... 2-bit integral detection circuit, 3... Selection circuit, 4... Input digital signal (detection signal) terminal, 5... Reliability parameter terminal , 6... Terminal of demodulated output signal, 7... Output terminal of 1-bit integral detection circuit, 8... Output terminal of 2-bit integral detection circuit, 11... Identification circuit, 12... Filter, 13... Threshold generation circuit, 21... Identification circuit, 22
...Filter, 23...Threshold value generation circuit, 24...
Selective coupling circuit.・2-, No Figure 1 Figure 2 Figure 3

Claims (2)

[Claims] (1) An identification circuit to which the input digital signal is connected; an integral discharge circuit which serves as a filter through which the output signal of this identification circuit passes; and an integral discharge circuit whose integral time is approximately equal to 1 bit of the input digital signal; In a digital signal demodulation circuit including a 1-bit integral detection circuit including a threshold generation circuit for controlling a discrimination threshold given to the circuit, a discriminating circuit to which the input digital signal is connected, in addition to the 1-bit integral detection circuit; As a filter through which the output signal of this identification circuit passes, there is provided an integral discharge circuit whose integration time is approximately equal to 2 bits of the input digital signal, and a threshold generation circuit that controls the identification threshold given to the identification circuit by the output of this filter. A 2-bit integral detection circuit including the above 1-bit integral detection circuit and the above 2-bit integral detection circuit is provided.
1. A digital signal demodulation circuit comprising a selection circuit for selecting one of the output signals of the bit integration detection circuit. (2) An identification circuit to which the input digital signal is connected, an integral discharge circuit as a filter through which the output signal of this identification circuit passes, and an integral discharge circuit whose integral time is approximately equal to 1 bit of the input digital signal; In a digital signal demodulation circuit including a 1-bit integral detection circuit including a threshold generation circuit for controlling a discrimination threshold given to the circuit, a discriminating circuit to which the input digital signal is connected, in addition to the 1-bit integral detection circuit; As a filter through which the output signal of this identification circuit passes, there is provided an integral discharge circuit whose integration time is approximately equal to 2 bits of the input digital signal, and a threshold generation circuit that controls the identification threshold given to the identification circuit by the output of this filter. 1. A digital signal demodulation circuit comprising: a 2-bit integral detection circuit; and a circuit for controlling a threshold generation circuit of the 2-bit integral detection circuit by a filter output of the 1-bit integral detection circuit.