JPH07115279A - Multilayer board and its manufacture - Google Patents

Multilayer board and its manufacture

Info

Publication number
JPH07115279A
JPH07115279A JP26217393A JP26217393A JPH07115279A JP H07115279 A JPH07115279 A JP H07115279A JP 26217393 A JP26217393 A JP 26217393A JP 26217393 A JP26217393 A JP 26217393A JP H07115279 A JPH07115279 A JP H07115279A
Authority
JP
Japan
Prior art keywords
resin
material layer
multilayer substrate
substrate according
insulating material
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP26217393A
Other languages
Japanese (ja)
Other versions
JP2591447B2 (en
Inventor
Tatsuo Ogawa
立夫 小川
Akihito Hatakeyama
秋仁 畠山
Koji Kawakita
晃司 川北
Hiroshi Sogo
寛 十河
Seiichi Nakatani
誠一 中谷
Tamaki Kojima
環生 小島
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP26217393A priority Critical patent/JP2591447B2/en
Publication of JPH07115279A publication Critical patent/JPH07115279A/en
Application granted granted Critical
Publication of JP2591447B2 publication Critical patent/JP2591447B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Abstract

PURPOSE:To provide a multilayer printed wiring board excellent in heatproof impact characteristics having an inner via hole and its manufacturing method. CONSTITUTION:In a board having a structure of electrically connecting with metal foils adhered to both surfaces of an insulated material layer 11 through a filling via hole comprising a conductive powder 12, hardened matter 13a of liquid resin, and reaction matter 13b of solidified resin, a glass transition point of the hardened matter of liquid resin and the reaction matter of the solidified resin constituting the filling via is lower than that of resin hardened matter of the insulated material layer. As for its manufacturing method, the insulated material layer and metal foils containing the filling via are further alternately repeatedly adhered onto one side or both sides of a both-side plate that metal foils of both surfaces are electrically connected through the filling via.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は、インナービアホールを
有する多層基板に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a multilayer board having an inner via hole.

【0002】[0002]

【従来の技術】電子機器の小型化、高機能化にともない
高配線密度、高信頼性を有する多層基板への要求が高ま
っている。従来のプリント多層基板では、スルーホール
による層間接続が一般的である。またさらに高密度な基
板として、インナービアホールで各層間の接続を行うも
のが提案されている。その一例として、まずガラスエポ
キシなどの絶縁基材の両面に銅箔を熱圧着で張り合わ
せ、エッチングなどの方法により回路パターンを形成し
た後、表裏を電気的に接続する箇所にドリル加工により
貫通孔を形成し、導体ペーストを充填、硬化することに
より2層回路基板を作製し、更にこの2層回路基板2枚
の間に、未硬化の絶縁基材にあらかじめ貫通孔を形成
し、導体ペーストを充填した中間接続体を挟んで熱圧着
することにより4層回路基板を得る方法がある。この方
法の繰り返しによって任意の層数の多層基板をインナー
ビアホール接続で作製することが出来る。
2. Description of the Related Art With the miniaturization and high functionality of electronic equipment, there is an increasing demand for a multilayer substrate having high wiring density and high reliability. In conventional printed multi-layer boards, interlayer connection by through holes is common. Further, as a higher density substrate, a substrate in which each layer is connected by an inner via hole is proposed. As an example, first, a copper foil is bonded to both sides of an insulating base material such as glass epoxy by thermocompression bonding, a circuit pattern is formed by a method such as etching, and then through holes are drilled at places where the front and back are electrically connected. A two-layer circuit board is manufactured by forming, filling and curing a conductor paste, and a through hole is previously formed in an uncured insulating base material between the two two-layer circuit boards to fill the conductor paste. There is a method for obtaining a four-layer circuit board by sandwiching the above-mentioned intermediate connector and thermocompression bonding. By repeating this method, it is possible to manufacture a multilayer substrate having an arbitrary number of layers by inner via hole connection.

【0003】[0003]

【発明が解決しようとする課題】しかしながら、一般に
プリント基板においては、絶縁基材の熱膨張係数は導体
金属に比べて大きいので、上記のスルーホールにより層
間を接続するタイプの基板では、スルーホール径に対す
る導体配線長、いわゆるアスペクト比が大きいため、熱
衝撃によって断線する場合がある。これは高多層になる
ほど、また基板厚みが増すほど顕著な問題となってい
る。また、上記の2つ目の例である層間接続タイプの多
層基板では、アスペクト比の観点からはスルーホールタ
イプの基板よりも有利と考えられるが、先行の特許では
充填された導電ペーストの硬化後の耐熱衝撃特性につい
て触れられていない。そこで本発明では、ビア部分の構
成に着目し、優れた耐熱衝撃特性をもつ層間接続ビアを
有するプリント多層基板を提供することを目的とする。
However, in a printed circuit board, the coefficient of thermal expansion of the insulating substrate is generally larger than that of the conductor metal. Since the conductor wiring length with respect to the so-called "aspect ratio" is large, the wire may be broken due to thermal shock. This becomes a serious problem as the number of layers increases and the thickness of the substrate increases. In addition, the interlayer connection type multilayer substrate which is the second example described above is considered to be more advantageous than the through hole type substrate from the viewpoint of the aspect ratio, but in the prior patent, after the filled conductive paste is cured, There is no mention of the thermal shock resistance property of. In view of the above, an object of the present invention is to provide a printed multilayer board having an interlayer connection via having excellent thermal shock resistance, paying attention to the structure of the via portion.

【0004】[0004]

【課題を解決するための手段】上記の課題を解決するた
めに、本発明では多層基板の構成として、導電性粉、液
状樹脂の硬化物、および固体樹脂の反応物より成る充填
ビアホールによって、絶縁材料層の両面に接着された金
属箔が電気的に接続されている両面板の、片側あるいは
両側にさらに充填ビアホールを含む絶縁材料層と金属箔
とを交互に繰り返し接着してなることを特徴とする。更
にビアを構成する液状樹脂の硬化物と固体樹脂の反応物
のガラス転移点が、絶縁材料層の樹脂硬化物のガラス転
移点より低いことが好ましく、特に液状樹脂として可と
う性エポキシ樹脂を含み、固体樹脂として粉体硬化剤を
用いることが好ましい。また導電性粉として銀・銅・ニ
ッケルのうちの少なくとも1種類以上から任意に選択す
ることができ、絶縁材料層をガラスエポキシコンポジッ
ト、ガラスBTレジンコンポジット、アラミドエポキシ
コンポジット、アラミドBTレジンコンポジットのうち
から選ぶことができる。また、ガラス及びアラミドは織
布、不織布の別なく本発明の基板に使用することが出来
る。
In order to solve the above-mentioned problems, in the present invention, a multilayer via board is insulated by a filled via hole made of conductive powder, a cured product of a liquid resin, and a reaction product of a solid resin. A double-sided plate in which metal foils adhered to both sides of the material layer are electrically connected, and an insulating material layer including a filling via hole is further repeatedly adhered to one side or both sides, and the metal foil is alternately and repeatedly adhered. To do. Furthermore, it is preferable that the glass transition point of the reaction product of the cured resin of the liquid resin and the solid resin constituting the via is lower than the glass transition point of the cured resin of the insulating material layer, and particularly the liquid resin contains a flexible epoxy resin. It is preferable to use a powder curing agent as the solid resin. The conductive powder can be arbitrarily selected from at least one of silver, copper, and nickel, and the insulating material layer is selected from glass epoxy composite, glass BT resin composite, aramid epoxy composite, and aramid BT resin composite. You can choose. Further, glass and aramid can be used for the substrate of the present invention regardless of whether they are woven cloth or non-woven cloth.

【0005】[0005]

【作用】上記のような構成とする事によって、ビア中に
硬化網目の中心として反応時に完全には溶融しないでも
との骨格をとどめる固体樹脂の反応物を点在させること
が出来、この部分の熱膨張係数は絶縁層材料に近いた
め、導電成分と絶縁層材料の間の熱膨張係数の違いから
生じる応力を低減することが可能となり、また液状樹脂
の硬化物及び固体樹脂の反応物のガラス転移点を、絶縁
材料層のガラス転移点より低くすることにより基板の熱
膨張収縮にビア部分が柔軟に対応することが出来るため
に耐熱衝撃特性に優れた多層基板を提供することが出来
る。
With the above-mentioned structure, the solid resin reactant that retains the original skeleton, which is not completely melted during the reaction, can be scattered in the via as the center of the cured network. Since the thermal expansion coefficient is close to that of the insulating layer material, it is possible to reduce the stress caused by the difference in the thermal expansion coefficient between the conductive component and the insulating layer material, and the glass of the cured product of the liquid resin and the reaction product of the solid resin. By setting the transition point to be lower than the glass transition point of the insulating material layer, the via portion can flexibly respond to the thermal expansion and contraction of the substrate, so that it is possible to provide a multilayer substrate excellent in thermal shock resistance.

【0006】[0006]

【実施例】以下本発明の実施例について説明する。最初
に本実施例における多層基板の作製方法について説明す
る。
EXAMPLES Examples of the present invention will be described below. First, a method for manufacturing a multilayer substrate in this example will be described.

【0007】絶縁基材にレーザー加工法などでビア穴加
工し、ビアに本願発明の導電ペーストを充填する。絶縁
基材については、ガラスエポキシコンポジット、ガラス
BTレジンコンポジット、アラミドエポキシコンポジッ
ト、アラミドBTレジンコンポジットのうちから選ぶこ
とが出来る。ペーストが充填された絶縁基材の両面を銅
箔で挟み、真空熱プレス中、180℃・50kg/cm
2・1時間の条件で加熱加圧した後、内層用回路パター
ンを形成して両面板を構成する。この両面板の両側を、
あらかじめ導電ペーストを充填したビアを有する絶縁材
料層で挟み、更に両外側に銅箔を配置して上記の条件で
熱圧着し外層用回路パターンを形成し4層構造の基板を
得る。これらの一連の工程を繰り返すことにより任意の
総数の多層基板を得ることが出来る。以下の実施例では
4層基板を作製して評価を行った。基板の作製方法は以
下の本発明の範囲外の構成を有する比較例においても共
通である。
Via holes are formed in the insulating base material by a laser processing method or the like, and the vias are filled with the conductive paste of the present invention. The insulating base material can be selected from glass epoxy composite, glass BT resin composite, aramid epoxy composite, and aramid BT resin composite. Both sides of the insulating base material filled with the paste are sandwiched between copper foils, and vacuum heat pressing is performed at 180 ° C and 50 kg / cm.
After heated and pressed under the conditions of 2-hour to form a double-sided plate to form an inner layer circuit pattern. Both sides of this double-sided board,
It is sandwiched between insulating material layers having vias filled with a conductive paste in advance, copper foils are further arranged on both outer sides, and thermocompression bonding is performed under the above conditions to form an outer layer circuit pattern to obtain a substrate having a four-layer structure. By repeating these series of steps, an arbitrary total number of multilayer substrates can be obtained. In the following examples, a four-layer substrate was prepared and evaluated. The method for manufacturing the substrate is common to the following comparative examples having configurations outside the scope of the present invention.

【0008】図1は、本発明の実施例による4層構造の
多層基板の断面図である。ビアは絶縁基材11に形成さ
れた貫通孔に充填されている。固化後のビアは導電性粉
12、液状樹脂の硬化物13a、および固体樹脂の反応
物13bよりなっており、内層回路14と外層回路1
5、あるいは内層回路間を電気的に接続している。本発
明に用いる導電ペーストとしては、銀、銅、ニッケルの
内から1種類以上選んだ導電性粉が50VOL%、エポキ
シ樹脂が40VOL%、粉体硬化剤が10VOL%の配合比で
混練した物を用いることができる。各導電性粉は球状粉
で、銀粉が中心粒径3.0ミクロン、BET値0.35
2/g、銅粉が中心粒径2.5ミクロン、BET値
0.40m2/g、ニッケル粉が5.0ミクロン、BE
T値0.30m2/gのものを用いた。エポキシ樹脂と
しては、最も一般的なビスフェノールA等(例;商品名
エピコート828、807、806:油化シェルエポキ
シ製)のビスーエピ系にたとえばグリシジルエステル系
等(例;商品名エピコート871:油化シェルエポキシ
製、アラルダイトCY184:チバガイギー製)の可と
う性エポキシを混合する事で適当な作業粘度のペースト
を得ることができる。可とう性エポキシを含むことによ
って、各種の導電性粉におけるペースト化可能な範囲を
広げることができる。また粉体硬化剤としては、アミン
系、イミダゾール系等(例;商品名アミキュアMY−2
4,MY−D,MY−H,PN−23、PN−D,PN
−H:味の素(株)製)が使用できる。
FIG. 1 is a sectional view of a multi-layer substrate having a four-layer structure according to an embodiment of the present invention. The via is filled in the through hole formed in the insulating base material 11. The vias after solidification are composed of the conductive powder 12, the cured product 13a of the liquid resin, and the reaction product 13b of the solid resin, and the inner layer circuit 14 and the outer layer circuit 1 are formed.
5, or the inner layer circuits are electrically connected. The conductive paste used in the present invention is a mixture of conductive powder selected from one or more of silver, copper, and nickel at 50 vol%, epoxy resin at 40 vol%, and powder curing agent at 10 vol%. Can be used. Each conductive powder is spherical powder, silver powder has a central particle diameter of 3.0 microns, BET value of 0.35
m 2 / g, copper powder has a central particle size of 2.5 μm, BET value 0.40 m 2 / g, nickel powder has 5.0 μm, BE
A T value of 0.30 m 2 / g was used. As the epoxy resin, the most common bisphenol A such as bisphenol A (eg; trade name Epicoat 828, 807, 806: made by oiled shell epoxy) and glycidyl ester type (eg; trade name Epicoat 871: oiled shell epoxy) are used. By mixing a flexible epoxy (made by epoxy, Araldite CY184: made by Ciba Geigy), a paste having an appropriate working viscosity can be obtained. By including the flexible epoxy, it is possible to expand the range in which various conductive powders can be pasted. Further, as the powder curing agent, amine-based, imidazole-based, etc. (eg, trade name Amicure MY-2
4, MY-D, MY-H, PN-23, PN-D, PN
-H: Ajinomoto Co., Inc. can be used.

【0009】これに対して本発明の範囲外の比較例の基
板用のペーストとして、市販のビスフェノールA55重
量部と酸無水物系液状硬化剤(例;商品名リカシッドM
H:新日本理化製)44.5重量部及びアミン系促進剤
(例;ライザー:花王製)0.5重量部からなる1液性
エポキシ樹脂に、銅及び銀を50VOL%になるように加
えて混連したペーストを作製した。このペーストを充填
したビアによる4層基板について断面を図2に示す。
On the other hand, as a paste for a substrate of a comparative example outside the scope of the present invention, 55 parts by weight of a commercially available bisphenol A and an acid anhydride type liquid curing agent (eg; trade name Rikacid M) are used.
H: New Nippon Rika) 44.5 parts by weight and an amine accelerator (eg; riser: Kao) 0.5 parts by weight to a one-part epoxy resin containing 50 vol% of copper and silver. To prepare a mixed paste. FIG. 2 shows a cross section of a four-layer substrate with vias filled with this paste.

【0010】絶縁基材21については本発明による基板
と同様に、ガラスエポキシコンポジット、ガラスBTレ
ジンコンポジット、アラミドエポキシコンポジット、ア
ラミドBTレジンコンポジットのうちから選ぶことがで
きる。本発明による基板と比較例の基板では、ビア部分
の構成のみが異なっている。即ち導電性粉22および液
状樹脂の硬化物23による網目のみからなっており、内
層回路24と外層回路25、あるいは内層回路間を電気
的に接続している。
The insulating base material 21 can be selected from glass epoxy composite, glass BT resin composite, aramid epoxy composite, and aramid BT resin composite, like the substrate according to the present invention. The substrate according to the present invention and the substrate of the comparative example differ only in the configuration of the via portion. That is, it is composed only of the mesh of the conductive powder 22 and the cured product 23 of the liquid resin, and electrically connects the inner layer circuit 24 and the outer layer circuit 25 or the inner layer circuit.

【0011】(表1)に以下の実施例で用いたペースト
の配合組成について示す。以下の実施例では(表1)中
のペースト番号を用いて説明する。
Table 1 shows the composition of the pastes used in the following examples. The following examples will be described using the paste numbers in (Table 1).

【0012】[0012]

【表1】 [Table 1]

【0013】以下に各種絶縁基材を用いた基板について
具体的な実施例を挙げて説明する。 (実施例1)絶縁基材として140℃、150℃、16
0℃にガラス転移点をもつ3種類の熱硬化エポキシ樹脂
とガラス織布によるガラスエポキシコンポジットにたい
して表1に示した各ペーストを充填し、上述の工程にそ
って4層基板を作製した。
Substrates using various insulating base materials will be described below with reference to specific examples. (Example 1) 140 ° C., 150 ° C., 16 as an insulating base material
Each paste shown in Table 1 was filled into a glass epoxy composite made of three kinds of thermosetting epoxy resins having a glass transition point at 0 ° C. and a glass woven cloth, and a four-layer substrate was manufactured according to the above steps.

【0014】これらの各回路に含まれるビアのうち30
00穴について、−55℃、125℃各30分保持50
0サイクルの熱衝撃試験Aを実施してビア部分の抵抗が
試験前と比べて2倍以上になったものを不良としてその
数を各基板で比較した。結果を(表2)に示す。
30 of the vias included in each of these circuits
For hole 00, hold at -55 ° C and 125 ° C for 30 minutes each 50
The thermal shock test A of 0 cycle was carried out, and the number in which the resistance of the via portion became twice or more as compared with that before the test was regarded as a defect was compared with each other. The results are shown in (Table 2).

【0015】[0015]

【表2】 [Table 2]

【0016】またビア部分と基材のガラス転移点の組み
合わせについて基板No.4〜15を選んで25℃、26
0℃各30秒保持100サイクルの熱衝撃試験Bを実施
して熱衝撃試験Aと同様にビア部分の抵抗が試験前と比
べて2倍以上になったものを不良としてその数を各基板
で比較した。結果を(表3)に示す。なお、各絶縁基材
の硬化後のガラス転移点及び各ビア部分の樹脂硬化物の
ガラス転移点についても同時に(表3)中に示した。
Regarding the combination of the glass transition point of the via portion and the base material, substrate Nos. 4 to 15 were selected and the temperature was 26 ° C. at 26 ° C.
The thermal shock test B of 100 cycles held at 0 ° C. for 30 seconds each was carried out, and as in the case of the thermal shock test A, those in which the resistance of the via portion was twice or more compared to that before the test were regarded as defective and the number of them was judged on each substrate. Compared. The results are shown in (Table 3). The glass transition point after curing of each insulating base material and the glass transition point of the resin cured product of each via portion are also shown in Table 3 at the same time.

【0017】[0017]

【表3】 [Table 3]

【0018】(実施例2)絶縁基材として142℃、1
50℃、163℃にガラス転移点をもつ3種類の熱硬化
エポキシ樹脂とアラミド不織布によるアラミドエポキシ
コンポジットにたいして表1に示した各ペーストを充填
し、上述の工程にそって4層基板を作製した。
Example 2 As an insulating base material, 142 ° C., 1
An aramid epoxy composite made of three kinds of thermosetting epoxy resins and aramid nonwoven fabric having glass transition points at 50 ° C. and 163 ° C. was filled with each paste shown in Table 1, and a four-layer substrate was manufactured according to the above steps.

【0019】これらの各回路に含まれるビアのうち30
00穴について、−55℃、125℃各30分保持50
0サイクルの熱衝撃試験Aを実施してビア部分の抵抗が
試験前と比べて2倍以上になったものを不良としてその
数を各基板で比較した。結果を(表4)に示す。
30 of the vias included in each of these circuits
For hole 00, hold at -55 ° C and 125 ° C for 30 minutes each 50
The thermal shock test A of 0 cycle was carried out, and the number in which the resistance of the via portion became twice or more as compared with that before the test was regarded as a defect was compared with each other. The results are shown in (Table 4).

【0020】[0020]

【表4】 [Table 4]

【0021】またビア部分と基材のガラス転移点の組み
合わせについて基板No.28〜39を選んで25℃、2
60℃各30秒保持100サイクルの熱衝撃試験Bを実
施して熱衝撃試験Aと同様にビア部分の抵抗が試験前と
比べて2倍以上になったものを不良としてその数を各基
板で比較した。結果を表5に示す。なお、各絶縁基材の
硬化後のガラス転移点及び各ビア部分の樹脂硬化物のガ
ラス転移点についても同時に(表5)中に示した。
Regarding the combination of the glass transition point of the via portion and the base material, substrate Nos. 28 to 39 were selected and the temperature was 2 ° C.
Thermal shock test B of 100 cycles held at 60 ° C. for 30 seconds each was carried out, and as in the case of thermal shock test A, the one in which the resistance of the via portion was more than double the resistance before the test was regarded as a defect and the number was determined for each substrate. Compared. The results are shown in Table 5. The glass transition point after curing of each insulating base material and the glass transition point of the resin cured product of each via portion are also shown in (Table 5) at the same time.

【0022】[0022]

【表5】 [Table 5]

【0023】(実施例3)絶縁基材として145℃、1
55℃、165℃にガラス転移点をもつ3種類のビスマ
レイミド・トリアジンとガラス不織布よりなるガラスB
Tレジンコンポジットにたいして表1に示した各ペース
トを充填し、上述の工程にそって4層基板を作製した。
Example 3 As an insulating base material, 145 ° C., 1
Glass B composed of 3 types of bismaleimide triazines having glass transition points at 55 ° C and 165 ° C and glass nonwoven fabric
The T-resin composite was filled with each paste shown in Table 1, and a four-layer substrate was manufactured according to the above steps.

【0024】これらの各回路に含まれるビアのうち30
00穴について、−55℃、125℃各30分保持50
0サイクルの熱衝撃試験Aを実施してビア部分の抵抗が
試験前と比べて2倍以上になったものを不良としてその
数を各基板で比較した。結果を(表6)に示す。
30 of the vias included in each of these circuits
For hole 00, hold at -55 ° C and 125 ° C for 30 minutes each 50
The thermal shock test A of 0 cycle was carried out, and the number in which the resistance of the via portion became twice or more as compared with that before the test was regarded as a defect was compared with each other. The results are shown in (Table 6).

【0025】[0025]

【表6】 [Table 6]

【0026】またビア部分と基材のガラス転移点の組み
合わせについて基板No.52〜63を選んで25℃、2
60℃各30秒保持100サイクルの熱衝撃試験Bを実
施して熱衝撃試験Aと同様にビア部分の抵抗が試験前と
比べて2倍以上になったものを不良としてその数を各基
板で比較した。結果を(表7)に示す。なお、各絶縁基
材の硬化後のガラス転移点及び各ビア部分の樹脂硬化物
のガラス転移点についても同時に(表7)中に示した。
Regarding the combination of the glass transition point of the via portion and the base material, the substrate Nos. 52 to 63 were selected and the temperature was 2 ° C. and the temperature was 2 ° C.
Thermal shock test B of 100 cycles held at 60 ° C. for 30 seconds each was carried out, and as in the case of thermal shock test A, the one in which the resistance of the via portion was more than double the resistance before the test was regarded as a defect and the number was determined for each substrate. Compared. The results are shown in (Table 7). The glass transition point after curing of each insulating base material and the glass transition point of the cured resin of each via portion are also shown in Table 7 at the same time.

【0027】[0027]

【表7】 [Table 7]

【0028】(実施例4)絶縁基材として143℃、1
52℃、167℃にガラス転移点をもつ3種類のビスマ
レミド・トリアジンとアラミド織布によるアラミドBT
レジンコンポジットにたいして(表1)に示した各ペー
ストを充填し、上述の工程にそって4層基板を作製し
た。
Example 4 As an insulating base material, 143 ° C., 1
Aramid BT made of aramid woven fabric and 3 types of bismalemid triazines having glass transition points at 52 ° C and 167 ° C
The resin composite was filled with each paste shown in (Table 1), and a four-layer substrate was manufactured according to the above steps.

【0029】これらの各回路に含まれるビアのうち30
00穴について、−55℃、125℃各30分保持50
0サイクルの熱衝撃試験Aを実施してビア部分の抵抗が
試験前と比べて2倍以上になったものを不良としてその
数を各基板で比較した。結果を(表8)に示す。
30 of the vias included in each of these circuits
For hole 00, hold at -55 ° C and 125 ° C for 30 minutes each 50
The thermal shock test A of 0 cycle was carried out, and the number in which the resistance of the via portion became twice or more as compared with that before the test was regarded as a defect was compared with each other. The results are shown in (Table 8).

【0030】[0030]

【表8】 [Table 8]

【0031】またビア部分と基材のガラス転移点の組み
合わせについて基板No.76〜87を選んで25℃、2
60℃各30秒保持100サイクルの熱衝撃試験Bを実
施して熱衝撃試験Aと同様にビア部分の抵抗が試験前と
比べて2倍以上になったものを不良としてその数を各基
板で比較した。結果を(表9)に示す。なお、各絶縁基
材の硬化後のガラス転移点及び各ビア部分の樹脂硬化物
のガラス転移点についても同時に(表9)中に示した。
Regarding the combination of the glass transition point of the via portion and the base material, substrate Nos. 76 to 87 were selected and the temperature was 2 ° C. and 2
Thermal shock test B of 100 cycles held at 60 ° C. for 30 seconds each was carried out, and as in the case of thermal shock test A, the one in which the resistance of the via portion was more than double the resistance before the test was regarded as a defect and the number was determined for each substrate. Compared. The results are shown in (Table 9). The glass transition point after curing of each insulating base material and the glass transition point of the cured resin of each via portion are also shown in Table 9 at the same time.

【0032】[0032]

【表9】 [Table 9]

【0033】以上の(実施例1)から(実施例4)の
(表2)、(表4)、(表6)、(表8)に示した結果
から明らかなように固体樹脂の反応物をビア中に含む物
は、熱衝撃試験Aの温度条件においての耐熱衝撃特性に
優れることが解る。また(表3)、(表5)、(表
7)、(表9)の結果からビア部分の樹脂硬化物のガラ
ス転移点が基材のガラス転移点以下である組み合わせを
選択することにより熱衝撃試験Bの様な途中にガラス転
移点の領域を含むような温度条件においても優れた耐熱
衝撃特性が得られることが解る。
As is clear from the results shown in (Table 2), (Table 4), (Table 6) and (Table 8) of (Example 1) to (Example 4) above, the reaction product of the solid resin is shown. It can be seen that the material containing the in the via has excellent thermal shock resistance characteristics under the temperature conditions of the thermal shock test A. Further, from the results of (Table 3), (Table 5), (Table 7), and (Table 9), heat can be obtained by selecting a combination in which the glass transition point of the resin cured product of the via portion is equal to or lower than the glass transition point of the base material. It can be seen that excellent thermal shock resistance characteristics can be obtained even under a temperature condition in which the glass transition point region is included in the middle of the shock test B.

【0034】[0034]

【発明の効果】以上のように本発明によれば、固体樹脂
の反応物をビア中に含むことによりビア部分の熱膨張係
数を絶縁材料層に近づけることが可能となり、またビア
内の樹脂硬化物のガラス転移温度を絶縁層材料よりも低
くすることで耐熱衝撃特性に優れたインナービアホール
を持つ多層基板を提供することが出来る。
As described above, according to the present invention, it is possible to bring the thermal expansion coefficient of the via portion close to that of the insulating material layer by including the reaction product of the solid resin in the via, and to cure the resin in the via. By making the glass transition temperature of the material lower than that of the insulating layer material, it is possible to provide a multilayer substrate having an inner via hole excellent in thermal shock resistance.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明の実施例における多層基板の構成を示す
断面図
FIG. 1 is a cross-sectional view showing a structure of a multilayer substrate according to an embodiment of the present invention.

【図2】従来例の多層基板の構成を示す断面図FIG. 2 is a cross-sectional view showing the structure of a conventional multilayer substrate.

【符号の説明】[Explanation of symbols]

11 絶縁基材 12 導電性粉 13a 液状樹脂の硬化物 13b 固体樹脂の反応物 14 内層用回路 15 外層用回路 11 Insulating Substrate 12 Conductive Powder 13a Liquid Resin Cured Product 13b Solid Resin Reaction Product 14 Inner Layer Circuit 15 Outer Layer Circuit

───────────────────────────────────────────────────── フロントページの続き (72)発明者 十河 寛 大阪府門真市大字門真1006番地 松下電器 産業株式会社内 (72)発明者 中谷 誠一 大阪府門真市大字門真1006番地 松下電器 産業株式会社内 (72)発明者 小島 環生 大阪府門真市大字門真1006番地 松下電器 産業株式会社内 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Hiroshi Togawa 1006 Kadoma, Kadoma City, Osaka Prefecture Matsushita Electric Industrial Co., Ltd. (72) Seiichi Nakatani, 1006 Kadoma, Kadoma City, Osaka Matsushita Electric Industrial Co., Ltd. (72) Inventor Tamao Kojima 1006 Kadoma, Kadoma City, Osaka Prefecture Matsushita Electric Industrial Co., Ltd.

Claims (11)

【特許請求の範囲】[Claims] 【請求項1】導電性粉、液状樹脂の硬化物、および固体
樹脂の反応物より成る充填ビアホールによって、絶縁材
料層の両面に接着された金属箔が電気的に接続されてい
る両面板の、片側あるいは両側にさらに前記充填ビアホ
ールを含む絶縁材料層と金属箔とを交互に繰り返し接着
してなり、ビアを構成する液状樹脂の硬化物と固体樹脂
の反応物のガラス転移点が、絶縁材料層の樹脂硬化物の
ガラス転移点より低いことを特徴とする多層基板。
1. A double-sided plate in which metal foils bonded to both sides of an insulating material layer are electrically connected by filled via holes made of conductive powder, a cured product of a liquid resin, and a reaction product of a solid resin, The insulating material layer containing the filled via hole and the metal foil are alternately and repeatedly bonded to one side or both sides, and the glass transition point of the cured product of the liquid resin and the reaction product of the solid resin forming the via is the insulating material layer. A multilayer substrate characterized by having a glass transition point lower than that of the resin cured product.
【請求項2】液状樹脂が、可とう性エポキシ樹脂を含む
ことを特徴とする請求項1記載の多層基板。
2. The multilayer substrate according to claim 1, wherein the liquid resin contains a flexible epoxy resin.
【請求項3】固体樹脂が、粉体硬化剤である請求項1記
載の多層基板。
3. The multilayer substrate according to claim 1, wherein the solid resin is a powder curing agent.
【請求項4】導電性粉が銀・銅・ニッケルのうちの少な
くとも1種類以上から選ばれる請求項1記載の多層基
板。
4. The multilayer substrate according to claim 1, wherein the conductive powder is selected from at least one selected from silver, copper and nickel.
【請求項5】絶縁材料層がガラスエポキシコンポジッ
ト、ガラスBTレジンコンポジット、アラミドエポキシ
コンポジット、アラミドBTレジンコンポジットのうち
の少なくとも1種類以上から選ばれることを特徴とする
請求項1記載の多層基板。
5. The multilayer substrate according to claim 1, wherein the insulating material layer is selected from at least one selected from a glass epoxy composite, a glass BT resin composite, an aramid epoxy composite, and an aramid BT resin composite.
【請求項6】絶縁材料層にビア穴加工する工程、ビアに
導電性粉、液状樹脂及び固体樹脂よりなる導電ペースト
を充填する工程、導電ペーストが充填された絶縁基材の
両面を銅箔で挟み、熱圧着する工程、内層用回路パター
ンを形成し両面板構成とする工程、さらにこの両面板の
両側あるいは片側に前記の充填ビアホールを有する絶縁
材料層と銅箔を交互に熱圧着しかつ銅箔をパターニング
して回路形成して多層構成とする工程の一連の工程より
なる多層基板の製造方法。
6. A step of forming a via hole in an insulating material layer, a step of filling a via with a conductive paste made of conductive powder, a liquid resin and a solid resin, and copper foil on both sides of an insulating base material filled with the conductive paste. Step of sandwiching and thermocompression bonding, forming an inner layer circuit pattern to form a double-sided board, and further thermocompressing an insulating material layer and a copper foil having the above-mentioned filled via holes on both sides or one side of the double-sided board alternately and copper. A method of manufacturing a multi-layer substrate, which comprises a series of steps of patterning a foil to form a circuit to form a multi-layer structure.
【請求項7】液状樹脂が、可とう性エポキシ樹脂を含む
ことを特徴とする請求項6記載の多層基板の製造方法。
7. The method of manufacturing a multilayer substrate according to claim 6, wherein the liquid resin contains a flexible epoxy resin.
【請求項8】固体樹脂が、粉体硬化剤である請求項6記
載の多層基板の製造方法。
8. The method for manufacturing a multilayer substrate according to claim 6, wherein the solid resin is a powder curing agent.
【請求項9】熱圧着後のビアを構成する液状樹脂の硬化
物と固体樹脂の反応物のガラス転移点が、絶縁材料層の
樹脂硬化物のガラス転移点より低いことを特徴とする請
求項6記載の多層基板の製造方法。
9. The glass transition point of a reaction product of a cured product of a liquid resin and a solid resin constituting a via after thermocompression bonding is lower than a glass transition point of a cured resin product of an insulating material layer. 7. The method for manufacturing a multilayer substrate according to item 6.
【請求項10】導電性粉が銀・銅・ニッケルのうちの少
なくとも1種類以上から選ばれる請求項6記載の多層基
板の製造方法。
10. The method for producing a multilayer substrate according to claim 6, wherein the conductive powder is selected from at least one of silver, copper and nickel.
【請求項11】絶縁材料層がガラスエポキシコンポジッ
ト、ガラスBTレジンコンポジット、アラミドエポキシ
コンポジット、アラミドBTレジンコンポジットのうち
の少なくとも1種類以上から選ばれることを特徴とする
請求項6記載の多層基板の製造方法。
11. The method for producing a multilayer substrate according to claim 6, wherein the insulating material layer is selected from at least one selected from a glass epoxy composite, a glass BT resin composite, an aramid epoxy composite, and an aramid BT resin composite. Method.
JP26217393A 1993-10-20 1993-10-20 Multilayer substrate and manufacturing method thereof Expired - Lifetime JP2591447B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP26217393A JP2591447B2 (en) 1993-10-20 1993-10-20 Multilayer substrate and manufacturing method thereof

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP26217393A JP2591447B2 (en) 1993-10-20 1993-10-20 Multilayer substrate and manufacturing method thereof

Publications (2)

Publication Number Publication Date
JPH07115279A true JPH07115279A (en) 1995-05-02
JP2591447B2 JP2591447B2 (en) 1997-03-19

Family

ID=17372085

Family Applications (1)

Application Number Title Priority Date Filing Date
JP26217393A Expired - Lifetime JP2591447B2 (en) 1993-10-20 1993-10-20 Multilayer substrate and manufacturing method thereof

Country Status (1)

Country Link
JP (1) JP2591447B2 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6753483B2 (en) 2000-06-14 2004-06-22 Matsushita Electric Industrial Co., Ltd. Printed circuit board and method of manufacturing the same

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6753483B2 (en) 2000-06-14 2004-06-22 Matsushita Electric Industrial Co., Ltd. Printed circuit board and method of manufacturing the same
US7155820B2 (en) 2000-06-14 2007-01-02 Matsushita Electric Industrial Co., Ltd. Method for manufacturing printed circuit board

Also Published As

Publication number Publication date
JP2591447B2 (en) 1997-03-19

Similar Documents

Publication Publication Date Title
JP3375555B2 (en) Circuit component built-in module and method of manufacturing the same
JP3197213B2 (en) Printed wiring board and method of manufacturing the same
JP4279893B2 (en) Manufacturing method of circuit component built-in module
US5960538A (en) Printed circuit board
TWI242398B (en) Printed circuit board and method of manufacturing the same
JP2587596B2 (en) Circuit board connecting material and method for manufacturing multilayer circuit board using the same
JPH10256687A (en) Conductor paste composition for filling it into via hole, and printed circuit board using the same
JP5217640B2 (en) Method for manufacturing printed wiring board and method for manufacturing printed circuit board unit
JPH07176846A (en) Composition of conductor paste for filling via hole, both-sided and multilayered printed board using it, and its manufacture
US20090294160A1 (en) Method of making printed wiring board and electrically-conductive binder
CN102281712A (en) Laminated circuit board, bonding sheet, laminated-circuit-board producing method, and bonding-sheet producing method
JP4606685B2 (en) Module with built-in circuit components
JPH07263828A (en) Printed interconnection board and its production process
US6930395B2 (en) Circuit substrate having improved connection reliability and a method for manufacturing the same
JP2002368043A (en) Conductive paste, conductive bump using it, its forming method, method for connecting conductive bump, circuit board and its producing method
US20030137815A1 (en) Printed wiring board and method of manufacturing the same
JP5077800B2 (en) Manufacturing method of multilayer printed wiring board
KR101281898B1 (en) Multilayer printed wiring board and method for producing same
JP3440174B2 (en) Multilayer printed wiring board and method of manufacturing the same
JP2004273575A (en) Multilayer printed wiring board and its manufacturing method
JP2002368364A (en) Printed wiring board and its manufacturing method
JPH07115279A (en) Multilayer board and its manufacture
KR100733759B1 (en) Electronic conductive paste coated with heterogeneous material and multi-level pcb manufacturing method
JP3678015B2 (en) Conductive material for connection between wirings through insulating layer and method for manufacturing wiring board
JPH03101195A (en) Method of connecting multilayer printed interconnection board

Legal Events

Date Code Title Description
FPAY Renewal fee payment (prs date is renewal date of database)

Free format text: PAYMENT UNTIL: 20071219

Year of fee payment: 11

FPAY Renewal fee payment (prs date is renewal date of database)

Free format text: PAYMENT UNTIL: 20081219

Year of fee payment: 12

FPAY Renewal fee payment (prs date is renewal date of database)

Free format text: PAYMENT UNTIL: 20091219

Year of fee payment: 13

FPAY Renewal fee payment (prs date is renewal date of database)

Free format text: PAYMENT UNTIL: 20091219

Year of fee payment: 13

FPAY Renewal fee payment (prs date is renewal date of database)

Free format text: PAYMENT UNTIL: 20101219

Year of fee payment: 14

FPAY Renewal fee payment (prs date is renewal date of database)

Free format text: PAYMENT UNTIL: 20101219

Year of fee payment: 14

FPAY Renewal fee payment (prs date is renewal date of database)

Free format text: PAYMENT UNTIL: 20111219

Year of fee payment: 15

FPAY Renewal fee payment (prs date is renewal date of database)

Free format text: PAYMENT UNTIL: 20111219

Year of fee payment: 15

FPAY Renewal fee payment (prs date is renewal date of database)

Free format text: PAYMENT UNTIL: 20121219

Year of fee payment: 16

FPAY Renewal fee payment (prs date is renewal date of database)

Free format text: PAYMENT UNTIL: 20121219

Year of fee payment: 16

FPAY Renewal fee payment (prs date is renewal date of database)

Free format text: PAYMENT UNTIL: 20131219

Year of fee payment: 17

EXPY Cancellation because of completion of term