JPH07115032A - Manufacture of thin film capacitor and semiconductor integrated circuit including the thin film capacitor - Google Patents

Abstract

PURPOSE:To reduce a manufacturing cost of an IC by reducing the number of layers by forming a resistor film of a microwave IC used in a communication field, etc., and a lower electrode wiring and an upper electrode wiring of an MIM capacitor of the same layer. CONSTITUTION:In a manufacturing method of a semiconductor integrated circuit including a resistor R, an inductor L, and an MIM capacitor C as constituents of a microwave IC, a resistor film 12 and a lower electrode wiring 14 are formed by the same manufacturing process when a resistor film, a lower electrode wiring 14A, an insulation layer 16, an electrode wiring 18, a bridge wiring 20, etc., are formed on a substrate 10 of each constituent in layers.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a thin film capacitor and a semiconductor integrated circuit including the thin film capacitor, and more particularly to a monolithic microwave integrated circuit (Monolith) used in the field of communication.
ic Microwave Integrated C
ircuit: MMIC) and microwave IC (MIC)
And a method for manufacturing a semiconductor integrated circuit including the thin film capacitor, which is a component of an IC for microwaves.

[0002]

2. Description of the Related Art Generally, MIM (Metal-Insulate-Met) which is a thin film capacitor in MMIC.
al) The capacitor includes, for example, as shown in the sectional view of FIG. 9, a substrate 10, a lower electrode wiring 14 formed on the upper surface of the substrate 10, an insulating film 16 formed on the upper surface of the lower electrode wiring 14, The upper electrode wiring 18 is formed on the upper surface of the insulating film 16 and the air bridge 20 (air wiring) is formed on the upper surface of the upper electrode wiring 18 by plating or the like.

In FIG. 9, a substrate 1 of the MIM capacitor
The lower electrode wiring 14 formed on the upper surface of 0 is formed of Ti / Au which is a conductor having a low resistance.

Conventionally, a resistor R, which is a constituent element of the MMIC,
The inductance L and the MIM capacitor having the above structure are shown in FIGS. 10 to 12 (layers 1 to 6).
It is manufactured according to the process sequence shown in. Hereinafter, each manufacturing process of the resistor R, the MIM capacitor C, and the inductance L will be described with reference to the same layer in mask or film formation, as shown in FIGS. 10 to 12, the resistance R, MIM
The same parts constituting the capacitor C and the inductance L will be described with the same reference numerals.

First, layer 1 (FIG. 10 (10-1))
Then, the resistive film 12 having a predetermined pattern is formed on the upper surface of the substrate 10 of the resistor R.

In the next layer 2 (FIG. 10 (10-2)), the lower electrode wiring 14 having a predetermined pattern is designed on the upper surface of the resistance film 12 of the resistor R and the upper surface of the substrate 10 of the MIM capacitor C. It is formed.

Layer 3 (FIG. 11 (11-1))
Then, the lower electrode wiring 1 of the resistor R and the MIM capacitor C
4 and the upper surface of the substrate 10 having the inductance L,
The insulating film 16 is formed over a predetermined range.

Furthermore, layer 4 (see FIG. 11 (11-
In 2)), the upper electrode wiring 18 having a predetermined pattern is formed on each of the upper surfaces of the insulating film 16 of the resistor R, the MIM capacitor C, and the inductance L, and the resistor R ends the manufacturing process.

In the next layer 5 (FIG. 12 (12-1)), a resist layer a22 is formed over a predetermined range on the upper surfaces of the upper electrode wirings 18 of the MIM capacitor C and the inductance L, and on the upper surfaces thereof. The power feeding layer 26 is formed.

Then, the layer 6 (see FIG. 12 (12-
In 2)), the resist layer b24 and the air bridge 20 by Au plating or the like are formed on the upper surfaces of the MIM capacitor C and the inductance L, and the manufacturing process of the MIM capacitor C and the inductance L is completed.

As can be understood from the above description, the MMI
When manufacturing an IC such as C, the number of manufacturing steps depends on the number of IC layers.

[0012]

However, the resistance R and the inductance L which are the constituent elements of the above-mentioned MMIC.
In the manufacturing process of the MIM capacitor and the manufacturing process of the MIM capacitor, the steps of forming the resistance film 12 and the lower electrode wiring 14 are performed separately, so that the number of layers becomes “6”. And the manufacturing cost of the IC is increased.

The present invention has been made in view of the above problems of the prior art. The object of the present invention is to form the resistance film and the lower electrode wiring in the same layer, or to form the resistance film. A thin film capacitor and a semiconductor integrated circuit including the thin film capacitor in which the number of layers is reduced by forming the upper electrode wiring and the upper electrode wiring in the same layer to reduce the manufacturing cost of the IC and the manufacturing period. It is intended to provide a method.

[0014]

In order to achieve the above object, a method of manufacturing a semiconductor integrated circuit according to the present invention is a method of manufacturing a semiconductor integrated circuit including resistors, inductances, and thin film capacitors as constituent elements. When the resistive film, the lower electrode wiring, the insulating layer, the upper electrode wiring and the aerial wiring are formed in layers on the substrate of the element, the resistive film and the lower electrode wiring are formed in the same manufacturing process, The film and the upper electrode wiring are formed in the same manufacturing process.

In the thin film capacitor according to the present invention, TaN is used for the lower electrode wiring or the upper electrode wiring formed on the substrate.

Furthermore, in the method of manufacturing a semiconductor integrated circuit according to the present invention, the lower electrode wiring is formed on the substrate, the insulating film and the resistance film are continuously formed on the upper surface thereof, and the upper electrode wiring is formed on the upper surface thereof. It is manufactured by a three-layer structure to be formed.

[0017]

The conductor TaN which is the same as the resistance film is used for the lower electrode wiring or the upper electrode wiring. Therefore, for example, the TaN resistance film and the lower electrode wiring having a predetermined pattern can be formed in the same layer on the upper surface of the substrate of the resistor and the capacitor, respectively.

Therefore, in the semiconductor manufacturing method according to the present invention, the number of layers can be reduced as compared with the conventional manufacturing process.

In the case of a thin film capacitor, Ta is used for the lower electrode wiring or the upper electrode wiring formed on the substrate.
By using N, the number of layers can be reduced as compared with the conventional manufacturing process.

Furthermore, by matching the manufacturing process of the resistance and the inductance according to the manufacturing process of the capacitor, all the constituent elements can be manufactured with only three layers.

[0021]

Embodiments of the method of manufacturing a thin film capacitor and a semiconductor integrated circuit including the thin film capacitor according to the present invention will be described below in detail with reference to the drawings.

FIG. 1 is a cross-sectional view of an essential part showing the structure of a MIM capacitor which is a first embodiment manufactured according to the present invention.

In FIG. 1, the same parts constituting the resistor R, the MIM capacitor C, and the inductance L corresponding to the structures shown in FIGS. 9 to 12 are designated by the same reference numerals.

M, which is a constituent element of the MMIC according to the present invention
The IM capacitor includes the substrate 10, the lower electrode wiring 14A formed on the upper surface of the substrate 10, the insulating film 16, the upper electrode wiring 18, and the air bridge 20 formed by plating or the like.

In the first embodiment of the present invention, the lower electrode wiring 14A formed on the substrate 10 of the MIM capacitor is
It is formed of TaN which is a resistance film of a conductor.

The MIM capacitor shown in FIG.
It is manufactured according to the process sequence as shown in FIGS. 2 to 4 (layers 1 to 5). Hereinafter, each manufacturing process of the resistor R, the MIM capacitor C, and the inductance L will be described in association with the same layer shown in FIGS.

First, in layer 1 (FIG. 2 (2-1)), TaN resistive film 12 having a predetermined pattern is formed on the upper surface of substrate 10 of resistor R and MIM capacitor C, respectively.
And the lower electrode wiring 14A is formed.

In the next layer 2 (FIG. 2 (2-2)),
An insulating film 16 is formed over a predetermined range on each of the resistance film 12 formed on the upper surface of the resistor R and the lower electrode wiring 14A formed on the upper surface of the MIM capacitor C.

In the layer 3 (FIG. 3 (3-1)), the upper electrode wiring 18 having a predetermined pattern is formed on the upper surface of the resistor R, the upper surface of the MIM capacitor C, and the upper surface of the substrate 10 of the inductance L. R finishes the manufacturing process.

Further, in layer 4 (FIG. 3 (3-2)), a resist layer a22 is formed over a predetermined range on the upper surface of the upper electrode wiring 18 of the MIM capacitor C and the inductance L, and on the upper surface thereof. The power feeding layer 26 is formed.

In layer 5 (FIG. 4 (4-1)), the resist layer b24 and the air bridge 20 formed by Au plating are formed on the upper surfaces of the MIM capacitor C and the inductance L. Finish the manufacturing process.

Therefore, the MI manufactured as described above
Since the lower electrode wiring 14A of the M capacitor C uses the same conductor TaN as the resistance film 12, the resistances R and M
On the upper surface of the substrate 10 of the IM capacitor C, a TaN resistance film 12 and a lower electrode wiring 14 each having a predetermined pattern are formed.
A and A can be formed in the same layer.

Therefore, in the above-described manufacturing process according to the present invention, the manufacturing process can be reduced by one layer from the conventional manufacturing process.

FIG. 5 is a cross-sectional view of an essential part showing the structure of the MIM capacitor of the second embodiment manufactured according to the present invention. The lower electrode formed of Ti / Au as a conductor on the substrate 10. The wiring 14 is formed, and the insulating film 1 is formed on the upper surface of the wiring 14.
6 and the resistance film 12 are continuously formed, and then the upper electrode wiring 18 is formed.
Is formed.

Hereinafter, each manufacturing process of the resistor R, the MIM capacitor C, and the inductance L according to the second embodiment will be described with reference to the same layer as shown in FIGS. 6 to 7 (layers 1 to 3). .

First, in the layer 1 (FIG. 6 (6-1)), the lower electrode wiring 14 having a predetermined pattern is formed on the upper surface of the substrate 10 of the MIM capacitor C and the inductance L, respectively.

In the next layer 2 (FIG. 6 (6-2)),
An upper electrode layer 28 formed by continuously forming an insulating film 16 and a resistance film 12 is formed on the upper surface of the substrate 10 of the resistor R and the upper surface of the lower electrode wiring 14 formed on the upper surfaces of the MIM capacitor C and the inductance L, respectively. become.

In Layer 3 (FIG. 7 (7-1)), the upper electrode wiring 18 having a predetermined pattern is formed on the upper surface of the upper electrode layer 28 of the resistor R, the MIM capacitor C and the inductance L, and the resistor R is formed. , The manufacturing process of the MIM capacitor C and the inductance L is completed.

FIG. 8 is a plan view of the inductance L obtained by the manufacturing process shown in FIGS. 6 to 7, and the lower electrode wiring 14 is formed on the substrate 10 by the layer 1.
It is formed in a spiral shape on the upper surface of the above, and a part of the lower electrode wiring 14 by the layer 2 is bridged by the upper electrode layer 28 by the insulating film 16 and the resistance film 12.

Therefore, in the manufacturing process shown in FIGS. 6 to 7, the manufacturing process of the resistor R and the inductance L is matched with the manufacturing process of the MIM capacitor C, so that only three layers are provided. The device can be manufactured.

[0041]

Since the present invention is constructed as described above, it has the following effects.

Since the resistance film and the lower electrode wiring are formed in the same manufacturing process, or the resistance film and the upper electrode wiring are formed in the same manufacturing process and are formed in the same layer, the number of layers can be reduced.

Since the same conductor TaN as that of the resistance film is used for the lower electrode wiring of the capacitor, the resistance film and the lower electrode wiring having a predetermined pattern are formed in the same layer on the upper surface of the substrate of the resistor and the capacitor, respectively. Can be formed.

Further, according to the manufacturing process of the capacitor,
By matching the manufacturing process of the resistance and the inductance, it is possible to manufacture all the constituent elements with only three layers.

Therefore, according to the present invention, it is possible to reduce the number of layers as compared with the conventional case, the number of manufacturing steps and the manufacturing period can be significantly reduced, and the manufacturing cost of the IC can be reduced. Like

[Brief description of drawings]

FIG. 1 is a first embodiment M manufactured according to the present invention.
It is a sectional view of the important section showing the structure of an IM capacitor.

FIG. 2 is an explanatory view showing a manufacturing process of the thin film capacitor according to the first embodiment of the present invention.

FIG. 3 is an explanatory view showing a manufacturing process of the thin film capacitor according to the first embodiment of the present invention.

FIG. 4 is an explanatory view showing a manufacturing process of the thin film capacitor according to the first embodiment of the present invention.

FIG. 5 is a second example M manufactured according to the present invention.
It is a sectional view of the important section showing the structure of an IM capacitor.

FIG. 6 is an explanatory view showing a manufacturing process of the MIM capacitor according to the second embodiment of the present invention.

FIG. 7 is an explanatory view showing the manufacturing process of the MIM capacitor according to the second embodiment of the present invention.

8 is a view of the inductance L in the layer 3 of FIG. 7 as viewed from the direction of arrow A, showing a plan view of the inductance L manufactured according to FIGS. 6 to 7. FIG.

FIG. 9 is a cross-sectional view of a main part showing the structure of a conventional MIM capacitor.

FIG. 10 is an explanatory diagram showing a manufacturing process of a conventional MIM capacitor.

FIG. 11 is an explanatory view showing a manufacturing process of a conventional MIM capacitor.

FIG. 12 is an explanatory view showing a manufacturing process of a conventional MIM capacitor.

[Explanation of symbols]

 10 Substrate 12 Resistive Film 14A Lower Electrode Wiring 16 Insulating Film 18 Upper Electrode Wiring 20 Air Bridge 22 Resist Layer a 24 Resist Layer b 26 Power Supply Layer

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification code Internal reference number FI Technical display 8832-4M H01L 27/04 P 8832-4ML

Claims (5)

[Claims] 1. A resistance element, an inductance element, and
In a method of manufacturing a semiconductor integrated circuit including a thin film capacitor, when forming a resistive film, a lower electrode wiring, an insulating layer, an upper electrode wiring and an aerial wiring on the substrate of each component in a layered manner, the resistive film and the A method of manufacturing a semiconductor integrated circuit, comprising forming the lower electrode wiring in the same manufacturing process. 2. A thin film capacitor which is a constituent element of a semiconductor integrated circuit, wherein when a resistive film, a lower electrode wiring, an insulating layer, an upper electrode wiring, an aerial wiring, etc. are formed in layers on the substrate, the thin film capacitor is formed on the substrate. A thin film capacitor, characterized in that TaN is used for the lower electrode wiring to be formed. 3. A resistance element, an inductance element, and
In a method of manufacturing a semiconductor integrated circuit including a thin film capacitor, when forming a resistive film, a lower electrode wiring, an insulating layer, an upper electrode wiring and an aerial wiring on the substrate of each component in a layered manner, the resistive film and the A method of manufacturing a semiconductor integrated circuit, comprising forming the upper electrode wiring in the same manufacturing process. 4. A thin film capacitor, which is a constituent element of a semiconductor integrated circuit, wherein a resistive film, a lower electrode wiring, an insulating layer, an upper electrode wiring, an aerial wiring and the like are formed in layers on the substrate, A thin film capacitor, characterized in that TaN is used for the formed upper electrode wiring. 5. A resistance element, an inductance element, and
In a method for manufacturing a semiconductor integrated circuit including a thin film capacitor, when forming a resistive film, a lower electrode wiring, an insulating layer, an upper electrode wiring and an aerial wiring on the substrate of each of the constituent elements in layers, A method of manufacturing a semiconductor integrated circuit, comprising: forming a lower electrode wiring, successively forming an insulating film and a resistance film on the upper surface thereof, and forming an upper electrode wiring on the upper surface thereof, in a three-layer structure.