KR100240647B1 - Method of manufacturing a capacitor of semiconductor device - Google Patents
Method of manufacturing a capacitor of semiconductor device Download PDFInfo
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- KR100240647B1 KR100240647B1 KR1019970039496A KR19970039496A KR100240647B1 KR 100240647 B1 KR100240647 B1 KR 100240647B1 KR 1019970039496 A KR1019970039496 A KR 1019970039496A KR 19970039496 A KR19970039496 A KR 19970039496A KR 100240647 B1 KR100240647 B1 KR 100240647B1
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- 239000003990 capacitor Substances 0.000 title claims abstract description 48
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 24
- 239000004065 semiconductor Substances 0.000 title claims abstract description 22
- 229910052751 metal Inorganic materials 0.000 claims abstract description 38
- 239000002184 metal Substances 0.000 claims abstract description 38
- 238000000034 method Methods 0.000 claims abstract description 22
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 18
- 239000010703 silicon Substances 0.000 claims abstract description 18
- 239000000758 substrate Substances 0.000 claims abstract description 12
- 239000010410 layer Substances 0.000 claims description 37
- 239000011229 interlayer Substances 0.000 claims description 12
- 238000000151 deposition Methods 0.000 claims description 9
- MAKDTFFYCIMFQP-UHFFFAOYSA-N titanium tungsten Chemical compound [Ti].[W] MAKDTFFYCIMFQP-UHFFFAOYSA-N 0.000 claims description 8
- 229910052782 aluminium Inorganic materials 0.000 claims description 4
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 4
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 2
- 238000005530 etching Methods 0.000 claims description 2
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 2
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 abstract description 16
- 230000003071 parasitic effect Effects 0.000 abstract description 8
- 238000001465 metallisation Methods 0.000 abstract description 5
- 230000000694 effects Effects 0.000 abstract 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 5
- 229920005591 polysilicon Polymers 0.000 description 5
- 238000007796 conventional method Methods 0.000 description 2
- 239000010931 gold Substances 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
- H01L27/0611—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region
- H01L27/0641—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region without components of the field effect type
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/5222—Capacitive arrangements or effects of, or between wiring layers
- H01L23/5223—Capacitor integral with wiring layers
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/5227—Inductive arrangements or effects of, or between, wiring layers
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
- H01L27/0611—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region
- H01L27/0617—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region comprising components of the field-effect type
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
- H01L28/10—Inductors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
- H01L28/40—Capacitors
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Abstract
본 발명은 반도체 소자의 캐패시터 제조 방법에 관한 것으로, 특히 모노리딕 실리콘 고주파 집적회로에 적용되는 엠 아이 엠(이하 MIM이라 한다) 캐패시터 제조 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a capacitor of a semiconductor device, and more particularly to a method for manufacturing a capacitor (hereinafter referred to as MIM) applied to a monolithic silicon high frequency integrated circuit.
고주파 직접회로에 적용되는 스파이럴 인덕터 및 캐패시터의 제조시, 실리콘 기판의 도전성으로 인한 전자파의 손실 및 금속선의 저항과 기판 사이의 기생성분 등의 영향때문에, 큰 캐패시턴스를 가지면서 성능이 우수한 캐패시터를 구현하는데 많은 어려움이 있다. 특히 MIM 캐패시터 제조시, 다층 금속배선 공정에서 캐패시터를 위한 여분의 금속배선 공정이 필요하므로 공정이 복잡해지고 수율이 떨어지는 문제점이 발생한다.When manufacturing spiral inductors and capacitors applied to high frequency integrated circuits, due to the loss of electromagnetic waves due to the conductivity of silicon substrates and the effects of resistance of metal wires and parasitic components between the substrates, a high capacitance and high performance capacitor is realized. There are many difficulties. In particular, when manufacturing a MIM capacitor, a redundant metallization process for the capacitor is required in the multilayer metallization process, resulting in a complicated process and a low yield.
본 발명에서는 여분의 금속배선 공정이 필요 없고 모노리딕 실리콘 고주파 집적회로에 적용되는 MIM 캐패시터의 새로운 제조 방법을 제시한다.The present invention proposes a novel method for manufacturing a MIM capacitor that is applied to a monolithic silicon high frequency integrated circuit without the need for an extra metallization process.
Description
본 발명은 반도체 소자의 캐패시터(capacitor) 제조 방법에 관한 것으로, 특히 모노리딕(monolithic) 실리콘 고주파(RF) 집적회로(IC)에 적용되는 MIM 캐패시터 제조 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a capacitor of a semiconductor device, and more particularly, to a method of manufacturing a MIM capacitor applied to a monolithic silicon high frequency (RF) integrated circuit (IC).
집적회로에서 캐패시터는 없어서는 안될 중요한 회로 구성 요소이다. 종래의 실리콘 집적회로는 주로 수백 ㎒ 이하의 낮은 주파수에서 사용되므로 캐패시터의 퀄리티(quality)가 그다지 중요하지는 않았다. 그러나 최근의 실리콘 집적회로에서는 ㎓ 이상의 높은 주파수에서도 적용 가능성이 연구되고 있으므로 스파이럴 인덕터(spiral inductor)와 더불어 높은 퀄리티의 캐패시터가 필요하게 되었다.In integrated circuits, capacitors are an integral circuit component. Since the conventional silicon integrated circuit is mainly used at low frequencies of several hundred MHz or less, the quality of the capacitor was not very important. However, in recent silicon integrated circuits, the applicability is being studied even at high frequencies above ㎓, which requires a high quality capacitor along with a spiral inductor.
종래의 실리콘 집적회로에서는 실리콘/산화막/폴리실리콘 구조 및 폴리실리콘/산화막/폴리실리콘 구조의 캐패시터가 주로 사용되어 왔다. 그러나 폴리실리콘의 높은 저항 때문에 높은 주파수에서는 성능이 떨어지게 되고, 이러한 이유로 마이크로웨이브(microwave) 주파수에서 사용되는 MMIC는 주로 금속/산화막/금속 구조의 MIM 캐패시터를 사용하게 되었다.In conventional silicon integrated circuits, capacitors having a silicon / oxide film / polysilicon structure and a polysilicon / oxide film / polysilicon structure have been mainly used. However, due to the high resistance of polysilicon, performance is deteriorated at high frequencies. For this reason, MMICs used at microwave frequencies mainly use metal / oxide / metal structure MIM capacitors.
도 1은 종래의 방법에 의한 반도체 소자의 캐패시터 제조 방법을 설명하기 위해 도시한 단면도이다.1 is a cross-sectional view for explaining a capacitor manufacturing method of a semiconductor device by a conventional method.
실리콘 기판(11)상의 산화막(12) 및 제 1 층간절연막(13)이 순차적으로 적층되어 있는 구조 상부에 제 1 금속층(14), 유전체막(15) 및 제 2 금속층(16)을 순차적으로 증착하여 MIM 구조의 캐패시터를 제조한다. 이렇게 제조된 캐패시터 상부에 제 2 층간절연막(17)을 증착하고 패터닝하여 캐패시터 배선용 제 3 금속층(18)을 콘택 시킨다.The first metal layer 14, the dielectric film 15, and the second metal layer 16 are sequentially deposited on the structure in which the oxide film 12 and the first interlayer insulating film 13 on the silicon substrate 11 are sequentially stacked. To produce a capacitor of the MIM structure. The second interlayer insulating film 17 is deposited and patterned on the capacitor thus manufactured to contact the
그런데 위와 같이 제조된 MIM 캐패시터는 원하지 않는 기생저항 및 기생용량 등으로 인하여 MIM 캐패시터의 주요 특성 변수인 퀄리티 팩터(quality factor)가 낮아지고, 자기 공명 주파수(self resonant frequency)가 낮아져서 고주파 집적회로에 적용할 때 문제가 발생하게 된다. 이러한 문제점을 해결하기 위해서는 기생저항 및 기생용량을 감소시켜야 하는데, 저항이 적은 금속인 금(Au)을 인터커넥트(interconnect)로 사용하거나, 금속막을 두껍게 사용함으로써 기생저항을 줄일수 있다. 또한 기생 용량을 줄이기 위해서는 실리콘 기판과 유전체의 두께를 증가시킴으로써 수동 소자의 성능을 개선 시킬 수 있다.However, the MIM capacitors manufactured as described above are applied to high frequency integrated circuits because they have low quality factor, which is a main characteristic variable of MIM capacitors, and low self resonant frequency due to unwanted parasitic resistance and parasitic capacitance. The problem arises. In order to solve this problem, parasitic resistance and parasitic capacitance should be reduced, and parasitic resistance can be reduced by using gold (Au), which is a low resistance metal, as an interconnect, or by using a thick metal film. To reduce the parasitic capacitance, the silicon substrate and the dielectric thickness can be increased to improve the performance of passive devices.
그러나 현재 실리콘 CMOS 제조 공정에서는 저항이 큰 폴리실리콘을 많이 사용하기 때문에 고성능 MIM 캐패시터의 제조에 제약을 주고 있다. 또한 MIM 캐패시터를 만들기 위해서는 다층 배선 공정에 캐패시터를 위한 여분의 금속배선 공정을 추가해야 하므로 공정이 복잡해지고 수율이 떨어질 가능성이 높아지게 된다.However, current silicon CMOS manufacturing processes use a lot of high-resistance polysilicon, which limits the manufacturing of high performance MIM capacitors. In addition, to make MIM capacitors, an extra metallization process for capacitors must be added to the multi-layer wiring process, which increases the complexity and yields.
본 발명은 금속배선 공정을 단순화 시키면서도 퀄리티 팩터가 큰, 모노리딕 실리콘 고주파 집적회로에 적용되는 MIM 캐패시터를 제조하는데 그 목적이 있다.It is an object of the present invention to manufacture a MIM capacitor applied to a monolithic silicon high frequency integrated circuit having a large quality factor while simplifying a metallization process.
상술한 목적을 달성하기 위한 본 발명에 따른 반도체 소자의 캐패시터 제조 방법은, 반도체 기판상의 산화막 및 제 1 층간절연막이 순차적으로 적층되어 있는 구조 상부에 제 1 금속층을 증착하는 단계와, 상기 제 1 금속층 상부에 제 2 층간 절연막을 증착한 후, 상기 제 2 층간 절연막의 선택된 영역을 식각하여 제 1 금속층이 노출되도록 패터닝 하는 단계와, 상기 노출된 제 1 금속층을 포함하는 전체구조 상부에 유전체막 및 제 2 금속층을 순차적으로 증착하는 단계를 포함하여 이루어져, 제 1 금속층 및 제 2 금속층의 두 층 배선만으로 엠.아이.엠 캐패시터 및 스파이럴 인덕터가 동시에 제작 가능한 것을 특징으로 한다.According to another aspect of the present invention, there is provided a method of manufacturing a capacitor of a semiconductor device, the method including: depositing a first metal layer on a structure in which an oxide film and a first interlayer insulating film on a semiconductor substrate are sequentially stacked; After depositing a second interlayer insulating film thereon, etching the selected region of the second interlayer insulating film to pattern the first metal layer to expose the first metal layer, and forming a dielectric film and a first layer on the entire structure including the exposed first metal layer. It comprises a step of depositing a second metal layer, characterized in that the M. I. M capacitor and the spiral inductor can be manufactured at the same time only by the two-layer wiring of the first metal layer and the second metal layer.
도 1은 종래의 방법에 의한 반도체 소자의 캐패시터 제조 방법을 설명하기 위해 도시한 단면도.BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a cross-sectional view for explaining a method of manufacturing a capacitor of a semiconductor device by a conventional method.
도 2(a) 내지 도 2(c)는 본 발명에 따른 반도체 소자의 캐패시터 제조 방법을 설명하기 위해 도시한 단면도.2 (a) to 2 (c) are cross-sectional views illustrating a method of manufacturing a capacitor of a semiconductor device according to the present invention.
도 3은 본 발명에 의해 제조된 캐패시터가 적용된 집적회로의 단위 셀 단면도.3 is a cross-sectional view of a unit cell of an integrated circuit to which a capacitor manufactured according to the present invention is applied.
＜도면의 주요 부분에 대한 부호 설명＞<Explanation of symbols on the main parts of the drawing>
11 및 21 : 반도체 기판 12 및 22 : 산화막11 and 21: semiconductor substrate 12 and 22: oxide film
13 및 23 : 제 1 층간절연막 14 및 24 : 제 1 금속층13 and 23: first interlayer insulating film 14 and 24: first metal layer
15 및 26 : 유전체막 16 및 27 : 제 2 금속층15 and 26: dielectric film 16 and 27: second metal layer
17 및 25 : 제 2 층간절연막 18 : 제 3 금속층17 and 25: second interlayer insulating film 18: third metal layer
이하, 첨부된 도면을 참조하여 본 발명을 상세히 설명하기로 한다.Hereinafter, with reference to the accompanying drawings will be described in detail the present invention.
도 2(a) 내지 도 2(c)는 본 발명에 따른 반도체 소자의 캐패시터 제조 방법을 설명하기 위해 도시한 단면도이다.2 (a) to 2 (c) are cross-sectional views illustrating a method of manufacturing a capacitor of a semiconductor device according to the present invention.
도 2(a)는 반도체 기판(21)상의 산화막(22) 및 제 1 층간절연막(23)이 순차적으로 적층된 구조 상부에 제 1 금속층(24)을 증착한 단면도이다. 이 때 반도체 기판(21)은 기생용량을 줄이기 위하여 저항값이 500 ∼ 20,000 Ω㎝인 고저항 실리콘 반도체 기판을 사용한다. 제 1 금속층(24)은 타이타늄텅스텐(TiW)/실리콘이 1 % 포함된 알루미늄(Al-Si)/타이타늄텅스텐(TiW)의 3중 구조로 이루어 진다.FIG. 2A is a cross-sectional view of depositing a first metal layer 24 on a structure in which an oxide film 22 and a first interlayer insulating film 23 on a semiconductor substrate 21 are sequentially stacked. At this time, in order to reduce the parasitic capacitance, the semiconductor substrate 21 uses a high resistance silicon semiconductor substrate having a resistance value of 500 to 20,000 cm 3. The first metal layer 24 has a triple structure of aluminum (Al-Si) / titanium tungsten (TiW) containing 1% of titanium tungsten (TiW) / silicon.
도 2(b)에 도시된 것과 같이, 제 1 금속층(24) 상부에 제 2 층간절연막(25)을 증착한 후, 캐패시터가 형성되는 부분을 식각하여 제 1 금속층(24)이 노출되도록 패터닝 한다.As shown in FIG. 2B, after depositing the second interlayer insulating layer 25 on the first metal layer 24, the portion where the capacitor is formed is etched and patterned to expose the first metal layer 24. .
위와 같은 과정으로 캐패시터 형성 영역을 만든 후, 도 2(c)와 같이, 전체 구조 상부에 유전체막(26)을 40 ∼ 300 ㎚ 두께로 증착한다. 유전체막(26)은 실리콘 질화막 또는 실리콘 산화막을 사용한다. 유전체막(26) 상부에 제 2 금속층(27)을 증착하여 캐패시터를 제조한다. 제 2 금속층(27)은 제 1 금속층(24)과 같은 타이타늄텅스텐(TiW)/실리콘이 1 % 포함된 알루미늄(Al-Si)/타이타늄텅스텐(TiW)의 3중 구조로 이루어 진다.After the capacitor formation region is formed in the same manner as described above, as shown in FIG. 2C, the dielectric film 26 is deposited to a thickness of 40 to 300 nm on the entire structure. The dielectric film 26 uses a silicon nitride film or a silicon oxide film. The second metal layer 27 is deposited on the dielectric layer 26 to manufacture a capacitor. The second metal layer 27 has a triple structure of aluminum (Al-Si) / titanium tungsten (TiW) containing 1% of titanium tungsten (TiW) / silicon as the first metal layer 24.
도 3은 본 발명에 의해 제조된 캐패시터가 적용된 집적회로의 단위 셀 단면도써, A는 CMOS 구조의 능동 소자이고, B는 본 발명에 의한 방법으로 제조된 MIM 캐패시터, C는 저항이며 D는 스파이럴 인덕터이다.3 is a cross-sectional view of a unit cell of an integrated circuit to which a capacitor manufactured by the present invention is applied, where A is an active element of a CMOS structure, B is a MIM capacitor manufactured by the method according to the present invention, C is a resistor, and D is a spiral inductor. to be.
본 발명에 의해서 제 2 금속층(27)은 캐패시터의 배선으로도 이용되므로 종래의 캐패시터 상부에 형성하는 금속배선 공정을 생략할 수 있다. 또한 제 2 금속층(27)이 캐패시터의 탑 플레이트(top plate)로도 사용되므로 공정의 단순화와 함께 소자의 수율을 향상시킬 수 있다.According to the present invention, since the second metal layer 27 is also used as the wiring of the capacitor, the metal wiring process formed on the conventional capacitor can be omitted. In addition, since the second metal layer 27 is also used as a top plate of the capacitor, it is possible to simplify the process and improve the yield of the device.
상술한 바와 같이 본 발명에 의하면 별도의 캐패시터 금속배선 공정 없이, 다층배선 공정을 수행하면서 배선, MIM 캐패시터 및 스파이럴 인덕터가 동시에 제작되므로 구주파 집적회로의 제조 공정이 간단해지고 수율이 증대 된다. 또한 퀄리티 팩터가 큰 캐패시터 제조로 주파수 범위가 1 ∼ 2 ㎓ 영역인 LNA 및 PCS용 실리콘 고주파 집적회로가 가능해지고 하나의 칩 안에 디지털 집적회로, 아날로그 집적회로 및 고주파 집적회로를 모두 집적할 수 있게 된다.As described above, according to the present invention, since the wiring, the MIM capacitor, and the spiral inductor are simultaneously manufactured while performing the multilayer wiring process without a separate capacitor metal wiring process, the manufacturing process of the rectangular wave integrated circuit is simplified and the yield is increased. In addition, the manufacture of capacitors with large quality factors enables silicon high frequency integrated circuits for LNA and PCS in the frequency range of 1 to 2 kHz, and it is possible to integrate digital integrated circuits, analog integrated circuits and high frequency integrated circuits in one chip. .
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| KR1019970039496A KR100240647B1 (en) | 1997-08-20 | 1997-08-20 | Method of manufacturing a capacitor of semiconductor device |
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| JP3918442B2 (en) * | 2001-02-19 | 2007-05-23 | ソニー株式会社 | Semiconductor device and manufacturing method thereof |
| KR100412128B1 (en) * | 2001-04-19 | 2003-12-31 | 주식회사 하이닉스반도체 | Method for manufacturing capacitor of semiconductor device |
| KR20030002604A (en) * | 2001-06-29 | 2003-01-09 | 주식회사 하이닉스반도체 | A method for forming a metal-insulator-metal capacitor |
| KR100414733B1 (en) * | 2001-06-29 | 2004-01-13 | 주식회사 하이닉스반도체 | A method for forming a metal-insulator-metal capacitor |
| KR100434699B1 (en) * | 2001-12-13 | 2004-06-07 | 주식회사 하이닉스반도체 | Method for forming inductor of semiconductor device |
| KR100527868B1 (en) * | 2003-12-23 | 2005-11-15 | 동부아남반도체 주식회사 | MIM capacitor with high capacitance and fabricating method thereof |
| JP4762531B2 (en) * | 2004-11-30 | 2011-08-31 | 太陽誘電株式会社 | Electronic component and manufacturing method thereof |
| KR100617056B1 (en) * | 2004-12-30 | 2006-08-30 | 동부일렉트로닉스 주식회사 | The method for preventing attack during via etching |
| KR101764761B1 (en) | 2015-09-07 | 2017-08-04 | 전자부품연구원 | Passive device and manufacturing method thereof |
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