JPS61137356A - Fine circuit element - Google Patents

Fine circuit element

Info

Publication number
JPS61137356A
JPS61137356A JP59260369A JP26036984A JPS61137356A JP S61137356 A JPS61137356 A JP S61137356A JP 59260369 A JP59260369 A JP 59260369A JP 26036984 A JP26036984 A JP 26036984A JP S61137356 A JPS61137356 A JP S61137356A
Authority
JP
Japan
Prior art keywords
circuit element
film
circuit
resistor
transistor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP59260369A
Other languages
Japanese (ja)
Inventor
Tadahisa Inoue
井上　忠久
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP59260369A priority Critical patent/JPS61137356A/en
Publication of JPS61137356A publication Critical patent/JPS61137356A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
    • H01L27/0688—Integrated circuits having a three-dimensional layout
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04042—Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191—Disposition
    • H01L2924/19101—Disposition of discrete passive components
    • H01L2924/19105—Disposition of discrete passive components in a side-by-side arrangement on a common die mounting substrate

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Semiconductor Integrated Circuits (AREA)

Abstract

PURPOSE:To obtain a small-sized fine circuit element by forming a circuit element such as a transistor and diode on the surface layer of a semiconductor substrate, coating an Si3N4 film on the substrate, separating from the circuit, forming a resistance element on the film, and connecting them by aluminum wirings. CONSTITUTION:Function elements 2 such as a transistor and a diode are formed on the surface layer of an Si wafer 1, and a plasma Si3N4 film 3 is coated on the overall surface. Then, a resistor 4 made of a Ta film is formed by low temperature magnetron sputtering at the position separate from the element 2, and the passive element is connected with the element 2 by aluminum wirings 5. Thus, the mounting efficiency is improved to further reduce the side of an ultrafine circuit element.

Description

【発明の詳細な説明】 〔産業上の利用分野１ 本発明は微小回路素子に係シ、特に半導体複合素子及び
受動素子ネットワークを同一シリコン拳ウェハ上に形成
した微小回路素子に関する。DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field 1] The present invention relates to a microcircuit device, and particularly to a microcircuit device in which a semiconductor composite device and a passive device network are formed on the same silicon wafer.

〔従来技術〕[Prior art]

軽、＃、短、小等の近年電子部品に要求される小型化の
傾向が増々増大している。例えば、移動通信機器にみら
れるページャ−などはその好例であろう。また、装置の
ライフサイクルも年々短くなりて来ておシ、このためこ
れを構成する電子部品のデリバリ−の早さが強く要求さ
れる。これ等両者の特徴を有するノ・イブリッドＩＣの
成長が近年者しい。ノーイブリッドＩＣｉ構成する素子
としては、半導体集積回路（以下ＩＣと称する）及び複
数のトランジスタ、ダイオードから成る能動素子と、複
数のコンデ／ｆ、抵抗体から成る受動素子を含むのが一
般的である。In recent years, there has been an increasing trend toward miniaturization of electronic components such as light, ##, short, and small. For example, pagers found in mobile communication devices are a good example. Furthermore, the life cycle of devices is becoming shorter year by year, and therefore there is a strong demand for rapid delivery of the electronic components that make up the devices. Hybrid ICs, which have these characteristics of both, have been growing rapidly in recent years. The elements constituting the no-brid IC generally include a semiconductor integrated circuit (hereinafter referred to as IC), an active element consisting of a plurality of transistors and diodes, and a passive element consisting of a plurality of capacitors and resistors. .

このハイブリッドＩＣＩ構成するＩＣパッケージ形態と
しては、ミンクラフト、ミノモールドと称する小型化モ
ールドタイプか、第３図に示すペアチップ８のタイプか
のいずれかを用いるのが通常である。これ等の部品は、
印刷またはスノくツタリング等によシ形成された抵抗体
４を有するアルミナセラミック基板７上に搭載される。As the IC package form for configuring this hybrid ICI, either a miniaturized mold type called Mincraft or Minomold, or a paired chip 8 type shown in FIG. 3 is usually used. These parts are
It is mounted on an alumina ceramic substrate 7 having a resistor 4 formed by printing or slatting.

この場合、モールドタイプはソルダリングによシ、また
ペアチップ８のタイプはマウント、ワイヤボンディング
によ）それぞれ接続される。特に、よシ小型化が必要な
場合には、モールドタイプに比べて小型化が可能なペア
チップ８０タイプが使用される。In this case, the mold type is connected by soldering, and the pair chip 8 type is connected by mounting and wire bonding. Particularly, when miniaturization is required, the pair chip 80 type, which can be made smaller than the mold type, is used.

しかるに、ペアチップ８のタイプに於ては、アルミナセ
ラミック基板７上に形成された抵抗体４のトリミング上
の関係から、またコンデンサの場合にはその構造上の関
係から、ペアチップ８を抵抗体４やコンデンサを有する
エリアの上部にはマウント出来ない。このため、実装ス
ペース的に限界があシ、よシ小型化に対する要求を満足
できない間°題がしばしば生ずる。However, in the type of pair chip 8, due to the trimming relationship of the resistor 4 formed on the alumina ceramic substrate 7, and due to the structural relationship in the case of a capacitor, the pair chip 8 is It cannot be mounted above the area containing the capacitor. For this reason, there is often a problem in that the mounting space is limited and the demand for miniaturization cannot be satisfied.

〔発明が解決しようとする問題点〕[Problem that the invention seeks to solve]

本発明の目的は、前記問題を解決し、実装効率を向上さ
せ、よシ小型化を実現した微小回路素子を提供すること
にある。SUMMARY OF THE INVENTION An object of the present invention is to solve the above-mentioned problems, improve mounting efficiency, and provide a microcircuit element that is more compact.

〔問題点を解決するための手段〕[Means for solving problems]

本発明の微小回路素子は、半導体基板に回路素子を設け
、さらに前記半導体基板上に薄膜からなる受動素子を設
け、前記回路素子と前記受動素子とを導体配線で結んだ
ことを特徴とする。The microcircuit element of the present invention is characterized in that a circuit element is provided on a semiconductor substrate, a passive element made of a thin film is further provided on the semiconductor substrate, and the circuit element and the passive element are connected by conductive wiring.

〔実施例〕 次に図面を参照しながら本発明の詳細な説明する。〔Example〕 Next, the present invention will be described in detail with reference to the drawings.

第１図は本発明の実施例の微小回路素子を示す断面図で
ある。同図において、通常の半導体プロセスによりシリ
コン・ウェハ１上に形成されたトランジスタまたはダイ
オード２のバッジベージ讐ン膜として、表面にプラズマ
窒化膜３が生成される。この窒化膜３を絶縁層として、
例えば低温マグネトロンスパッタリングによシ抵抗体４
となるべきタンタルが窒化膜３上に蒸着される。次にホ
トリングラフィ工程によシ所要のパターンにタンタルが
エツチングされ、抵抗体４が形成される。FIG. 1 is a sectional view showing a microcircuit element according to an embodiment of the present invention. In the figure, a plasma nitride film 3 is produced on the surface of a transistor or diode 2 formed on a silicon wafer 1 by a normal semiconductor process. This nitride film 3 is used as an insulating layer,
For example, by low-temperature magnetron sputtering, the resistor 4
Tantalum, which is to become , is deposited on the nitride film 3. Next, tantalum is etched into a desired pattern using a photolithography process to form the resistor 4.

これ等抵抗体４と予め形成されているトランジスタ、ダ
イオードとは、例えばアルミニウム配線５によシ結線さ
れ、同一シリコン・ウェハ１上に所望の回路網が構成さ
れる。These resistors 4 and previously formed transistors and diodes are connected to, for example, aluminum wiring 5, and a desired circuit network is constructed on the same silicon wafer 1.

以上、第１図に従って本発明の詳細な説明したが、本発
明はこれに限定されるものではない。Although the present invention has been described above in detail with reference to FIG. 1, the present invention is not limited thereto.

例えば、第１図において抵抗体４のみならず、コンデン
サを単独にあるいは抵抗体４と併せてＣ几ネットワーク
を形成することも可能である。、ｉた、他の実施例とし
ては、トランジスタ、ダイオードに限らず、ＩＣと受動
素子ネットワークとの同一シリコン・ウェハ上での結線
が可能であることは当然である。さらに、また他の実施
例としては、絶縁層を介して、トランジスタ、ダイオー
ド、ＩＣ等半導体素子を形成しているエリア上に三次元
的にＣ几素子を形成し、それぞれを結線し、回路機能を
構成することも可能である。For example, in addition to the resistor 4 shown in FIG. 1, it is also possible to form a C-type network using a capacitor alone or in combination with the resistor 4. In other embodiments, it is of course possible to connect not only transistors and diodes but also ICs and passive element networks on the same silicon wafer. Furthermore, as another embodiment, C elements are three-dimensionally formed on areas where semiconductor elements such as transistors, diodes, and ICs are formed through an insulating layer, and each is connected to perform a circuit function. It is also possible to configure

さらに、第２図に示す通シ、本実施例の微小回路素子６
を例えばアルミナセラミック基板７上に搭載し、ハイブ
リッドＩＣを構成する場合には、前述した受動素子忙よ
る技術的、スペース的制限がないため、アルミナセラミ
ック基板上のどの位置にもマウントすることが可能であ
り実装効率が著しく向上し、より一層の小型化が実現で
きる。Further, as shown in FIG. 2, the microcircuit element 6 of this embodiment
For example, when mounting on an alumina ceramic substrate 7 to form a hybrid IC, there is no technical or space limitation due to the passive elements mentioned above, so it can be mounted at any position on the alumina ceramic substrate. This significantly improves mounting efficiency and enables further miniaturization.

〔発明の効果〕〔Effect of the invention〕

本発明によれば、以上説明したように、半導体素子を形
成しているシリコンΦウェハと同一ウェハ上にＣ８受動
素子を形成することができるため、アルミナセラミック
基板に形成する必要がなく、例えば薄膜技術を応用した
ファインパターン化が可能でちゃ、従りて従来のアルミ
ナセラミック上に形成した受動素子よりも一層の小型化
が実現できるという効果が得られる。According to the present invention, as explained above, since the C8 passive element can be formed on the same wafer as the silicon Φ wafer on which the semiconductor element is formed, it is not necessary to form it on the alumina ceramic substrate. If it is possible to create a fine pattern by applying technology, it will be possible to achieve an effect of realizing further miniaturization than passive elements formed on conventional alumina ceramics.

【図面の簡単な説明】[Brief explanation of drawings]

第１図は本発明の実施例の微小回路素子を示す断面図、
第２図は第１図の微小回路素子を搭載したハイブリッド
ＩＣ構造例を示す断面図、３１３図は従来の部品を搭載
したハイブリッドＩＣ構造例を示す断面図である。 同図において、１・・・・・・シリコン・ウェハ、２・
・・・・・トランジスタ、３・・・・・・窒化膜、４・
・・・・・抵抗体、５・・・・・・アルミニウム配線、
６・・・・・・微小回路素子、７・・・・・・アルミナ
セラミック基板、８・・・・・・ペアチップ。FIG. 1 is a sectional view showing a microcircuit element according to an embodiment of the present invention;
FIG. 2 is a sectional view showing an example of a hybrid IC structure in which the microcircuit elements of FIG. 1 are mounted, and FIG. 313 is a sectional view showing an example of a hybrid IC structure in which conventional components are mounted. In the figure, 1... silicon wafer, 2...
...Transistor, 3...Nitride film, 4.
...Resistor, 5...Aluminum wiring,
6...Micro circuit element, 7...Alumina ceramic substrate, 8...Pair chip.

Claims (1)

【特許請求の範囲】[Claims] 　半導体基板に回路素子を設け、さらに前記半導体基板
上に薄膜からなる受動素子を設け、前記回路素子と前記
受動素子とを導体配線で結んだことを特徴とする微小回
路素子。1. A microcircuit element comprising a circuit element provided on a semiconductor substrate, a passive element made of a thin film provided on the semiconductor substrate, and the circuit element and the passive element connected by conductive wiring.
JP59260369A 1984-12-10 1984-12-10 Fine circuit element Pending JPS61137356A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP59260369A JPS61137356A (en) 1984-12-10 1984-12-10 Fine circuit element

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP59260369A JPS61137356A (en) 1984-12-10 1984-12-10 Fine circuit element

Publications (1)

Publication Number Publication Date
JPS61137356A true JPS61137356A (en) 1986-06-25

Family

ID=17346971

Family Applications (1)

Application Number Title Priority Date Filing Date
JP59260369A Pending JPS61137356A (en) 1984-12-10 1984-12-10 Fine circuit element

Country Status (1)

Country Link
JP (1) JPS61137356A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63104337A (en) * 1986-10-20 1988-05-09 Nec Corp Manufacture of semiconductor device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63104337A (en) * 1986-10-20 1988-05-09 Nec Corp Manufacture of semiconductor device

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