JP3322665B2 - High frequency module - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a high-frequency module suitable for a cellular phone or the like.

[0002]

2. Description of the Related Art In a conventional high-frequency module, a strip line including a microstrip line is formed by using a single-sided board, a double-sided board, or a laminated board according to the purpose. It had mounted resistors, capacitors, and even semiconductor components.

FIG. 8 is a schematic perspective view showing an example of a conventional high-frequency module. As shown in FIG. 8, the conventional high-frequency module includes a lower shield layer 105,
Substrate layer 10 on which strip line for resonator is formed
4. A ground layer 103, a top layer 102 on which so-called chip components (resistors, capacitors and other semiconductor components) are mounted, and a metal cap shield case 101
It is of a configuration that is sequentially laminated.

[0004]

In a conventional high-frequency module having the above-described configuration, the shapes of these components are factors that determine the size and thickness of the module. Due to market demands, component manufacturers are paying attention to how to make these chip components smaller and thinner.

[0005] On the other hand, an assembly maker introduces various simulators, including dedicated equipment for high-density mounting, and is proceeding with circuit design. In these situations,
Mobile phones, PDAs (Personal Digital Assistant)
s) and the like are increasingly required to be smaller, thinner and lighter. To meet this need, miniaturization of modules has become essential.

In the conventional module, 1608 (1.6 mm
× 0.5mm) to 1005 (1.0mm × 0.5mm)
The chip size has been shifted to 0603 (0.6 mm
× 0.3mm) Some of the sizes are being used. When shifting from the 1005 size chip to the 0603 size chip, the problems related to the unit cost of components, mounting, mounting equipment, yield, and the like increase exponentially.

[0007] However, as described above, achieving the small size, light weight, and low price of the market needs has not been sufficiently addressed by the underlying technologies. Further, it is necessary to have a prospect of a new technology after the process technology of the 0603-size chip is established, but the conventional technology as described above cannot sufficiently cope with it.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-described problems, and has as its object to provide a small, lightweight, low-cost high-frequency module that can be easily redesigned.

[0009]

In order to achieve the above object, a high-frequency module according to the present invention comprises a plurality of first passive elements formed in an array and an electrical connection between the plurality of first passive elements. A first passive element array layer with wiring, including a first passive element wiring pattern for performing the following, a plurality of second passive elements formed in an array, and an electrical connection between the plurality of second passive elements. A second passive element array layer with wiring, including a second passive element wiring pattern to be performed. A structural feature of the present invention is that the plurality of first passive elements and the plurality of second passive elements are mutually connected in any combination by changing the first and second passive element wiring patterns. Thus, a desired circuit constant can be obtained.

As the first passive element, a resistance element,
One of a capacitor element and an inductor element corresponds to the second passive element, and any of the resistor element, the capacitor element, and the inductor element corresponds to the second passive element.

The high-frequency module according to the present invention is, for example,
The first passive element array layer with wiring and the second passive element array layer with wiring are formed on different surfaces or both on the same surface. In any case, the first passive element wiring pattern and the second passive element wiring pattern are connected by a wiring interposed between the first passive element array layer with wiring and the second passive element array layer with wiring. Electrically connected.

When the first passive element array layer with wiring and the second passive element array layer with wiring are formed on the front and back surfaces of one substrate, respectively, the first passive element wiring pattern and the second passive element array pattern are formed. Electrical connection with the element wiring pattern can be made by a conductive layer formed in a through hole provided through the substrate.

With the above-described structure, according to the present invention, for example, the resistance element, the capacitor element, or the inductor element configured as an array is predetermined regardless of the specific application to which the high-frequency module is applied.
An array of elements having a predetermined resistance value, capacitance value, or inductance value is formed, and a circuit constant required for a desired application can be obtained by combining these elements by changing only the wiring pattern. Since such a high-frequency module can be applied to a wide range of applications, it can be designed as a standard high-frequency module that can respond to various requests. As a result, a large reduction in manufacturing cost is realized, which leads to mass production.

In addition, since only the wiring pattern of each array layer needs to be changed in addition to the circuit design to make the design change, the development time is reduced and the development cost is reduced.

If a resistor array, a core capacitor array, or an inductor array as a passive element array of the high-frequency module of the present invention is formed by using a technique such as printing, vapor deposition, photoetching, and selective plating, the variation accuracy is improved. Therefore, it is possible to form a module that meets the target in terms of module performance, and it has great industrial significance.

Furthermore, since passive elements are not used as chip parts, it is not necessary to handle very small chip parts such as the conventional 0603 size.
Equipment such as expensive mounters is not required.

Further, according to the present invention, since most of the passive components can be formed by forming them on the main surface of the laminated substrate layer, only the active semiconductor components can be used.
For example, it may be mounted on the top layer on the top of the laminate, and conventional equipment can sufficiently cope with the problem.

In a preferred embodiment of the high-frequency module according to the present invention, at least one of a stripline and an active electronic component is arranged on at least one of the upper and lower sides of the first passive element array layer with wiring.

In the high-frequency module according to the present invention, at least one of the plurality of first passive elements and the plurality of second passive elements has the same resistance, capacitance, or inductance. be able to. Further, at least one of the plurality of first passive elements and the plurality of second passive elements forms a plurality of groups, and in each of the plurality of groups, the total number of constituent passive elements has the same resistance and capacitance. It can also be configured to have a value, or inductance value.

This is because the plurality of first passive elements and the plurality of second passive elements are interconnected in any combination by changing only the wiring patterns for the first and second passive elements, respectively. This is because the following circuit constant can be obtained.

[0021]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a cross-sectional view showing a schematic structure of a high-frequency module in which four substrate layers are stacked according to the present embodiment, which are separated for each substrate layer so that boundaries between the substrate layers can be easily understood. is there. This high-frequency module includes a first substrate layer 1 (FIG. 1) as a top substrate layer from above.
(A)), second substrate layer 2 (FIG. 1 (b)), third substrate layer 3
(FIG. 1C) and the fourth substrate layer 4 (FIG. 1D)
Are sequentially laminated. Among these substrate layers, the feature of the present embodiment is that FIG.
Since this is the third substrate layer 3 shown in (c), the third substrate layer 3 will be described first.

In the third substrate layer 3, the insulating substrate 3
A capacitor array layer 3a with wiring including capacitor elements 31 and wiring pattern layers 32a and 32b arranged in an array as a dielectric film is formed on the upper surface of the substrate.
On the lower surface of the insulating substrate 30, a resistance array layer 3c with wiring including a resistance film 34 and a wiring pattern 35 arranged in an array is formed. Further, a via hole 36 is formed in the insulating substrate 30, and via the conductor buried in the via hole 36, the resistance array layer with wiring 3 c is formed.
And the wiring-equipped contentor array layer 3a.
Therefore, the insulating substrate 30 corresponds to the connection layer 3b.

In the capacitor array layer 3 a with wiring on the upper surface of the insulating substrate 30, Ta serving as a dielectric film of the capacitor 31 is formed.
Wiring patterns 32a and 32b including electrodes and wiring made of a conductive material such as Al and Cu are formed so as to sandwich the O ₂ (tantalum oxide) thin film 31a in the vertical direction in the drawing.
The capacitor element 31 is constituted. An insulating film 33 made of a resin material or the like is disposed on the wiring patterns 32a and 32b except for a connection portion (contact portion) with the second substrate layer 2 disposed on the upper portion.

In the resistance array layer 3c with wiring on the lower surface of the insulating substrate 30, the resistance film 3 made of a resistive material such as W is formed.
A wiring pattern 35 including an electrode and a wiring made of a conductive material such as Al or Cu is formed so as to sandwich 4 from both sides in the horizontal direction in the drawing.

A part of the wiring patterns 32a and 32b of the wiring capacitor array layer 3a and a part of the wiring pattern 35 of the wiring resistor array layer 3c are connected by a via hole 36 formed inside the insulating substrate 30. Thus, the insulating substrate 30 functions as the connection layer 3b.

Although only one capacitor element and one resistance element are shown in FIG. 1, actually, a plurality of similar elements are formed in an array.

Since the present embodiment is configured as described above, in the wiring capacitor array layer 3a, by selectively wiring the capacitor elements so as to match the intended circuit by patterning the wiring pattern 32. Accordingly, a capacitance value as a constant required in a circuit can be obtained by a combination of these capacitor elements.

Further, in the resistor array layer 3c with wiring, by patterning the wiring pattern 35, the resistive elements are selectively wired so as to match the target circuit, and these resistive elements are combined to form a circuit. It is possible to obtain a resistance value as a necessary constant.

The upper part of the third substrate layer 3 has the second
The substrate layer 2 is laminated. The second substrate layer 2 includes an insulating substrate 20
The ground conductive layer 23 is formed below the
The connection terminal 24 with the substrate layer 3 is formed. The connection terminal 24 is connected to the wiring-attached capacitor array layer 3 a of the third substrate layer 3.
Is electrically connected to the portion of the wiring pattern 32 where the insulating film 33 is not formed.

The upper portion of the insulating substrate 20 is electrically connected to the connection terminal 24 via a through hole 22 formed inside the insulating substrate 20, so that the upper portion of the insulating substrate 20 is electrically connected to the first substrate layer 1. Are formed.

The first substrate layer 1 (top substrate layer) is laminated on the second substrate layer 2. In the first substrate layer 1, a strip line 14 is completed and a connection terminal 15 with the second substrate layer 2 is formed below the insulating substrate 10. The connection terminals 15 are connected to the connection terminals 21 of the second substrate layer 2.
And are electrically connected.

On the insulating substrate 10, active electric components 11 and a quasi-pattern 12 for wiring them are formed. A part of the wiring pattern 12 is
0, and is electrically connected to the connection terminal 15 through the through hole 13 formed inside.

A fourth substrate layer 4 is laminated below the third substrate layer 3 as described above. In the fourth substrate layer 4, a connection terminal 41 that is electrically connected to a part of the wiring pattern 35 of the wiring array 35 of the third substrate layer 3 is formed on the insulating substrate 40.

A ground surface 43 is formed below the insulating substrate 40, and a connection terminal 44 electrically connected to the connection terminal 41 via a through hole 42 formed inside the insulating substrate 40. Is formed.

The wiring patterns, connection terminals and connection portions, through holes, via holes, and the like shown in FIG. 1 are conceptually drawn and are not limited to the above. It will be applied.

Next, the high-frequency module of this embodiment will be described with reference to FIG. 2, which is a schematic perspective view conceptually showing the high-frequency module.

The resistance array 56 is formed by forming a plurality of resistance elements in an array. The resistance wiring pattern 55 is a wiring pattern of the resistance array 56. The resistor array 56 and the resistor wiring pattern 55 are the third
It corresponds to the resistance-equipped resistance array layer 3 of the substrate layer 3. And
The capacitor array 54 includes a plurality of capacitor elements formed in an array.
b is a wiring pattern of the capacitor array 54. Capacitor array 54 and wiring pattern 5 for capacitor
Reference numerals 3a and 53b correspond to the capacitor array layer with wiring in FIG. In FIG. 2, the wiring patterns 55, 53a, and 53b are illustrated as separate layers separated from the capacitor array 54 and the resistor array for easy understanding. The connection layer 3 shown in FIG. 1 is provided between the wiring pattern 53a for the capacitor array and the wiring pattern 55 for the resistor array.
A connection layer 58 corresponding to “b” is interposed.

According to the present embodiment, with this configuration, for example, the resistor element and the capacitor element configured as the resistor array 54 and the capacitor array 54 may be an array of elements having constant resistance and capacitance, respectively. A constant required for the circuit can be obtained by a combination of these elements. In the case of a module for a specific use, it can usually be dealt with by changing the circuit constants, so that the wiring patterns 55, 53a, 53
Various requests can be met by changing only b.

A strip line 52 (corresponding to the strip line 14 of the first substrate 1 in FIG. 1) is disposed above the capacitor wiring pattern 53b, and a top shield substrate 51 (not shown in FIG. 1) is further disposed thereon. ) Is arranged. A lower surface shield layer 57 (the ground surface 4 of the first fourth substrate layer 4 in FIG.
3).

In the above embodiment, the capacitance values of the plurality of capacitor elements constituting the capacitor array layer 3a with wiring in FIG. 1 or the capacitor array 54 in FIG. 2 or the resistance array layer 3c with wiring in FIG. The resistance values of the plurality of resistance elements constituting the two resistance arrays 56 may all be the same. Also, if necessary for design, a plurality of capacitor elements or a plurality of resistance elements constituting the array may be divided into several groups, and each group may be set to a different capacitance value or resistance value. Good. Even when the element constants (capacitance value, resistance value, inductance, etc.) are set in this way, it is basically possible to match the designed circuit constants only by selecting the wiring pattern.

In the above embodiment, as in the third substrate layer 3 of FIG. 1, the capacitor array layer with wiring 3a and the resistor array layer with wiring 3c are formed on both sides of one insulating substrate 30.
However, it is also possible to configure these arrays on one side, depending on the desired circuit size. In this case, a resistor array, a capacitor array, and a wiring pattern thereof may be formed on the same plane, and further connected thereto. This is effective in the case of a circuit scale in which the degree of integration of the resistor array and the capacitor array is not so required, and the number of stacked layers can be reduced.

Further, in the above embodiment, the selectivity has been described based on the wiring pattern of the capacitor element or the resistance element. However, as the circuit element, the strip line 14 of the first substrate layer 1 of FIG. Naturally, a method of selecting the wiring of the inductor by the line 52 is also conceivable.

As means for forming the capacitor array or the resistor array of the above-mentioned embodiment, techniques such as lithography, vacuum deposition, and thickening of a wiring layer or the like by plating are commonly used in the IC field. In addition, printing technology is used in hybrid IC technology.

In the present embodiment, the chip height can be configured in the order of the film thickness as compared with the component mounting using the chip components as in the conventional device shown in FIG. Can be finished.

Further, since the wiring accuracy at the mask level and the dimensional accuracy of the capacitor and the resistor are improved, characteristics closer to the design values can be obtained and the size can be reduced. In addition, since the process can have a configuration similar to that of an IC, it is suitable for mass production and can be easily dealt with by a minor change such as replacement of only a wiring mask.

As described above, according to the present invention, in the high-frequency module, thinning, miniaturization, reduction of equipment, and development time can be easily realized.

Next, with respect to the third substrate layer 3 of the above-described embodiment, after a structure having general versatility that can be preliminarily formed and a wiring pattern being changed to form a desired specific circuit, The two embodiments will be described with reference to FIGS.

(Embodiment 1) First, as Embodiment 1, the concept of the present invention is applied, and a capacitor array 31 and capacitor wiring patterns 32a,
The structure in which the resistor array 32b is formed and the resistor array 34 and the resistor wiring pattern 35 are formed on the lower surface of the insulating substrate will be described with reference to FIGS.

FIG. 3 shows a structure which can be preliminarily formed before forming a specific circuit of this embodiment. In this state, a TaO ₂ thin film 31 a serving as a dielectric film of the capacitor array 31 is formed on the upper surface of the insulating substrate 30.
Of the wiring patterns 32a and 32b formed so as to sandwich the O ₂ thin film 31a in the direction perpendicular to the drawing, only the lower wiring pattern 32a is formed. Also, the insulating substrate 3
0, a resistance film 34a constituting the resistance array 34
Only are formed.

For such a structure prepared in advance,
On the upper surface of the insulating substrate 30, a wiring pattern 32 b corresponding to a target circuit is formed from the upper surface of the TaO ₂ thin film 31 a to the via hole 36.
By forming a wiring pattern 35 corresponding to a target circuit on the lower surface of the substrate at positions sandwiching the resistance film 34a from both sides in the horizontal direction, the structure shown in FIG. 4 can be obtained.

The structure shown in FIG. 4 shows only a very small part of the circuit to be formed. Actually, a large number of such circuits are arranged vertically and horizontally, for example, having a sectional structure as shown in FIG. A circuit is formed.

(Embodiment 2) Next, as Embodiment 2, the concept of the present invention is applied, and the capacitor array 31 and the capacitor wiring pattern 32 are formed on the upper surface of the insulating substrate 30.
a and 32b and a structure in which both the resistor array 34 and the resistor wiring pattern 35 are formed on the lower surface of the insulating substrate will be described with reference to FIGS.

FIG. 6 shows a structure which can be preliminarily formed before forming a specific circuit of this embodiment. In this state, a TaO ₂ thin film 31 a serving as a dielectric film of the capacitor array 31 is formed on the upper surface of the insulating substrate 30.
Wiring patterns 32a and 32b are formed only above and in the vicinity of the TaO ₂ thin film 31a so as to sandwich the O ₂ thin film 31a in the direction perpendicular to the drawing. Further, in the present embodiment, a resistance film 34a constituting the resistance array 34,
And each resistive film 3 sandwiching it from both sides in the horizontal direction.
The wiring pattern 35 formed only in the vicinity of 4a is also formed on the upper surface of the insulating substrate. Further, conductive films 37 are also formed on the inner peripheral surface of the via hole provided through the insulating substrate 30 and on the upper and lower surfaces of the insulating substrate in the vicinity thereof.

For such a structure prepared in advance,
On the upper surface of the insulating substrate 30, the wiring patterns 32a, 3
2b, 35, and 37, a wiring pattern 38 corresponding to a target circuit so as to electrically connect specific wirings.
Is formed, the structure shown in FIG. 7 can be obtained.

The above embodiment is merely an embodied example of the present invention, and the present invention includes various modes in which the configurations described in the claims are modified within an equivalent scope. .

[0057]

According to the present invention, the passive elements configured as an array form an array of elements having predetermined circuit constant values that are predetermined regardless of the specific application to which the high-frequency module is applied. However, a circuit constant required for a desired application can be obtained by a combination of these elements by changing only the wiring pattern. Since such a high-frequency module can be applied to a wide range of applications, it can be designed as a standard high-frequency module that can respond to various requests. As a result, a large reduction in manufacturing cost is realized, which leads to mass production. In addition, only the wiring pattern of each array layer needs to be changed in addition to the circuit design to make the design change, so that the development time is shortened and the development cost is reduced.

[Brief description of the drawings]

FIG. 1 is a fragmentary cross-sectional view showing a schematic structure of a high-frequency module according to an embodiment of the present invention.

FIG. 2 is a schematic perspective view conceptually showing the high-frequency module according to the embodiment of the present invention.

FIGS. 3A and 3B are views showing a structure which can be preliminarily formed before forming a specific circuit of Example 1, in which FIG. 3A is a plan view, FIG. 3B is a cross-sectional view taken along the line IIIB-IIIB, (C) has shown the bottom view, respectively.

4A and 4B are diagrams showing a structure after a specific circuit of Example 1 is formed, wherein FIG. 4A is a plan view, FIG. 4B is a cross-sectional view taken along line IVB-IVB, and FIG. Each is shown.

FIG. 5 is a circuit diagram of the first embodiment shown in FIG.
It is sectional drawing which shows the structure at the time of column arrangement.

FIGS. 6A and 6B are diagrams showing two types of structures that can be preliminarily formed before forming a specific circuit of Example 2. FIGS.

FIG. 7A is a plan layout diagram showing a structure after a specific circuit of Example 2 is formed, and FIG. 7B is an equivalent circuit diagram thereof.

FIG. 8 is a perspective view of a main part showing a schematic structure of a conventional high-frequency module.

[Explanation of symbols]

3a capacitor array layer with wiring (first passive element array layer with wiring), 3b connection layer, 3c resistor array layer with wiring (second passive element array layer with wiring), 11 active electronic components, 14 strip line, 31 capacitor element (First passive element), 32a, 32b Capacitor wiring pattern layer (first passive element wiring pattern), 34
Resistance element (second passive element), 35 Resistance element wiring pattern layer (second passive element wiring pattern).

──────────────────────────────────────────────────の Continuation of the front page (51) Int.Cl. ⁷ identification code FI H01P 3/08 H01G 4/40 301A H05K 1/02 (58) Field surveyed (Int.Cl. ⁷ , DB name) H05K 1 / 16 H05K 1/02 H01L 25/00 H01G 4/40 H01C 17/22 H01P 3/08

Claims (8)

(57) [Claims] A first passive element including a plurality of first passive elements formed in an array and a first passive element wiring pattern for electrically connecting the plurality of first passive elements;
A second passive element with wiring, including a passive element array layer, a plurality of second passive elements formed in an array, and a second passive element wiring pattern for electrically connecting the plurality of second passive elements; An element array layer, wherein the plurality of first passive elements and the plurality of second passive elements are mutually interconnected in any combination by changing the first and second passive element wiring patterns. , A high-frequency module capable of obtaining a desired circuit constant. 2. The method according to claim 1, wherein the first passive element is any one of a resistance element, a capacitor element, and an inductor element, and the second passive element is any one of a resistance element, a capacitor element, and an inductor element. Item 7. The high-frequency module according to Item 1. 3. The wiring-provided first passive element array layer,
The wiring-attached second passive element array layer is formed on different surfaces from each other, and the connection for electrically connecting the first passive element wiring pattern and the second passive element wiring pattern is formed by the wiring-attached second wiring. The high-frequency module according to claim 1, wherein the high-frequency module is interposed between one passive element array layer and the second passive element array layer with wiring. 4. The first passive element array layer with wiring,
The wiring-attached second passive element array layer is formed on each of the front and back surfaces of a single substrate, and the electrical connection between the first passive element wiring pattern and the second passive element wiring pattern is performed by the substrate. 4. The high-frequency module according to claim 3, wherein the high-frequency module is formed by a conductive layer formed in a through hole provided through the substrate. 5. The first passive element array layer with wiring,
The wiring-attached second passive element array layer is formed on the same surface, and the connection for electrically connecting the first passive element wiring pattern and the second passive element wiring pattern is formed by the first wiring-attached first wiring pattern. The high-frequency module according to claim 1, wherein the high-frequency module is interposed so as to connect a passive element array layer and the second passive element array layer with wiring. 6. The high-frequency module according to claim 2, wherein at least one of a stripline and an active electronic component is arranged on at least one of upper and lower sides of the first passive element array layer with wiring. 7. The high-frequency module according to claim 2, wherein the total number of at least one of the plurality of first passive elements and the plurality of second passive elements has the same resistance value, capacitance value, or inductance value. . 8. At least one of the plurality of first passive elements and the plurality of second passive elements forms a plurality of groups, and in each of the plurality of groups, the total number of constituent passive elements is the same. 3. The high-frequency module according to claim 2, having a resistance value, a capacitance value, or an inductance value.