JPH07111429A - Gain control amplifier - Google Patents

Abstract

PURPOSE:To attain the gain control characteristic with excellent linearity so as not to use an area of deteriorated linearity when a gain of a differential amplifier is minimum or maximum. CONSTITUTION:A contrast control voltage by a variable voltage source VCONT is changed in a range of 0-5V by the control of a control system. The control voltage is inputted to an amplifier AMP via a terminal Tv and an input level is adjusted to a range of aV-bV by DC shift and a predetermined attenuation and the adjusted level is inputted to a base of transistor(TR) Q1. With the minimum input level set to aV, a current I1 is generated to the collector by a transistor differential pair comprising TRs Q11, Q12 to cancel the current I1 flowing to the collector to flow it to the collector of the (TR) Q1. Thus, an area in the vicinity of a minimum gain among areas with deteriorated linearity in the differential amplifier comprising TRs Q1, Q2 is not used and a gain control characteristic with excellent linearity is obtained.

Description

Detailed Description of the Invention

[0001]

The present invention relates to a CRT (Cathode Ray T
It is related to the gain control amplifier applied to the drive circuit of displays such as ube).

[0002]

2. Description of the Related Art In order to extend the frequency characteristic to a wide band by using ICs of R (red), G (green) and B (blue) video gain control amplifiers, as shown in FIG.
This can be realized by configuring the G and B3 channels by IC1 to IC3 of one channel and one package, respectively. As a result, crosstalk between R, G, and B is reduced, and all R, G, and B can be designed on the same board pattern when mounting on a board, so that the frequency characteristics of three channels can be made uniform. This is possible and is also advantageous for improving frequency characteristics.

However, in order to obtain the same gain control curve for all R, G, and B in different ICs, in the semiconductor process,
This is almost impossible due to variations in the current amplification factor h _FE of resistors and transistors. In fact, if nothing is done, as shown in FIG. 15, all the R, G, and B channels show a variable gain control characteristic, but as shown in FIG. 16, all the gains for the minimum control voltage are 3 channels. If there is a matching IC, the system configuration shown in FIG.
It is possible to obtain the same gain control characteristics for the R, G, and B channels.

In the system shown in FIG. 14, the contrast control voltage can be changed by changing the user gain control resistance value by the user volume VR, and the respective gains of R, G and B can be changed by the variable resistance R. _It can be adjusted with _A , R _B , and R _C. Specifically, the control voltage is set so that the gain is almost the maximum, and then the gains of R, G, and B are matched by the respective volumes of the variable resistors R _A , R _B , and R _C , so that As shown in, the gain control curve has good linearity characteristics over the entire three channels.

FIG. 18 shows a conventional gain control amplifier.
FIG. 3 is a circuit diagram showing a configuration example of a group. In FIG. 18, Q
₁~ Q_FourIs an npn transistor, I_e01~ I_e03Is electric
Source, D₁~ D₂Is a diode, V_B1, V_B2Is a constant voltage
Source, V_CONTIs a variable voltage source, R _INIs the resistance value R_INVInput
Anti-element, R_LIs the resistance value R_LVEach of the load resistance elements
Shows.

This gain control amplifier is composed of a so-called Gilbert amplifier circuit, and each element is connected as follows. That is, the transistor Q _1
Has a base connected to the variable voltage source V _CONT , an emitter connected to the current source I _e01 , and a collector connected to the cathode of the diode D ₁ . The base of the transistor Q ₂ is connected to the midpoint of connection between the variable voltage source V _CONT and the constant voltage source V _B1 , the emitter is connected to the current source I _e02 , and the collector is connected to the cathode of the diode D ₂ . The anodes of the diodes D ₁ and D ₂ are connected to the constant voltage source V _B2 .

Transistor Q₃The base of is a transistor
Q₁Collector and diode D₁Connecting with the cathode of
Connected to a point and the emitter is a transistor Q_FourThe emitter of
Connected to the collector of the constant voltage source V_B2Connected to
It Also, the transistor Q₃And Q_FourThe emitters of
The middle point of the connection is the current source I_eo3It is connected to the. Transi
Star Q_FourIs the base of transistor Q₂Collector and die
Aether D₂Connected to the cathode of the
Resistance element R_LConstant voltage source V via _B2Connected to
It

In such a configuration, the variable voltage source V
_When the control voltage set to a level in the range of 0 to 5 V is supplied to the base of the transistor Q ₁ by _CONT , and the voltage of the predetermined level by the constant voltage source V _B1 is supplied to the base of the transistor Q ₂ , the transistor is turned on. Q ₁
A current (I ₀ + ΔI ₀ ) appears on the collector side of the transistor and a current (I ₀ −ΔI ₀ ) appears on the collector side of the transistor Q ₂ .

A signal corresponding to the current difference appearing on the collector side of the transistors Q ₁ and Q ₂ is supplied to the bases of the transistors Q ₃ and Q _{4 in} the output stage, _whereby the current value of the current source I _e03 is changed. If the 2I _1, appears current (I ₁ -ΔI ₁₎ on the collector side of the transistor Q _3, the collector of the transistor Q ₄ are current (I ₁ + Δ
I ₁ ) appears. Then, from this circuit, a signal V _{OUT that} is (I ₁ + ΔI ₁ ) · R _LV (resistance value of the load resistance element _RL ) is output from the collector side of the transistor Q ₄ .

[0010]

However, if the above-mentioned conventional gain control amplifier is used in the circuit of FIG. 14 to match the three channels at the minimum gain,
Since the re of the transistors Q ₁ and Q ₂ changes the control voltage, the linearity deteriorates at the maximum and minimum gains, as shown in FIG. FIG. 19
14B is an enlarged view of the region near the minimum gain shown in FIG. 14A. As described above, normally, the control voltage value at the minimum gain causes a potential difference between R ′ and G ′. There is a large error in absorbing the variation in the luminous efficiency of R, G, and B of the CRT by using the system of 1), and there is an influence that the color changes depending on the change of the gain control by the user.

Further, in order to keep the control voltage value at the minimum gain constant, (R _INV I
_Since it is necessary to make the value of ( ₀ ) constant (even with the temperature characteristic), high accuracy is required for the value of the power supply voltage and the bandgap voltage, and there is a problem that the management becomes complicated.

A circuit for improving these is shown in FIG.
As shown in 0, the difference between the base of the transistor Q ₁ and the variable voltage source V _CONT is made up of the transistors Q ₅ and Q ₆ connected to the current mirror circuit having the pnp type transistors P ₁ and P ₂ on the collector side. Transistors Q ₇ and Q are connected to a current mirror circuit having pnp type transistors P ₃ and P ₄ on the collector side between the base of the transistor Q ₂ and the constant voltage source V _B1 while connecting an amplifier having a dynamic pair. It has been proposed to connect an amplifier having a differential pair of _eight . However, in this circuit, in the vicinity of the maximum and minimum gains, the amplifier composed of the transistors Q ₁ , Q ₅ , and Q ₆ and the transistor Q
The loop system of the amplifier composed of ₂ , Q ₇ , and Q ₈ is disengaged due to the cutoff of the transistors Q ₁ and Q ₂ , so that there is a drawback that it oscillates.

The present invention has been made in view of the above circumstances, and an object thereof is to improve linearity in the vicinity of minimum and maximum gains, and to use three 1-channel, 1-package ICs of RGB amplifiers to disperse each IC. , A gain control amplifier capable of absorbing variations due to light emission efficiency of a CRT and simplifying RGB drive adjustment.

[0014]

To achieve the above object, in the present invention, a signal input stage constituted by a transistor differential pair and a differential output for amplifying and outputting a differential output of the signal input stage. A gain control amplifier in which a signal adjusted to a level between a first level and a second level higher than the first level is input to the base of one of the transistors of the signal input stage. A current supply circuit that supplies a current having the same value as the current to one output of the signal input stage so as to cancel the current flowing to the one output when the signal of the first level is input .

In the present invention, a current having the same value as the current is supplied to the other output of the signal input stage so as to cancel the current flowing to the other output when the signal of the second level is input. A current supply circuit for

[0016]

According to the present invention, the signal adjusted to the level between the first level and the second level is input to the base of one transistor of the signal input stage. One of the differential outputs of the signal input stage has a first input signal with the minimum input signal level.
At the level of, a predetermined current I ₁ flows. A current that cancels the current I ₁ is constantly supplied to the _one output from the current supply circuit. As a result, it is possible to prevent the use of the region with poor linearity at the minimum gain of the differential amplifier in the signal input stage, and to obtain the gain control characteristic with good linearity.

Further, according to the present invention, a predetermined current I ₂ flows to the other output of the differential outputs of the signal input stage when the input signal level is the maximum second level. And
A current that cancels the current I ₂ is constantly supplied to the other output from the current supply circuit. As a result, it is possible to avoid using the region with poor linearity at the minimum gain and the maximum gain of the differential amplifier in the signal input stage, and to obtain the gain control characteristic with good linearity.

[0018]

[Embodiment 1] FIG. 1 is a circuit diagram showing a first embodiment of a gain control amplifier according to the present invention, and the same components as those in FIG. That is, Q _{1 to} Q ₄ , Q ₁₁ and Q ₁₂ are npn transistors, I _{e01 to} I _e03 are current sources, I _M11 and I _M12 are current sources for current mirror circuits, D _{1 and} D ₂ are diodes, and V.
_B11 ~V _B14 is a constant voltage source, V _CONT is a variable voltage source, R _IN1
Is an input resistance element having a resistance value R _INV1 , R _IN2 is a resistance value R _INV2
Input resistance element, a load resistor element R _L1 is the resistance value R _LV1, R _L1 is the load resistance element of the resistance value R _LV1, AMP is the amplifier, V _CC is the power supply voltage, T _V is the contrast control voltage input terminal Are shown respectively.

A connection relationship different from that in FIG. 18 in the configuration of FIG. 1 will be described below. The base of the transistor Q ₁ is connected to the output of the amplifier AMP, and the input of the amplifier AMP is connected to the contrast control voltage input terminal T _V. An external variable voltage source V _CONT for contrast control voltage is connected to the terminal T _V. The emitter of the transistor Q _{1 and} the emitter of the transistor Q ₂ are connected via the resistance element R _{IN 1} .
A current source I _e01 is connected to the midpoint of connection between the emitter of the transistor Q ₂ and the resistance element R _IN1 . The amplifier AMP has 0 V at the minimum gain and 5 V at the maximum gain.
V, and by applying a DC shift and an attenuation action to a control voltage set to a predetermined voltage value between 0V and 5V, 0V to 5V is set to ab [V] so that the transistor Q ₁ Let the base type. The load resistance elements R _L1 and R _L2 are connected between the collectors of the transistors Q ₄ and Q ₃ and the power supply voltage V _CC , respectively.

Transistor Q₁₁The base of is a transistor
Q₂Is connected to the base of the
_B11It is connected to the. Transistor Q₁₁The emitter of
Resistance element R_IN2Through transistor Q₁₂To the emitter of
Connected, collector has power supply voltage V_CCIt is connected to the.
Also, the transistor Q₁₁Emitter and resistance element R_IN2When
Current source I to the connection midpoint of_e02Are connected. To
Langista Q₁₂Is the constant voltage source V_B13Connected to the
The collector is the current source I for the current mirror circuit._M11Connected to
Has been. Current source I for current mirror circuit_{M1 2}Is tran
Dista Q₁Collector and diode D₁With the cathode of
It is connected to the connection midpoint. Also, the current mirror circuit
Current source I_M11, I_M12Is a constant voltage source V _B14Connected to
There is.

In the present circuit having such a configuration, the input to the base of the transistor Q ₁ is aV which is at the minimum level.
In this case, a current I ₁ flows through the collector of the transistor Q ₁ . When the input to the base of the transistor Q ₁ is bV which is the maximum level, the transistor Q ₂
A current of I ₂ flows through the collector of. The set voltage of the constant voltage sources V _B11 and V _B13 is the same as when the difference aV, which is the minimum level of the base of the transistor Q ₁ , is input, and the collector of the transistor Q ₁₂ is always I It is configured so that a current of ₁ flows.

Next, the basic operation of the main part having the above configuration will be described.
This will be described with reference to FIGS. The contrast control voltage by the variable voltage source V _CONT is changed to a value according to the command in the range of 0V to 5V by the output of the control system (not shown). This control voltage is input to the amplifier AMP via the terminal T _V. In the amplifier AMP part, the input control voltage is subjected to the DC shift and the predetermined attenuation action, and the input level 0V to 5V is changed to a as shown in FIG.
It is adjusted to V to bV and input to the base of the transistor Q ₁ .

At this time, when the control voltage is 0V,
Langista Q₁When aV is supplied to the base of
Dista Q₁I's collector₁Current flows. Well
Transistor Q₁₁And Q₁₂In the differential pair of
As shown in FIG. 3, the transistor Q is always₁₂Collector of
Current IC_Q12As a constant current I₁Is flowing and this
Transistor Q₁₂Collector current I₁Is the current mirror
Current source I forming a circuit_M11And I_M12Input through
Stage transistor Q₁₁Collector and diode D₁Mosquito
It is poured into the midpoint of connection with the sword. This allows you to type
Diode D in the stage₁And D₂Current flowing through
I_D1, I _D2Are "0" and "I₀-I₁"
It Also, when the control voltage is 5V, the transistor Q
₁When bV is supplied to the base of the
Iodo D₁And D₂The current flowing through₀−
I₁, "0".

FIG. 3 is a diagram showing the relationship between the control voltage and the current I _Q1 flowing through the input stage transistor Q ₁ .
As shown in FIG. 3, the current flowing through the diode D ₁ I _D1 is the collector current I _Q1 of the transistor Q of the transistor Q ₁
Becomes the difference between the collector current I _Q12 of _12, when the control voltage is 0V, the current I _D1 flowing in the diode D ₁ as described above becomes "0".

Further, FIG. 4 shows a control voltage and a diode.
Mode D₁And D₂Current I flowing through _D1And I_D2Relationship with
FIG. As can be seen from FIG. 4, the circuit of FIG.
When the control voltage is near 0V, diode D₁and
D₂Current I flowing through_D1And I_D2The characteristics of
I'm good. Looking at the output signal, the current characteristics are output as is
As shown in FIG. 5, the circuit of FIG.
Gain output characteristic with good linearity
A control curve can be obtained.

As described above, according to this embodiment,
The collector of the transistor to Q ₁ input stage, I flowing in the collector of the transistor Q ₁ when the minimum input level aV
_{In order} to cancel the current of _{1, the} current of I ₁ is always generated by the transistor differential pair composed of the transistors Q ₁₁ and Q _12, and the current is fed to the collector of the transistor Q ₁ .
As shown in FIG. 2, regions P1 and P2 having poor linearity of the differential amplifier composed of the transistors Q ₁ and Q _{2 are used.}
Since the area P1 in the vicinity of the minimum gain is not used, a gain control characteristic with good linearity can be obtained. As shown in FIG. 5, the linearity of this circuit at the maximum gain is as bad as that of the conventional circuit.
There is no restriction that the value of (R _INV · I ₀ ) should be a constant value, and the linearity at the minimum gain is improved.

Also, by applying this circuit to the system of FIG. 14, the R, G, B gain control characteristics can be made uniform. As a result, R, G, B each 1
The channel 1 package can be integrated into an IC, and the frequency characteristics can be extended compared to the 3 channel 1 package.
There are advantages such as reducing crosstalk.

FIG. 6 is a circuit diagram showing an example of an application circuit of the circuit of FIG. In this circuit, the base input stage of the transistor Q ₁ of the circuit of FIG. 1, the voltage source V _B11 and the current source I
_A current mirror circuit composed of _M11 and I _M12 is shown as a specific element, and between the cathode of the diode D ₁ and the collector of the transistor Q ₁ and between the cathode of the diode D ₂ and the transistor Q in the differential amplifier of the input stage. Diodes D ₃ and D between the collector of ₂ and
₄ is inserted from the cathode side of the diodes D ₁ and D _{2 in} the forward direction, and further provided with a limiter for preventing the collector voltage of the transistor Q ₁ from becoming higher than a certain voltage (E ₁ −V _BE ). There is.

Base of transistor Q ₁ and amplifier AMP
Between the current source I _e13 for supplying the current I ₁ connected in series between the power supply voltage V _CC and the ground, the pnp type transistors P ₁₁ and P _12, and also between the amplifier AMP and the ground. The resistance elements R ₁₁ and R ₁₂ connected in series are connected in parallel. Specifically, the midpoint of connection between the current source I _e13 and the emitter of the transistor P ₁₁ is the transistor Q ₁
Of the transistor P ₁₁ is connected to the base and the emitter of the transistor P ₁₂ . The collector of the transistor P ₁₂ is grounded, and the base is connected to the connection midpoint between the resistance elements R ₁₁ and R ₁₂ . With such a configuration, the amplifier AMP is connected via the terminal T _V.
The input control voltage input to is subjected to the DC shift and the predetermined attenuation action, and the input level 0V to 5V is
It is adjusted to aV to bV and input to the base of the transistor Q ₁ .

The voltage source V _B11 includes a current source I _e14 for supplying a current I ₁ connected in series between the power source voltage V _CC and ground, pnp type transistors P ₁₃ and P _14, and a resistance element R _13. It is configured. Then, the current source I _e14
A connection point between the emitter of the transistor P ₁₃ is connected to the base of the transistor Q _2, Q ₁₁ and Q _12, the collector of the transistor P ₁₃ is the base and the transistor P ₁₄
Connected to the emitter. The collector of the transistor P ₁₄ is grounded, and the base is grounded via the resistance element R ₁₃ . Such a configuration for supplying a predetermined voltage to the base of the transistor Q _2, Q ₁₁ and Q _12.

The current mirror circuit is composed of pnp type transistors P _{M11 to} P _M14 . The emitters of the transistors P _M11 and P _M13 have a power supply voltage V _CC.
And the bases of both are connected. The collector of the transistor P _M11 is the base and the transistor P is
_It is connected to the emitter of _M12 , and the collector of the transistor P _M12 is connected to the midpoint of connection between the collector of the transistor Q ₁ and the cathode of the diode D ₃ . The collector of the transistor P _M13 is connected to the emitter of the transistor P _M14 . The base of the transistor P _M14 is connected to the collector and the base of the transistor P _M12 ,
The midpoint of the connection between the base and the collector is connected to the collector of the transistor Q ₁₂ . With such a configuration, the current I ₁ that appears in the collector of the transistor Q ₁₂ flows into the collector of the transistor Q ₁ via the current mirror circuit.

The reason why the diodes D ₃ and D ₄ , especially D ₃ are provided on the collector side of the differential amplifier of the input stage is that the collector current IC _Q1 of the transistor Q ₁ and the transistor P of the current mirror circuit when the control voltage is 0V. Ideally, it should be the same as the collector current IC _{PM12 of M12} , but they do not necessarily match due to variations in the elements. Therefore,
When the collector current IC _PM12 of the transistor P _M12 is larger than the collector current IC _Q1 of the transistor Q ₁ , the diode D ₃ is prevented from flowing into the diode D _1.
Has been inserted. For the diode D _4, the same reason.

The limiter is composed of an npn type transistor Q _E1 and a constant voltage source V _E1 of the supply voltage E ₁ . Specifically, the base of the transistor Q _E1 is connected to the constant voltage source V _E1 , the collector is connected to the power supply voltage V _CC ,
The emitter is grounded. With this configuration,
As described above, the collector voltage of the transistor Q ₁ is controlled so as not to be higher than a certain voltage (E ₁ −V _BE ).

In the circuit of FIG. 6 also, the gain control characteristic with good linearity can be obtained without using the region near the minimum gain.

[0035]

Second Embodiment FIG. 7 is a gain control according to the present invention.
It is a circuit diagram which shows the 2nd Example of an amplifier. In this example
Is the transistor Q which is the feature of the first embodiment described above.₁
If the input to the base of
Register Q₁I flowing to the collector ₁The same value as the current
Current of the transistor Q₁Pour into the collector of
Therefore, the gain control characteristic
In addition to the configuration that improves nearness, transistor Q₂
If the input to the base of the
Register Q₂I flowing to the collector₂The same value as the current
Current of the transistor Q₂Pour into the collector of
Therefore, the gain control characteristic
A structure is provided to improve nearness. concrete
The current I₂Transistor Q for generating₁₃And
And Q₁₄And a differential pair consisting of
Star Q₂Current mirror times to pour into collector
Current source I as a path_M21And I_M22Is provided.

The base of the transistor Q ₁₃ is a constant voltage source V
_It is connected to _B11 , the emitter is connected to the emitter of the transistor Q ₁₄ via the resistance element R _IN3 , and the collector is connected to the current source I _{M2 1} . A current source I _e04 is connected to the midpoint of connection between the emitter of the transistor Q ₁₃ and the resistance element R _IN3 . The base of the transistor Q ₁₄ is connected to the constant voltage source V _B15 , and the collector is connected to the power supply voltage V _CC . In addition, the current source I for the current mirror circuit
_M21 and I _M22 are connected to the constant voltage source V _B14 .

In such a configuration, the constant voltage source V _B11
The difference between the set voltages of V _B15 and V _B15 is that transistor Q ₁
This is the same as when the maximum level bV of the base is input, and the current I ₂ is always flown to the collector of the transistor Q ₁₃ .

Next, the basic operation of the main part having the above configuration will be described.
This will be described with reference to FIGS. Since the operation at the minimum gain is the same as that of the first embodiment, the description here will be focused on the maximum gain. The contrast control voltage by the variable voltage source V _CONT is changed to a value according to the command in the range of 0V to 5V by the output of the control system (not shown). This control voltage is input to the amplifier AMP via the terminal T _V. In the amplifier AMP portion, the input control voltage is subjected to the DC shift and the predetermined attenuation action, and the input level 0V to 5V changes to aV as shown in FIG.
Adjusted to ~ bV and input to the base of the transistor Q ₁ .

At this time, when the control voltage is 0V,
Langista Q₁When aV is supplied to the base of
Dista Q₁I's collector₁Current flows. Well
Also, the control voltage is 5V, the transistor Q₁The
When bV is supplied to the source, the transistor Q₂Collect
I have₂Current flows. Transistor Q₁₃and
Q₁₄In the differential pair of, as shown in FIG.
Langista Q₁₃Collector current IC_Q13As a constant power
Flow I₂Is flowing, this transistor Q₁₃Collector of
Current I₂Is a current source I that constitutes a current mirror circuit_M21
And I_M22Through the input stage transistor Q₂This
And diode D₂Pour into the middle point of connection with the cathode of
Get caught As a result, as shown in FIG.
Voltage is 0V, transistor Q₁AV is used for the base of
Diode D in the input stage when supplied₁And D
₂Current I flowing through_D1, I_D2Are "0" and "I₀
-(I₁＋ I₂) ” In addition, the control voltage
Transistor Q at 5V₁BV was supplied to the base of
If the diode D in the input stage₁And D₂Flow to
The current is₀-(I₁＋ I₂) ”And“ 0 ”.

FIG. 9 is a diagram showing the relationship between the control voltage and the current flowing in the transistor Q _{2 of the} input stage. As shown in FIG. 9, when the input voltage is bV, the diode D ₂
The electric current flowing through is 0.

FIG. 10 is a diagram showing the relationship between the control voltage and the currents I _D1 and I _D2 flowing in the diodes D ₁ and D ₂ . As can be seen from FIG. 10, in the circuit of FIG. 7, the characteristics of the currents I _D1 and I _D2 flowing through the diodes D ₁ and D ₂ have good linearity when the control voltage is near 0 V and 5 V. Looking at the output signal, the current characteristics appear as they are, so the circuit of FIG.
An output amplitude characteristic as shown in FIG. 11 can be obtained, and a gain control curve with good linearity can be obtained at the minimum and maximum gains.

As described above, according to this embodiment,
Input stage transistor Q₁To the collector of the minimum input level
Transistor Q at aV₁I flowing to the collector
₁Transistor Q to cancel the current₁₁and
Q₁₂A transistor differential pair consisting of I₁Become the current
Generate the transistor Q₁When poured into the collector of
In both cases, when the maximum input level is bV, the transistor Q₂
I flowing to the collector ₂To cancel the current
Langista Q₁₃And Q₁₄Transistor differential pair consisting of
Always I₂To produce a current₂of
Pour it into the collector and use a transistor as shown in Figure 8.
Q₁And Q₂Linearity of differential amplifier consisting of
Since the unused areas P1 and P2 are not used,
In addition to the effect of Example 1, gay with better linearity
Control characteristics can be obtained.

Further, by applying this circuit to the system of FIG. 14, the gain control characteristics of R, G and B can be made uniform. As a result, R, G, B each 1
The channel 1 package can be integrated into an IC, and the frequency characteristics can be extended compared to the 3 channel 1 package.
There are advantages such as reducing crosstalk.

Further, in order to change the currents I ₁ and I ₂ to change the part of the differential amplifier having a good linearity and the part having a wide dynamic range, the resistance element R _IN , the current I ₀ by the current source I _e0 and the constant voltage source are used. This is possible by changing the voltage value E _A of V _B11 .

FIG. 12 shows a first application circuit example of the circuit of FIG.
It is a circuit diagram showing. This circuit is similar to the circuit in Figure 1.
The part has the same configuration as the circuit of FIG.
In addition, the transistor Q of the circuit of FIG.₁₂And Q₁₄The ba
Input source voltage source V_B13And V_B15, Current source I
_M21And I_M22The current mirror circuit consisting of
, And the die in the input stage differential amplifier.
Aether D ₁Cathode and transistor Q₁With the collector of
Between and diode D₂Cathode and transistor
Q₂Diode D between collector and₃, D
_FourThe diode D₁And D₂Forward from the cathode side of
Insert it so that it is facing the direction₁and
Q₂The collector voltage of a certain voltage (E₁+ V_BE) Higher than
A limiter is provided to prevent it from getting worn out.

The voltage source V _B13 includes a current source I _e15 for supplying a current I ₁ connected in series between the power source voltage V _CC and ground, a resistance element R ₁₄ , pnp type transistors P ₁₇ and P ₁₈ , and It is composed of a resistance element R ₁₅ . The midpoint of connection between the current source I _e14 and the resistance element R ₁₄ is connected to the base of Q ₁₂ , the emitter of the transistor P ₁₇ is connected to the resistance element R ₁₄ , and the collector is connected to the base and the emitter of the transistor P _18. Has been done. Transistor P
The collector of ₁₈ is grounded, and the base is grounded via a resistance element R ₁₅ . With such a configuration, a predetermined voltage is supplied to the base of the transistor Q ₁₂ .

Further, the voltage source V_B15Is the power supply voltage V_CCContact with
Current I connected in series with the ground ₁Supply current source
I_e16, Resistance element R₁₆, Pnp type transistor P₁₉And
And P ₂₀, And also connect in series between the amplifier AMP and ground.
Resistor element R connected₁₇And R₁₈But transistor Q₁₄
Bass and amplifier AMP₂Placed in parallel between and
It Specifically, the current source I_e16And resistance element R₁₆Connection with
Midpoint is Q₁₄Connected to the base of the transistor P₁₉D
Mitter is a resistance element R₁₆Connected to the transistor P ₁₉of
The collector is the base and the transistor P₂₀To the emitter of
It is connected. Transistor P₂₀The collector of is grounded
And the base is a resistive element R₁₇And R₁₈Connected to the middle point
Has been. With this configuration, the specified voltage is
Dista Q₁₄Supply to the base of.

The current mirror circuit is composed of pnp type transistors P _{M21 to} P _M24 . The emitters of the transistors P _M21 and P _M23 have a power supply voltage V _CC.
And the bases of both are connected. The collector of the transistor P _M21 is the base and the transistor P is
_It is connected to the emitter of _M22 , and the collector of the transistor P _M22 is connected to the midpoint of connection between the collector of the transistor Q ₂ and the cathode of the diode D ₄ . The collector of the transistor P _M23 is connected to the emitter of the transistor P _M24 . The base of the transistor P _M24 is connected to the base and collector of the transistor P _M22 ,
The midpoint of connection between the base and the collector is connected to the collector of the transistor Q ₁₃ . With such a configuration, the current I ₂ that appears in the collector of the transistor Q ₁₃ flows into the collector of the transistor Q ₂ via the current mirror circuit.

The reason why the diodes D ₃ and D ₄ are provided and the limiter is provided on the collector side of the differential amplifier of the input stage is that the control voltage is 0 V as described above.
At this time, the collector current IC _Q1 , of the transistors Q ₁ and Q ₂ ,
IC _Q2 and current mirror circuit transistors P _M12 , P
Ideally, the collector currents IC _PM12 and IC _{PM22 of M12} should be the same, but they do not necessarily match due to variations in the elements. For example, when the collector current IC _PM12 is large, the collector potential of the transistor Q ₁ rises until the transistor P _M12 becomes saturated. Therefore, the transistor P _M12 ,
Diodes D ₃ and D ₄ are inserted so that the current does not flow into the diodes D ₁ and D ₂ when the collector currents IC _PM12 and IC _{PM22 of} P _M12 are larger than the collector currents of the transistors Q ₁ and Q _2. At the same time, a limiter is provided so that the collector potentials of the transistors Q ₁ and Q ₂ do not exceed a certain potential (E ₁ + V _BE ).

The limiter is composed of pnp type transistors P ₁₅ and P ₁₆ and a constant voltage source V _E1 of the supply voltage E ₁ . Specifically, the bases of the transistors P ₁₅ and P ₁₆ are connected to the constant voltage source V _E1 , the emitter of the transistor P ₁₅ is connected to the collector of the transistor Q ₂ , and the emitter of the transistor P _{16 is} the collector of the transistor Q ₁ . The collectors of both transistors P ₁₅ and P ₁₆ are connected and grounded. With such a configuration, as described above, the collector voltages of the transistors Q ₁ and Q ₂ are controlled so as not to be higher than a certain voltage (E ₁ + V _BE ).

Also in the circuit of FIG. 12, gain control characteristics with good linearity can be obtained without using the regions near the minimum and maximum gains.

FIG. 13 is a circuit diagram showing a second application circuit example of the circuit of FIG. That this circuit differs from the circuit of Figure 12, npn-type limiter transistor Q _15, Q _16, diode D ₁₁ to D ₁₄ and the current source I _e05, lies in the structure by I _e06. Specifically, the transistor Q ₁₅ ,
The base of Q ₁₆ is connected to the constant voltage source V _B12 , and the collector is connected to the power supply voltage V _CC . The emitter of the transistor Q ₁₅ is connected to the anode of the diode D _12, a cathode of the diode D ₁₂ is connected to the cathode and the current source I _e05 of the diode D _11, the anode of the diode D ₁₁ is connected to the collector of the transistor Q ₁ There is. Also,
The emitter of the transistor Q ₁₆ is connected to the anode of the diode D _14, the cathode of the diode D ₁₄ is connected to the cathode and the current source I _e05 of the diode D _13, the anode of the diode D ₁₃ is connected to the collector of the transistor Q ₃ There is. Other configurations are similar to those of the circuit of FIG. 12, and the same actions and effects as those of the circuit of FIG. 12 can be obtained.

[0053]

As described above, according to the present invention,
It is possible to avoid using the region of poor linearity at the minimum and maximum gains of the differential amplifier, and obtain gain control characteristics with good linearity.

Also, by applying this circuit to a system in which R, G, and B 3 channels are each configured by 1 channel 1 package, the R, G, B gain control characteristics can be made uniform. As a result, R, G, B
Each 1-channel 1-package can be integrated into an IC, the frequency characteristics can be extended and cross-talk can be reduced as compared with the 3-channel 1-package.

[Brief description of drawings]

FIG. 1 is a first gain control amplifier according to the present invention.
3 is a circuit diagram showing an embodiment of FIG.

2 is a diagram showing the relationship between the base voltage and the collector current of the transistor to Q ₁ circuit of FIG.

3 is a diagram showing the relationship between the collector current of the control voltage and the transistor to Q ₁ circuit of FIG.

FIG. 4 is a control voltage and a diode D of the circuit of FIG.
Is a diagram showing the relationship between the current flowing through the _first and D _2.

5 is a diagram showing an output amplitude characteristic with respect to a control voltage of the circuit of FIG.

6 is a circuit diagram showing an example of an application circuit of the circuit of FIG.

FIG. 7 is a second gain control amplifier according to the present invention.
3 is a circuit diagram showing an embodiment of FIG.

8 is a diagram showing a relationship between a base voltage and a collector current of a transistor Q _{1 in} the circuit of FIG.

9 is a diagram showing the relationship between the base voltage of the transistor Q ₁ and the collector current of the transistor Q _{2 in} the circuit of FIG.

10 is a diagram showing the relationship between the control voltage of the circuit of FIG. 7 and the currents flowing in the diodes D ₁ and D ₂ .

11 is a diagram showing an output amplitude characteristic with respect to a control voltage of the circuit of FIG.

12 is a circuit diagram showing a first application circuit example of the circuit of FIG. 7. FIG.

13 is a circuit diagram showing a second application circuit example of the circuit of FIG.

FIG. 14 is a diagram showing a system in which R, G, and B3 channels are each configured by one channel and one package.

FIG. 15 is a diagram showing a gain control characteristic when there are variations in all R, G, and B channels.

FIG. 16 is a diagram showing a gain control characteristic when the gains for the minimum control voltage are the same on all three channels.

FIG. 17 is a diagram showing the same gain control characteristic for all R, G, and B channels.

FIG. 18 is a circuit diagram showing a first conventional example.

FIG. 19 is a diagram for explaining a problem of the circuit of FIG.

FIG. 20 is a circuit diagram showing a second conventional example.

[Explanation of symbols]

_{Q 1 ~Q 4, Q 11 ~Q} 16 ... npn type transistor P ₁₁ ~P ₂₀ ... pnp type transistor _{I e01 ~I e06, I e11 ~I} e16 ... current source _{I M11, I M12, I M21} , I M22 ... current source D ₁ to D for the current mirror circuit _4, D ₁₁ ~D ₁₄ ... diodes V _B11 ~V _B15 ... constant voltage source V _CONT ... variable voltage source R _IN1 to R _IN3 ... input resistance element R _L1, R _L2 ... load Resistance elements R _{11 to} R ₁₈ ... resistance elements AMP, AMP ₁ , AMP ₂ ... amplifier V _CC ... power supply voltage T _V ... contrast control voltage input terminal

Claims (2)

[Claims] 1. A signal input stage configured by a transistor differential pair and a differential output stage for amplifying and outputting a differential output of the signal input stage, wherein one transistor of the signal input stage is provided. A gain control amplifier in which a signal adjusted to a level between a first level and a second level higher than the first level is input to a base, wherein one output of the signal input stage is: A gain control amplifier comprising a current supply circuit for supplying a current having the same value as the current so as to cancel the current flowing through the one output when the signal of the first level is input. 2. The other output of the signal input stage,
2. The gain control amplifier according to claim 1, further comprising a current supply circuit that supplies a current having the same value as the current so as to cancel the current flowing through the other output when the signal of the second level is input.