JPH0137884B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a gain control circuit configured using a differential amplifier and a current mirror circuit.

A gain control circuit has the function of arbitrarily changing the ratio of the magnitude of an output signal to an input signal, and when implementing such a gain control circuit into a semiconductor integrated circuit, the circuit should be configured using a differential amplifier. is commonly practiced.

Figure 1 shows a conventional example of a gain control circuit constructed using a differential amplifier. A control signal input terminal 14 is connected to the bases of transistors 1 and 4, a control signal input terminal 15 is connected to the bases of transistors 2 and 3, and the collectors of transistors 1 and 3 are connected to each other. is directly connected to the power supply 20, and the collectors of transistors 2 and 4 are connected to the load resistor 1.
6 to the power supply 20. Gain control signals are applied to the control signal input terminals 14 and 15 in opposite phases. transistors 2 and 4
An output signal is further supplied from the collector to the base of the emitter follower transistor 17, and an output signal from the emitter resistor 18 is supplied to the output terminal 19.
It has been taken out. constant current source transistor 5,
Emitter resistors 7 and 8 are connected to 6, respectively.
A base bias voltage is applied to the base from a base bias power supply 11 via resistors 9 and 10. An input signal is supplied from an input terminal 12 via a coupling capacitor 13.

The circuit operation of gain control in FIG. 1 will be explained below.

Since the input signal applied to the input terminal 12 is applied to the base of the transistor 5 via the coupling capacitor 13, the collector current of the transistor 5 becomes a current containing the signal current and flows to the emitters of the differentially connected transistors 1 and 2. . transistors 1 and 2
A DC voltage is applied to the base of the transistor from the control signal input terminals 14 and 15, and by differentially changing this DC voltage, the ratio of the collector current of the transistor 5 to the transistors 1 and 2 changes. do. The collector current of the transistor 2 controlled in this way flows to the load resistor 16 and is sent to the output terminal 19 via the emitter follower transistor 17.
is extracted as an output signal. The emitter current of differentially connected transistors 3 and 4 is
The distribution ratio of this current is also determined by the DC voltage applied between the control signal input terminals 14 and 15, similar to the differential connection transistors 1 and 2 described above. controlled. The collector currents of transistors 2 and 4 flow through the load resistor 16, but they increase and decrease in opposite directions. Therefore, if the collector bias currents of transistors 5 and 6 are set equal, the potential across the load resistor will change. The drop is kept constant, and the DC operating point of the output terminal 19 does not vary even when the gain is controlled by the DC voltage applied to the control signal input terminals 14 and 15. Therefore, the base bias resistors 9 and 10 and the emitter resistors 7 and 8 are usually set to the same resistance value.

In the conventional gain control circuit shown in Fig. 1, in order to keep the DC operating point constant, a current source for current compensation and differential transistors (transistors 3, 4, 6 and resistor 8, in Fig. 1) are used. 10) is required, and when controlling the gain of multiple input signals at the same time, for example when there are two input signals whose gain should be controlled in parallel, one gain control circuit is required for each input signal. As the number of elements increases,
This results in an increase in current consumption, which is undesirable especially in semiconductor integrated circuits.

An object of the present invention is to eliminate such inconveniences, and to provide gain control that reduces the number of elements and current consumption by sharing the current source for current compensation and the differential transistor when controlling the gain of multiple input signals at the same time. The purpose is to obtain the circuit.

The gain control circuit according to the present invention includes first and second transistors connected in a differential manner, third and fourth transistors connected in a differential manner, fifth and sixth transistors connected in a differential manner. a transistor, first and second signal input terminals to which first and second input signals are respectively supplied, and a direct current coupled to the emitter junction of the first and second transistors and the first signal input terminal. means for supplying a signal current corresponding to the first input signal together with a bias current to the emitter coupling point; a direct current bias current coupled to the emitter coupling points of the third and fourth transistors and substantially the same as the direct current bias current; means for supplying a DC bias current substantially the same as the DC bias current to the emitter connection of the fifth and sixth transistors and to the second signal input terminal; means for supplying a signal current according to the signal to the emitter coupling point; a first transistor commonly connected to the bases of the first, fourth and fifth transistors;
a second gain control terminal commonly connected to the bases of the second, third and sixth transistors; means for supplying a gain control voltage between the first and second gain control terminals; a current input terminal connected to the collector of the third transistor; and first and second current output terminals connected to the collectors of the second and sixth transistors, respectively; the ratio of the output current to the input current; is substantially set to 1, first and second signal output terminals connected to the collectors of the second and sixth transistors, respectively;
a DC voltage source, and the DC voltage source and the first
and a first and second load respectively connected between the signal output terminal and the second signal output terminal.

Next, the present invention will be explained in more detail with reference to the drawings.

FIG. 2 is a circuit diagram showing the operating principle of the present invention.

The same parts as in FIG. 1 are designated by the same reference numerals. The difference from FIG. 1 is that the load resistor 16 is connected to a DC voltage source 21 that provides the output operating point, and that a current mirror consisting of PNP transistors 22 and 23 is connected between the collectors of transistors 2 and 3. The circuit 24 is connected. As is well known, in the current mirror circuit 24, a current equal to the emitter current of the diode-connected transistor 23 flows as the emitter current of the transistor 22. In FIG. Therefore, the current flows out as the collector current of the transistor 22. Therefore, the load resistance 16
The difference between the collector current of transistor 2 and the collector current of transistor 22 flows,
When both collector currents are equal, that is, when no input signal is applied, the difference current is zero and the transistor 17
The voltage of the DC voltage source 21 is applied to the base of the output voltage source 21, and this becomes the output operating point. Transistors 2 and 3 have the same rate of change in collector current due to gain control using the DC voltage applied to terminals 14 and 15, so the output operating point remains constant in any state of gain control, and the gain A controlled output signal is obtained at the load resistor 16, and the circuit operates substantially the same as the conventional example shown in FIG.

FIG. 3 is a circuit diagram showing an embodiment of the present invention. Portions corresponding to those in FIG. 2 are indicated by the same reference numerals. 25 and 26 are differentially connected transistors corresponding to transistors 1 and 2, 27 is a current source transistor, 28 is an emitter resistor, 29 is a base bias resistor, 30 is one input terminal for the input terminal 12, and 31 is a coupling capacitor. and are connected in parallel to the control terminals 14 and 15 and the base bias voltage source 11, respectively. The DC bias currents flowing through transistors 5, 6 and 27 are substantially the same. The collector of transistor 26 is PNP
The collector of transistor 32 is connected, but the base of transistor 32 is connected to transistor 2.
Current mirror circuit 2 connected to the base of 3
It forms the same current mirror circuit as 4. That is, transistors 22, 32 and 3
2 constitutes a current mirror circuit in which the collector of transistor 23 is a current input terminal and the collectors of transistors 22 and 32 are first and second current output terminals, respectively, and the ratio of output current to input current is substantially 1. is set to . A load resistor 33, an emitter follower formed by a transistor 34 and a resistor 35 are connected to the collector of the transistor 26, and a gain-controlled output signal is taken out to an output terminal 36 as in FIG.
Load resistor 33 and load resistor 16 are connected to DC voltage source 21 . In this embodiment, the input signals applied to input terminals 12 and 30 are
The gain is simultaneously controlled by the control voltages applied to terminals 4 and 15, and output signals are taken out to output terminals 19 and 36, respectively. It can be seen that the connecting transistor and the diode-connected transistor 23 forming the current mirror circuit can be used in common for the two gain control circuits.

That is, the first gain control terminal 14 is commonly connected to the bases of the first, fourth and fifth transistors 1, 4 and 25, and the second gain control terminal 15 is connected to the bases of the second, third and sixth transistors. It is commonly connected to the bases of transistors 2, 3 and 26, and a current mirror circuit (transistors 22, 23, 3
The current input terminal (collector of 23) of 2) is connected to the collector of the third transistor 3, and the first and second current output terminals (collectors of 22, 32) are connected to the collectors of the second and sixth transistors 2, 26. and the outputs for the first and second input signals are connected to the second and sixth transistors 2, 26, respectively.
By connecting the loads 16 and 33 between each output and the DC voltage source 21, the potential of the second gain control terminal 15 is lower than that of the first gain control terminal 14. When becomes high (low), the collector currents of the second, third, and sixth transistors 2, 3, and 26 all become large (small), and the current mirror circuits 22, 23, and 3
2, the increase (decrease) in the collector current of the second and sixth transistors 2 and 26 is
This is compensated for by the increase (decrease) in the collector current of the transistor 3, and no DC current flows through the loads 16 and 33, and the output DC voltage does not change. load 16,
33, the DC voltage at each output terminal is determined by the DC voltage source 21, and therefore the resistance values of the loads 16 and 33 can be arbitrarily set to obtain the desired AC gain. can do. Furthermore, first and second gain control terminals 14, 15
Since the collector currents of the second and sixth transistors 2 and 26 change in the same direction in response to changes in the gain control voltage between them, the gains for both input signals can be set in the same direction. Moreover, although gain control is performed for two input signals, the required configuration is three pairs of differential transistors 1, 2: 3, 4: 25, 26) and one current mirror. Circuits 23, 22, 32, and DC bias current and input signal current supply circuit 5-1
1,27-29, which reduces the number of elements and reduces power consumption.

This is a significant reduction in the number of circuit elements and current consumption compared to the conventional circuit shown in Fig. 1, which would require two sets of the circuit shown in Fig. 1 to perform the same operation. Naturally, the more input signals there are to control, the more effective it is.

The gain control circuit according to the present invention can be applied to a plurality of signal level control circuits, such as volume control of stereo audio signals and color density adjustment of color televisions. Further, the basic effects of the present invention do not change even if the present invention is used as a mixing circuit that takes out a combined output of two signals by adding another input signal to the current source for current compensation described above. Second
It is clear that the circuit operation is basically the same even if the NPN transistors are replaced with PNP transistors and the PNP transistors are replaced with NPN transistors in FIGS.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram showing a conventional example of a gain control circuit.
Figure 2 is a circuit diagram showing the operating principle of the present invention;
The figure is a circuit diagram showing one embodiment of the present invention. 1, 2, 3, 4, 25, 26... differential connection transistor, 5, 6, 27... current source transistor,
7, 8, 28... Emitter resistance, 9, 10, 29...
Base bias resistor, 11... Base bias power supply, 12, 30... Input terminal, 13, 31... Coupling capacitor, 14, 15... Control terminal, 16, 33...
Load resistance, 17, 34... Emitter follower transistor, 18, 35... Emitter follower resistor, 19,
36... Output terminal, 20... Collector bias voltage source, 21... Bias voltage source providing an output operating point,
22, 23... PNP transistor for current mirror, 24... current mirror circuit.

Claims (1)

[Claims] 1 first and second transistors connected in a differential manner; third and fourth transistors connected in a differential manner;
a fifth and a sixth transistor connected in a differential manner, first and second signal input terminals to which the first and second input signals are respectively supplied; means coupled to an emitter coupling point and the first signal input terminal for supplying a signal current corresponding to the first input signal together with a DC bias current to the emitter coupling point; means coupled to the emitter coupling point of the fifth and sixth transistors and means coupled to the emitter coupling point of the fifth and sixth transistors and means coupled to the second signal input terminal for supplying a DC bias current substantially the same as the DC bias current to the emitter coupling point; means for supplying a signal current corresponding to the second input signal to the emitter coupling point together with a direct current bias current substantially the same as a direct current bias current, commonly connected to the bases of the first, fourth and fifth transistors; a first gain control terminal, a second gain control terminal commonly connected to the bases of the second, third and sixth transistors, and supplying a gain control voltage between the first and second gain control terminals; means, having a current input terminal connected to the collector of the third transistor, and first and second current output terminals respectively connected to the collectors of the second and sixth transistors; a current mirror circuit with a ratio of substantially 1; first and second signal output terminals connected to the collectors of the second and sixth transistors, respectively; a DC voltage source; A gain control circuit comprising first and second loads respectively connected between the first and second signal output terminals.