JPS6161726B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention provides an automatic gain control system that extracts the output from any collector terminal of an amplifier connected in a bi-differential format and applies a gain control voltage to the base of the bi-differential amplifier to perform gain control. Regarding control circuits.

FIG. 1 is a circuit diagram showing an example of a conventional automatic gain control circuit. In an amplifier including a transistor 1 having a terminal a as an input terminal and a terminal c as an output terminal, differential amplification transistors 3,
The voltage applied across the base of transistor 1 is varied, thus controlling the ratio of the signal input voltage applied to the base of transistor 1 to the signal output voltage developed across load resistor R15, and thus the voltage gain of the amplifier. Here, the output signal taken out from terminal c is transmitted to any amplifier 1.
When the input signal voltage applied to the input terminal a is amplified by the rectifier circuit 200 and then converted to a DC signal by the rectifier circuit 200 and applied to the g terminal of the automatic gain control circuit shown in FIG. By designing the voltage amplifier and rectifier circuit after terminal c so that the DC signal voltage applied to the terminal also increases.
AGC circuits can be designed. A feature of the conventional automatic gain control circuit is that a change in the control voltage applied to the terminal g is applied to the bases of the differential amplifier transistors 3 and 4 as a change in the voltage drop across the resistor R19 from the terminals d and e, which are set to a predetermined bias voltage. , load resistance R
The purpose of this is to change the bias current flowing through 15 to control the gain. Note that in the example of FIG. 1, the bias of terminal e is normally selected to be higher than the bias of terminal d, and when no control voltage is applied to terminal g, transistor 4
is the cutoff and the operating point is set at the maximum gain.

Now, the problems of the conventional automatic gain control circuit shown in FIG. 1 will be described. First, it is susceptible to the influence of noise contained in the control voltage, and the internal noise generated from the gain control circuit is also large, making it difficult to obtain a good signal-to-noise ratio (S/N) at the output terminal c. That is, the internal noise generated at the gain control terminal g and the external noise applied to the terminal g are caused by the mutual conductance of the transistor 9 and the resistance R1.
It is amplified by a factor of 9, is generated at the base input terminals of differential amplifier transistors 3 and 4, and is further amplified by a resistor R19.
It is added to the noise generated in , and is output as noise to output terminal c. Therefore, the signal-to-noise ratio at the input terminal a is deteriorated by the above-mentioned noise.

Second, it is difficult to arbitrarily set the loop gain of the automatic gain control circuit (AGC) and the control voltage at which gain control begins. That is, the input control signal level at which gain control begins is determined by the point at which the collector current of transistor 9 begins to flow and the resistor R19, and to reduce this level, it is sufficient to set the resistor R18 small or the resistor R19 large. , this setting also increases the ratio of resistor R18 and resistor R19, increasing the AGC loop gain in this part. Therefore, when the gain control circuit shown in Fig. 1 is used in various automatic gain control circuits, the input signal level (proportional to the input control voltage) at which automatic gain control starts is required.
AGC loop gain cannot be designed arbitrarily.

The conventional automatic gain control circuit shown in FIG. 1 suffers from the problems described above, which are also related. That is, the first problem can be solved by lowering the gain of the automatic gain control circuit mentioned in the second
Although this can be improved to some extent, on the other hand, this imposes restrictions on the setting of the input signal level at which automatic gain control (AGC) begins to apply, and it is extremely difficult to achieve both.

Furthermore, in the configuration shown in FIG. 1, the third problem is that the distribution ratio of the DC bias current between the transistors 3 and 4 changes depending on the gain control voltage applied to the terminal g. This will result in a change in voltage. DC coupling with the next circuit is thus impossible.

The present invention provides an automatic gain control circuit that solves the above-mentioned first, second, and third problems all at once.

Next, the present invention will be explained in more detail with reference to the drawings.

An embodiment of an automatic gain control circuit according to the present invention is shown in FIG. In FIG. 2, transistors 1,
3, 4 and resistors 11, 15 correspond to transistors 1, 3, 4 and resistors 11, 15 in FIG.
Further, terminals a, b, c, f, k in FIG. 2 correspond to a, b, c, f, k in FIG. transistor 1
0 is added differentially with transistor 9,
The loads of these transistors 9 and 10 are connected to transistors 7 and 8 whose bases are supplied with a constant voltage through terminals d, and furthermore, the emitter voltage of these transistors 7 and 8 is applied to the bases of transistors 3 and 4. has been added. Furthermore, this circuit includes transistors 5 and 6 connected in a differential manner, transistor 2 serving as a bias current source for these transistors, and resistors 12 and 14, which are connected as shown.

The feature of this embodiment circuit shown in FIG. 2 is that the output obtained at terminal c is applied to base terminals g or h of transistors 9 and 10 via a suitable amplifier 100 and rectifier circuit 200, The change in is detected as a change in the difference in the base-emitter voltage of the emitter follower transistors 7 and 8 with reference to the terminal d set to a predetermined bias voltage, and through the transistors 3 and 4 of the differential amplifier,
The gain is controlled by changing the signal current flowing through the load resistor R15, and the voltage between the bases of the transistors 5 and 6 is also controlled to keep the DC bias at the output terminal c constant. At this time, a constant bias voltage is applied to the terminal g or h to which no gain control voltage is applied and the terminal f, but these are omitted in the figure.

The advantages of the automatic gain control circuit according to the present invention shown in FIG. 2 will now be described. First, the signal-to-noise ratio (S/N) characteristics are significantly improved compared to the conventional automatic gain control circuit shown in FIG. That is, in FIG. 2, transistors 3 and 4
The base terminal of is connected to emitter follower transistors 7 and 8 whose bases are connected to a reference voltage application terminal d (grounded in AC terms).
The noise generated here is the noise caused by the relatively large (several KΩ) resistor R19 in the conventional circuit shown in FIG. 1, whereas the emitter resistance (collector current is 26Ω when the current is 1mA), so for example, it is several hundredths of the conventional value.
Can be done significantly.

Second, the automatic gain control circuit according to the present invention is
This has the advantage that the AGC loop gain and the control voltage at which gain control starts can be set arbitrarily. That is, the input signal voltage value at which gain control begins can be easily changed without changing the AGC loop gain by arbitrarily setting the bias voltage of the comparison voltage terminal h or g in FIG. can.

Third, the automatic gain control circuit according to the present invention makes it easier to compensate for temperature and suppress variations in the input signal voltage value at which gain control begins, compared to conventional automatic gain control circuits. First, the above-mentioned temperature compensation can be achieved by equalizing the temperature changes of the control voltages applied to terminals g and h in FIG. That is, the second
In the automatic gain control circuit shown in the figure, transistor 9
and 10, transistors 7 and 8, transistors 3 and 4, and transistors 5 and 6 are each configured in a differential format, so if the temperature characteristics of each transistor are made uniform, the control applied to terminals g and h The operation of the automatic gain control circuit is temperature compensated for voltage. Here, in order to make the temperature characteristics of each transistor uniform, it can be relatively easily achieved by configuring the circuit of the present invention on a semiconductor integrated circuit in which these transistors are formed on the same semiconductor chip. However, by this means, variations in the characteristics of each element can be reduced, and therefore variations in the input signal voltage at which gain control begins can be reduced. Further, by changing the emitter area ratio of transistors 9 and 10 and transistors 7 and 8, the gain control characteristics can be freely set.

Fourth, even if the DC bias current of transistor 3 increases or decreases due to the control voltage from terminal g (or h), transistor 5
acts, so the DC voltage at terminal c does not fluctuate.

As described above, by using the gain control circuit according to the present invention, an automatic gain control (AGC) circuit having various excellent characteristics can be easily designed.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram showing a conventional automatic gain control circuit, and FIG. 2 is a circuit diagram showing an embodiment of the present invention. 1 to 10 and 17...transistor, 11 to
15, 18, 19...Resistor, a...Signal input terminal, b...Power supply voltage supply terminal, c...Signal output terminal, d, e, f...DC bias terminal, g, h...
...gain control voltage application terminal, K...ground terminal.

Claims (1)

[Claims] 1 first and second transistors connected in a differential manner and having an input signal supplied to their emitter connection; and third and fourth transistors connected in a differential manner and having a bias current supplied to their emitter connection. , fifth and sixth transistors whose respective bases are biased at a constant voltage, seventh and eighth transistors which are differentially connected and have a gain control signal supplied between their bases, and the first and sixth transistors. 3
means for commonly connecting the bases of the transistors, the emitters of the fifth transistors and the collectors of the seventh transistors, the bases of the second and fourth transistors, the emitters of the sixth transistors and the eighth means for commonly connecting the collectors of the transistors; means for commonly connecting the collectors of the first and fourth transistors; means for commonly connecting the collectors of the second and third transistors; and means for extracting an output signal from the collector of at least one of the transistors.