JP3363001B2 - Differential amplifier circuit and image processing device - Google Patents

Description

Detailed Description of the Invention

[0001]

[Table of Contents] The present invention will be described in the following order. TECHNICAL FIELD OF THE INVENTION Conventional technology (Figs. 3-5) Problems to be Solved by the Invention (FIG. 6) Means for Solving the Problems (FIG. 1) Embodiment of the invention (FIGS. 1 and 2) The invention's effect

[0002]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a differential amplifier circuit and an image processing device, and can be applied to, for example, a device for varying the gain of a video signal sent to a computer display device using a cathode ray tube.

[0003]

2. Description of the Related Art Conventionally, in a display device for a computer using a cathode ray tube, even if image signals of three primary colors of red, green and blue are given in the same size, the respective images on the display surface will be affected by manufacturing errors. The signal brightness is uneven. Therefore, it is necessary to relatively adjust the sizes of the video signals of the three primary colors to achieve white balance on the display surface. The overall brightness of the display surface is adjusted according to the usage conditions such as the brightness of the installation location. At this time, for example, by using three gain adjusting / amplifying circuits 1 shown in FIG. 3, the magnitudes of the video signals of the three primary colors are adjusted relatively and entirely by one gain variable amplifying stage 1A, respectively.
It suppressed the deterioration of power consumption and frequency characteristics.

The gain adjusting / amplifying circuit 1 inputs one image signal S1 of the three primary color image signals to the variable gain amplifying stage 1A, and divides the shunt ratio K ₁ set in the main adjusting stage 1B and the sub adjusting stage 1C. According to the product of the set diversion ratio K ₂ , the gain is gradually reduced from the maximum value and the amplified video signal S2 is output. The variable gain amplifying stage 1A is entirely driven by constant current sources 2 and 3 which flow a constant current I ₀ , respectively. The video signal S1 is input from the signal source V _IN through the resistor R _IN to the power supply voltage V _CC side of the constant current source 3. The video signal S2 is taken out at the voltage V ₁ from the other end of the resistor R _L1 whose one end is connected to the power supply voltage V _CC .

Assuming that the current flowing through the resistor R _IN by the video signal S1 is ΔI ₀ , the overall gain G of the variable gain amplifying stage 1A.
_T1 is

[Equation 1] It is represented by. The gain G _AC1 of only the AC component is

[Equation 2] It is represented by.

As shown in FIG. 4, the main adjusting stage 1B is
As the main control voltage V _CONT1 applied to the transistor Q1 increases from 0 [V] to 5 [V], the diversion ratio K ₁ is linearly increased from 0 to 1. As shown in FIG. 5, the sub adjusting stage 1C does not make the diversion ratio K ₂ zero as the sub control voltage V _CONT2 applied to the transistor Q3 increases from 0 [V] to 5 [V], for example. Increase linearly from 1 to 1.

Thus, the gain G according to the equation (2) is obtained.
_When the shunt ratio K ₂ is K ₂ = 1, the total gain G _T1 of _AC1 is linear from 0 to 1 as the main control voltage V _CONT1 increases from 0 [V] to 5 [V], for example. Increase to. Further, the gain G _AC1 has a main control voltage V _CONT1 of, for example, 0 [V] to 5 when the diversion ratio K ₂ is K ₂ = α.
As it increases to [V], the total gain G _T1 changes from 0 to α
R> increases linearly.

[0008]

By the way, in the variable gain amplifier stage 1A described above, the transistor Q is connected by the constant current source 3.
6 drives the differential pair of transistors Q9 and Q10, and the transistor Q10 drives the differential pair of transistors Q13 and Q14. Differential pair transistor 1
3 and 14 constitute a Gilbert amplifier circuit together with the main adjusting stage 1B. Transistors Q13 and Q14
And transistors Q15 and Q16 of the main control stage 1B
When the emission area and emission current of and are the same,
The diversion ratio β set in the transistor Q14 and the diversion ratio K
₁ is the following equation,

[Equation 3] It becomes a relationship.

However, in the above-described gain adjustment amplifier circuit 1, the sub-control voltage V _CONT2 is narrowed down so that the shunt ratio K ₂ is 0.
, The collector current of the transistor Q10 decreases. The Gilbert amplifier circuit in this state operates in a portion having low linearity, and therefore the expression (3) does not hold. That is, as shown in FIG. 6, as the shunt ratio K ₂ is reduced to K ₂ = α by narrowing down the sub control voltage V _CONT2 , the characteristic curve of the gain G _AC1 of only the AC component with respect to the main control voltage V _CONT1 . There was a problem that the linearity of was decreased. Therefore, the linearity of the amplitude of the video signal S2 with respect to the main control voltage V _CONT1 decreases.

The present invention has been made in consideration of the above points, and a differential amplifier circuit and image processing capable of improving the linearity of the gain characteristic when one of the two control inputs for simultaneously controlling the gain is narrowed down. It is intended to propose a device.

[0011]

In order to solve the above problems, according to the present invention, a first differential pair operates differentially with first and second transistors and with first and second transistors. The first preamplifier sets the first shunt ratio to the first and second transistors and the second shunt ratio to the third transistor. The second differential pair includes fourth and fifth transistors, and the first preamplifier sets the first shunt ratio to the fourth transistor and the second shunt ratio to the fifth transistor. To do. The third differential pair includes sixth and seventh transistors, and the second preamplifier sets the third diversion ratio to the sixth transistor and the fourth diversion ratio to the seventh transistor. Then, it is driven by the third transistor. The fourth differential pair is composed of eighth and ninth transistors, and the second preamplifier sets the third diversion ratio to the eighth transistor and the fourth diversion ratio to the ninth transistor. Then, it is driven by the second and fifth transistors. The input signal is applied to the common emitter side of the second differential pair, and the output signal is output from the common collectors of the first, sixth and ninth transistors.

A collector current of a fifth transistor for inputting an input signal to the emitter side and setting a second shunt ratio;
The fourth differential pair is driven by the first transistor and the collector current of the second transistor which is set to the first shunt ratio and differentially operates with the third transistor to drive the fourth differential pair and the third transistor. Of controlling the gain by extracting an output signal from the common collector of the sixth transistor which is driven by the transistor of No. 4 and the third shunt ratio is set, and the ninth transistor of which the fourth shunt ratio is set. It is possible to further improve the linearity of the gain characteristic when the second control input for controlling the first and second differential pairs of the first and second control inputs is narrowed down.

Further, according to the present invention, the first and second transistors and the third transistor which operates differentially with the first and second transistors are provided, and the first preamplifier provides the first shunt ratio with the first shunt ratio. 1st and 2nd transistors, and a 1st differential pair which sets 2nd shunt ratio to a 3rd transistor, and a 4th and 5th transistor,
The first preamplifier sets the first shunt ratio to the fourth transistor and the second differential pair to the second shunt ratio to the fifth transistor, and the sixth and seventh transistors. , A second preamplifier sets the third shunt ratio to the sixth transistor, and the fourth shunt ratio to the seventh transistor to form a third differential pair driven by the third transistor. , An eighth and a ninth transistor,
A fourth differential driven by the second preamplifier with the third shunt ratio set to the eighth transistor, the fourth shunt ratio set to the ninth transistor, and driven by the second and fifth transistors. And the input image signal is applied to the common emitter side of the second differential pair to output the output image signal as the first and sixth signals.
And a differential amplifier circuit for outputting from the common collector of the ninth transistor.

[0014]

BEST MODE FOR CARRYING OUT THE INVENTION An embodiment of the present invention will be described in detail below with reference to the drawings.

FIG. 1 in which parts corresponding to those in FIG. 3 are assigned the same reference numerals shows a gain adjusting amplifier circuit 10 for adjusting the magnitude of a video signal supplied to a computer display device using a cathode ray tube as a whole. It is used for each of the three primary color video signals to adjust the magnitude of the three primary color video signals relatively and globally. The gain adjustment amplifier circuit 10 inputs one input signal of the video signals of the three primary colors, for example, the video signal S1 to a differential amplifier circuit, for example, the variable gain amplification stage 10A, and outputs the second signal.
Of the preamplifier, for example, the shunt ratio K ₁ set in the main adjusting stage 1B and the first preamplifier, for example, the shunt ratio K ₂ set in the sub adjusting stage 1C, the gain is gradually reduced from the maximum value and amplified. The output signal, for example, the video signal S2 is output.

The gain adjustment amplifier circuit 10 is provided with a variable gain amplification stage 10A in place of the variable gain amplification stage 1A in the configuration of the gain adjustment amplifier circuit 1, and the sub control voltage V
The linearity of the characteristic curve of the gain G _AC2 of the AC component when _CONT2 is narrowed down is improved. The variable gain amplification stage 10A is replaced with the one transistor Q7 of one differential pair of transistors Q7 and Q8 driven by the constant current source 2 and controlled by the sub adjustment stage 1C in the configuration of the variable gain amplification stage 1A. , First
Transistor, for example, transistor Q19 is provided.

Further, the variable gain amplifying stage 10A is provided with a third transistor such as a transistor Q8 and a tenth transistor such as a transistor Q20 having a collector and an emitter connected in common. As a result, the transistors Q8 and Q20 commonly drive the sixth and seventh transistors of the differential pair, for example, the transistors Q11 and Q12, by their collector currents. Further, the variable gain amplification stage 10A has a common collector with the fourth and fifth transistors of the other differential pair driven by the constant current source 3 and controlled by the sub adjustment stage 1C, for example, one transistor Q10 of the transistors Q9 and Q10. And a second transistor, for example, a transistor Q21, which is connected to the transistor Q8 and the emitter is commonly connected. As a result, the transistors Q10 and Q21 commonly drive the eighth and ninth transistors of the differential pair, for example, the transistors Q13 and Q14, by their collector currents.

The transistors Q19 to Q21 have an emitter area ratio of (n-
2) It is formed in a ratio of 1: 1 and an emitter current proportional to each emitter area is passed. Transistor Q1
9, Q11 and Q14, the collector is connected to the power supply V _CC via the commonly connected resistors R _L1, and outputs a video signal S2 with a voltage V ₂ from the connection point of the collector and the resistance R _L1.

The current I ₂ flowing through the transistor Q19 is given by the following equation:

[Equation 4] Required by. Current I flowing through transistor Q20
₃ is the following equation,

[Equation 5] Required by. Current I flowing through transistor Q21
₄ is the following equation,

[Equation 6] Required by. The current I ₅ flowing through the transistor Q8 is
The following equation,

[Equation 7] Required by. Current I flowing through transistor Q11
₆ is the following equation,

[Equation 8] Required by.

On the other hand, the current I flowing through the transistor Q10
₇ is the following equation,

[Equation 9] Required by. Current I flowing through transistor Q14
₈ is the following equation,

[Equation 10] Required by.

The output voltage V ₂ generated at the common collector of the transistors Q19, Q11 and Q14 is as follows:

[Equation 11] Required by. The overall gain G _{T2 at} this time is

[Equation 12] Required by. Also, the gain G _AC2 of only the AC component is (1
From the formula 2), the following formula,

[Equation 13] Required by.

In the above configuration, n is set to 3 or more. The gain G _AC2 of the AC component (video signal S2) is (1
As shown in the formula (3), when the main control stage 1B narrows down the main control voltage V _CONT1 to bring the diversion ratio K ₁ close to 0, it can be cut down. By taking out the product of the diversion ratios K ₁ and K _{2 in} the equation (13) from the transistor Q14,
Consider the drive currents of the transistors Q13 and Q14 of the differential pair.

Transistors Q13 and Q14 are (10)
As shown in the equation, in addition to the current I ₇ that is the same as that of the conventional case due to the transistor Q10,
Driven by ₄ . The current I ₇ becomes 0 when the sub-control voltage V _CONT2 is reduced by the sub-adjustment stage 1C to reduce the shunt ratio K _2.
Close to. On the other hand, the current I ₄ increases as the sub control voltage V _CONT2 is _reduced , as shown in the equation (6).

In this way, in the transistors Q13 and Q14, the DC component of the drive current never becomes 0 even when the sub control voltage V _CONT2 is reduced. This allows the transistors Q13 and Q14 to operate in a region having high linearity. Therefore, even when the sub control voltage V _CONT2 is reduced, the linearity of the gain G _AC2 of the AC component with respect to the main control voltage V _CONT1 of the main adjustment stage 1B can be further improved. By the way, the DC potential of the output voltage V ₂ is
As shown in (11), it changes according to the diversion ratio K ₂ . This amount of change decreases as n increases.

According to the above configuration, the transistor Q for inputting the video signal S1 to the emitter side and setting the diversion ratio K ₂
10 collector current I ₇ and transistors Q19 and Q
20 and the shunt ratio (1-K ₂ ) is set to drive the differential pair of transistors Q13 and Q14 with the transistor Q8 and the collector current I ₄ of the transistor Q21 which operates differentially, and the transistors Q19, Q11 and Q14 are commonly used. By extracting the video signal S2 from the collector, the gain G
_AC2 can further improve the linearity of the gain characteristic when was Shibotsu sub control voltage V _CONT2 of the main control voltage V _CONT1 and the sub-control voltage V _CONT2 for controlling.

Further, since the gain G _AC2 can be independently controlled by the main adjusting stage 1B and the sub adjusting stage 1C, it is most suitable for an integrated circuit having a large power consumption such as a wide band amplifier circuit.

[0027] In the above embodiment, emitter area respectively n-2: 1: a transistor Q19~Q21 formed arranged in 1, (1 / n) ( 1-K 2) I 0
The current of the
Although the case of flowing from Q13 and Q14 has been described, the present invention is not limited to this, and as shown in FIG. 2, two transistors Q2 each having an emitter area of n-1: 1 are formed.
2 and Q23 disposed, (1 / n) (1 -K 2) of the differential pair of current I ₀ in the transistor Q23 transistor Q1
It can also be applied to the case of flowing from 3 and Q14. Also in this case, the same effect as described above can be obtained. Incidentally, the output voltage V ₃ in this case is

[Equation 14] Sought in. The DC potential of the output voltage V ₃ changes according to the diversion ratios K ₁ and K ₂ as shown in the equation (14).

In the above embodiment, the video signal S2 applied to the computer display device using the cathode ray tube.
However, the present invention is not limited to this and is also applicable to the case of adjusting the gain of a video signal applied to a display device other than the cathode ray tube, for example, a liquid crystal display device or a plasma display device.

[0029]

As described above, according to the present invention, the collector current of the fifth transistor for inputting the input signal to the emitter side and the second shunt ratio is set, and the first shunt current together with the first transistor. The ratio is set and the third transistor and the collector current of the second transistor that operates differentially
Driving a differential pair of the first transistor, a sixth transistor driven by the third transistor and having a third shunt ratio, and a ninth transistor having a fourth shunt ratio. Of the gain characteristic when the second control input for controlling the first and second differential pairs of the first and second control inputs for controlling the gain is narrowed by extracting the output signal from the common collector of It is possible to realize a differential amplifier circuit and an image processing device that can further improve linearity.

[Brief description of drawings]

FIG. 1 is a connection diagram showing a gain adjustment amplifier circuit according to an embodiment of a differential amplifier circuit and an image processing apparatus according to the present invention.

FIG. 2 is a connection diagram showing a gain adjustment amplifier circuit according to another embodiment.

FIG. 3 is a connection diagram showing a conventional gain adjustment amplifier circuit.

FIG. 4 is a characteristic diagram showing a characteristic of a diversion ratio set by a main control stage.

FIG. 5 is a characteristic diagram showing characteristics of a diversion ratio set by a sub-adjustment stage.

FIG. 6 is a characteristic diagram showing a gain control characteristic of a conventional AC component.

[Explanation of symbols]

1, 10, 12 ... Gain adjustment amplifier circuit, 1A, 10A:
12A: Variable gain amplification stage, 1B: Main adjustment stage, 1
C ... Sub adjustment stage, 2-5 ... Constant current source.

Claims (5)

(57) [Claims] 1. A first and a second transistor and the first transistor.
And a second transistor and a third transistor that performs a differential operation, the first preamplifier sets the first diversion ratio to the first and second transistors, and the second diversion ratio is set to the second diversion ratio. The first differential pair is set to the third transistor, the fourth and fifth transistors, and the first preamplifier sets the first diversion ratio to the fourth transistor, and the second differential pair. The second differential pair for setting the shunt ratio to the fifth transistor and the sixth and seventh transistors, and the third shunt ratio to the sixth transistor by the second preamplifier. , A fourth differential ratio is set in the seventh transistor, and the third differential pair is driven by the third transistor, and the eighth and ninth transistors. Above the third diversion ratio An eighth transistor, a fourth differential pair driven by the second and fifth transistors, the fourth diversion ratio being set to the ninth transistor, and the input signal is A differential amplifier circuit which is applied to a common emitter side of the second differential pair and outputs an output signal from a common collector of the first, sixth and ninth transistors. 2. The first differential pair includes a tenth transistor which operates differentially with the third transistor and sets the first shunt ratio by the first preamplifier, The differential amplifier circuit according to claim 1, wherein the third differential pair is driven by the third and tenth transistors. 3. The differential amplifier circuit according to claim 1, wherein the first transistor causes a collector current of the same value or more as that of the second transistor to flow. 4. The differential amplifier circuit according to claim 1, wherein the second and tenth transistors flow collector currents of the same value. 5. A first and a second transistor and the first transistor.
And a second transistor and a third transistor that performs a differential operation, the first preamplifier sets the first diversion ratio to the first and second transistors, and the second diversion ratio is set to the second diversion ratio. The first differential pair is set to the third transistor, and the fourth and fifth transistors. The first preamplifier sets the first diversion ratio to the fourth transistor and the second differential pair. The second differential pair for setting the shunt ratio of the fifth transistor to the fifth transistor and the sixth and seventh transistors, and the third shunt ratio to the sixth transistor by the second preamplifier. , A fourth differential flow ratio is set for the seventh transistor, and a third differential pair driven by the third transistor is connected to the eighth and ninth transistors.
The second preamplifier sets the third shunt ratio to the eighth transistor and the fourth shunt ratio to the ninth transistor to set the second and the second transistors. 4th driven by 5 transistors
An input image signal is applied to the common emitter side of the second differential pair, and an output image signal is output from the common collectors of the first, sixth and ninth transistors. An image processing apparatus comprising a differential amplifier circuit.