JP2970178B2 - RGB matrix circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an RGB matrix circuit, and more particularly to an RGB matrix circuit having a small variation in pedestal voltage and a stable black level.

[0002]

2. Description of the Related Art In a color receiver, R, G,
In order to match the beam characteristics of the three colors B, in an RGB matrix circuit of the IC (FIG. 5), the addition signal of the color signal and the luminance signal shown on the left side and the DC voltage shown on the right side are controlled in R, G, and B, respectively. , G, and B signals are made uniform in beam current. On the other hand, in an IC, it is desired to perform signal processing with a minimum current and use a transistor having a minimum area. To satisfy this condition, there is a circuit shown in FIG. Hereinafter, description will be given according to (FIG. 4).

The color signal VS1 and the inverted luminance signal VS2 are signals Q1 and Q2, respectively, as shown on the left side of FIG.
The DC voltage VD1 and the pedestal DC voltage equal to the color signal VS1 are input to Q3 and Q4, respectively, as shown on the right side of FIG. On the signal side, the signal voltage is converted into a signal current by a resistor R1, and on the DC side, the difference voltage between VP1 and VP2 is converted to a DC current by a resistor R2.
Converted to current. The signal current is current mirror Q11,
DC is connected to the collector of Q12 by R6, Q12 and R7.
Current flows to the collector of Q14 through current mirrors Q13, R8, Q14, R9. The currents flowing through Q12 and Q14 are divided by the differential amplifiers of Q5 and Q6 and Q7 and Q8 by control voltages VC1 and VC2, and are divided by Q5 and Q7.
And the collector current having predetermined signal components of Q6 and Q8. A signal current flows through the resistor R12 by the current mirrors Q9, R3, Q15, and R5 and the current mirrors Q16, R10, Q17, and R11, and the collector currents of Q6 and Q8 become output voltages. At this time, as shown in FIG. 5, the potential difference on the signal side is larger than that on the DC side. Therefore,
In the IC, it is better to make the transistors Q3 and Q4 smaller than Q1 and Q2 in order to use the area effectively. By doing so, Q13 and Q14 can also be reduced, which is more effective. Now, assuming that the transistor sizes of Q1 and Q2 are 3 s and the transistor sizes of Q3 and Q4 are 2 s, Q3, Q4, Q13, Q1
4, Q7 and Q8 can be reduced, and the area for 6 s can be reduced.

[0004]

However, in the above configuration, in the control portions of the control voltages VC1 and VC2, the transistors Q5, Q7 and Q6, Q8 cause the current at the time of the maximum signal current and the current at the minimum signal current due to the Early effect. The pedestal changes differently. This is shown in FIG. Since the emitters of the transistors Q1, Q2 and Q3, Q4 are different, the current characteristics are slightly different.
There is a difference between the collector currents of Q12 and Q14. Q12 collector current and Q14 collector current are IC1 and IC2, respectively.
And the emitter-collector voltages of Q6 and Q8 are V1, Q
5, the emitter-collector voltage of Q7 is V2. At this time, when the signal current is maximum, the maximum current flows to the Q6 and Q7 sides, and no current flows to the Q5 and Q8 sides. When the current at this time is obtained, the base current of Q6 is Ib1 and the base current of Q7 is Ib2 '. Conversely, when the signal current is minimum, Q6, Q7
No current flows to the side, and the maximum current flows to the Q5 and Q8 sides.
When the current at this time is obtained, the base current of Q6 is Ib1 ',
The base current of Q7 is Ib2. Control voltage V
The current flowing through C1 and VC2 is IA = I when the signal current is maximum.
b1 + Ib2 ′, and when the signal current is minimum, IB = Ib1 ′
+ Ib2. Since the values of the signal current maximum IA and the signal current minimum IB are slightly different, the output voltages are also different. If there is no luminance and chrominance signals and the pedestal voltage of VS2 is equal to VD2, a DC voltage difference of 168 mV is generated (in actual use, a signal current from 1/2 to the maximum value is used.
The voltage difference is 84 mV). This DC voltage is further subjected to DC correction by low light control, but it is necessary to secure a range capable of absorbing the DC voltage difference (here, 84 mV).

[0005] In view of the above, the present invention reduces the DC voltage difference due to the Early effect in the current control unit to a very small value.
It is an object to provide a control circuit with good accuracy.

[0006]

In order to solve the above problem, the RGB matrix circuit of the present invention reduces the output DC difference voltage due to the Early effect by applying a load also to the collector opposite to the output of the signal distribution control unit. It is very small.

[0007]

According to the present invention, the load on the low light control for correcting the DC voltage difference can be minimized by making the DC voltage difference between the maximum signal and the minimum signal extremely small. In addition, since the burden on low light control can be reduced, DAC bus control, which is often used in recent ICs, can be used.
It is possible to reduce the number of IT or loosen the accuracy.

[0008]

Embodiment (FIG. 1) shows R in the first embodiment of the present invention.
FIG. 2 shows a GB matrix circuit, and FIG. 2 shows current characteristics of transistors in a signal current control unit. Hereinafter, description will be given according to (FIG. 1) and (FIG. 2).

The chrominance signal VS1 and the inverted luminance signal VS2 are signals Q1 and Q2, respectively, as shown on the left side of FIG.
The DC voltage VD1 and the pedestal DC voltage equal to the color signal VS1 are input to Q3 and Q4, respectively, as shown on the right side of FIG. On the signal side, the signal voltage is converted into a signal current by a resistor R1, and on the DC side, the difference voltage between VP1 and VP2 is converted to a DC current by a resistor R2.
Converted to current. The signal current is current mirror Q11,
DC is connected to the collector of Q12 by R6, Q12 and R7.
Current flows to the collector of Q14 through current mirrors Q13, R8, Q14, R9. The currents flowing through Q12 and Q14 are divided by the differential amplifiers of Q5 and Q6 and Q7 and Q8 by control voltages VC1 and VC2, and are divided by Q5 and Q7.
And the collector current having predetermined signal components of Q6 and Q8. Q5, Q7 collector current is resistance R
4 and the collector currents of Q6 and Q8 flow through the resistor R12 through the current mirrors Q9, R3, Q15 and R5 and the current mirrors Q16, R10, Q17 and R11 to become output voltages. At this time, as in the embodiment, the transistor sizes of Q1 and Q2 are 3 s,
The transistor size of No. 4 is 2 s. Control voltage VC
1, the transistor Q in the control section of VC2.
The state of the current when the signal current is maximum and the signal current when the signal current is minimum due to the Early effect in Q5, Q7, Q6 and Q8 are shown in FIG.
Since the emitters of the transistors Q1, Q2 and Q3, Q4 are different, the current characteristics are slightly different.
4 has a difference in the collector current. Q12 collector current and Q14 collector current are assumed to be IC1 and IC2, respectively.
The emitter-collector voltage of Q8 is V1, and the emitter-collector voltages of Q5 and Q7 are V2. At this time, when the signal current is maximum, the maximum current flows to Q6 and Q7 sides, and Q5 and Q8
No current flows on the side. When the current at this time is obtained, the base current of Q6 is Ib1 and the base current of Q7 is Ib2 '. Conversely, when the signal current is minimum, no current flows on the Q6 and Q7 sides, and a maximum current flows on the Q5 and Q8 sides. When the current at this time is obtained, the base current of Q6 is Ib1 'and the base current of Q7 is Ib2. The currents flowing through the control voltages VC1 and VC2 are equal to those in the conventional case and the signal current is at the maximum IA '.
= Ib1 + Ib2 ′, minimum signal current IB ′ = Ib1 ′
+ Ib2. Although the values of the currents IA and IB are slightly different, the Early voltages are almost equal. Therefore, as shown in FIG. 2, Ib1 ≒ Ib1 ′, Ib2 ≒ Ib2 ′, and
The values of A 'and IB' are almost equal. As an example, when there is no luminance and chrominance signals and the pedestal voltage of VS2 is equal to VD2, the DC voltage difference is very small at 2.6 mV. (In actual use, the DC voltage difference is 1.3 mV because the signal current from 1/2 to the maximum value is used.) That is, the conventional DC difference voltage of 84 mV can be reduced to 1.3 mV.

When the brightness is changed, the DC level of Q2 changes and the current of Q12 changes, so that in the conventional circuit, the output DC level changes due to the Early effect. Accordingly, the white balance has changed due to variations in the R, G, and B characteristics of the CRT. In this embodiment, however, the white balance is very good even when the brightness is changed.

FIG. 3 shows R in another embodiment of the present invention.
2 shows a GB matrix circuit. In this case, a transistor Q10 and a resistor R4 are used as loads for Q5 and Q7. When the resistance R4 is equal to the resistance R3, Q5 and Q7
, The difference between the emitter-collector voltage V1 and the emitter-collector voltage V2 of Q6, Q8 is further reduced, and the difference between the output DC voltages is further reduced.

[0012]

As described above, according to the present invention, a load is also applied to the collector on the opposite side of the output of the signal distribution control unit, so that the output DC difference voltage due to the Early effect is extremely reduced. The load on the low light control for correcting the DC voltage difference can be reduced as much as possible by making the DC voltage difference extremely small, so that the white balance is low. Further, since the burden on low light control can be reduced, the number of BITs of the DAC can be reduced or the precision can be reduced in the bus control often used in recent ICs, so that the practical effect is very large. .

[Brief description of the drawings]

FIG. 1 is a circuit diagram of an RGB matrix according to an embodiment of the present invention.

FIG. 2 shows currents of transistors Q5, Q6, Q7 and Q8.
Voltage characteristic diagram

FIG. 3 is a circuit diagram of an rgb matrix according to another embodiment of the present invention.

FIG. 4 is a circuit diagram of a conventional RGB matrix.

FIG. 5 is a diagram showing current-voltage characteristics of transistors Q5, Q6, Q7, and Q8 in FIG.

FIG. 6 is a current-voltage characteristic diagram of transistors Q5, Q6, Q7, and Q8 in FIG.

[Explanation of symbols]

Q1, Q2, Q11, Q12, Q5, Q6 Emitter size 3s transistor Q3, Q4, Q13, Q14, Q7, Q8 Emitter size 2s transistor R4 Load resistance Q10 Load diode

Claims (5)

(57) [Claims] A first transistor for inputting a base of a color signal and a second transistor for inputting a base of an inverted luminance signal; a first resistor between an emitter of the first transistor and an emitter of the second transistor; A first transistor having a base input of the same DC voltage as a signal, a third transistor having a different emitter area, a fourth transistor having a base input of a DC voltage near a pedestal, an emitter of the third transistor, and an emitter of the fourth transistor A first differential amplifier comprising a second resistor between the first and second transistors, a fifth transistor for base-inputting a first control voltage for shunting a collector current of the first transistor, and a sixth transistor for base-inputting a second control voltage. , The third
A second differential amplifier comprising a seventh transistor for base-inputting a second control voltage for shunting a collector current of the transistor and an eighth transistor for base-inputting the first control voltage; and the fifth and seventh transistors The ninth transistor and the third resistor are connected between the collector and the ground, and the current is output by a current mirror. The fourth transistor is connected between the common and the collector of the sixth and eighth transistors. An RGB matrix circuit having a resistance to control a magnitude of an addition signal of a color signal and a luminance signal while keeping a DC output voltage constant. 2. The method according to claim 1, wherein when the first control voltage is equal to the second control voltage, the sum of the base-emitter voltage of the ninth transistor and the voltage across the third resistor is equal to the voltage value across the fourth resistor. The RGB matrix circuit according to claim 1, wherein 3. An emitter area of a second transistor and a fourth transistor
3. The RGB matrix circuit according to claim 1, wherein the transistors have different emitter areas. 4. The transistor according to claim 1, wherein the emitter areas of the first and second transistors are larger than the emitter areas of the third and fourth transistors.
An RGB matrix circuit according to claim 3. 5. The RGB matrix circuit according to claim 1, further comprising a tenth transistor in series with a fourth resistor, wherein the fourth resistor and the third resistor are equal.