JPH09162721A - Current switching type logic circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To operate the logic circuit under a low power supply voltage by avoiding a process error and effect of an operating temperature. SOLUTION: A base of a 1st differential transistor(TR) Q5 is connected to an emitter of a 1st emitter follower TR Q3 via a 1st emitter resistor R11 , a base of a 2nd differential transistor(TR) Q6 is connected to an emitter of a 2nd emitter follower TR Q4 via a 2nd emitter resistor R12 , and a 2nd constant current source 11 supplying an emitter current to the 1st and 2nd emitter follower TRs Q3 , Q4 is configured by a current mirror circuit. Furthermore, the resistance of the 1st emitter resistor R11 and the 2nd emitter resistor R12 is selected nearly twice the resistance of a load resistor of a reference current side TR Q10 of the current mirror circuit. A base-emitter voltage of the TR of the current mirror circuit cancels the base-emitter voltage of the 1st or 2nd emitter follower TR Q3 or Q4 and the base-emitter voltage of the 1st or 2nd differential TR Q5 or Q5 .

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a current switching type logic circuit (so-called CML; Current Mode Logic), and more particularly to a current switching type logic circuit capable of obtaining stable operation even at a low power supply voltage.

[0002]

2. Description of the Related Art In a switching circuit using a saturation operation transistor, the base current (steady base current) flowing through the transistor in the ON state reaches several times the minimum base current required to saturate the transistor. Not a few things. This results in extra charge being stored in the base region of the transistor, which requires a delay time at turn-off to recombine this charge (or remove it as a reverse base current) before the collector current is cut off. become. This time is the accumulation time, and shortening this time is an important key for increasing the speed of the saturation logic circuit. However, it is impossible to completely eliminate the accumulation time, and in this sense, the logic circuit using the saturation operation transistor has a limit in operation speed.

On the other hand, the current switching type logic circuit has a characteristic that the transistor operates in a non-saturated region and thus has an extremely high operating speed, and is often used in logic circuits such as OR and NOR and various high-speed arithmetic circuits. ing. FIG. 4 is a block diagram of a conventional current switching type logic circuit. The current switching type logic circuit has a current switching type logic circuit in each of the input section 1 and the output section 2, and the emitter follower section 3 is connected between them. In addition, although this figure shows a so-called direct connection type example in which the output unit 2 is directly connected to an external load, the present invention is not limited to this. A type in which a buffer for current amplification is connected between the output unit 2 and an external load may be used.

In this figure, Q _{1 to} Q ₆ are bipolar transistors, R _{1 to} R ₄ are resistors, V _i1 and V _i2 are input voltages, V _out1 and V _out2 are output voltages, V _CC is a power supply voltage, 4 to
7 is a constant current source, and I _{1 to} I ₄ are constant currents. The configuration of the constant current sources 4 to 7 is such that a constant voltage V _const is typically applied to the base of a bipolar transistor Q ₇ whose emitter is grounded via a resistor R ₅ , as shown in FIG. .

Here, taking the output unit 2 as an example, a current switching type logic
The basic operation of the circuit will be described. Q now_Five, Q₆Respectively
With the same subscript to the base potential of V_Five, V₆And identify
Then if one is sufficiently smaller than the other, for example,
V_Five<< V₆In case of, Q_FiveIs off, I_FourIs
All on side Q₆Flows through. V_FiveIncreases, V_Five= V
₆Then, in principle, Q_Five, Q₆The same amount of current (I_Four
/ 2) flows. V_FiveIs further increased, Q_FiveIs on
Yes, but Q_FiveThe base-emitter voltage of is almost constant
Therefore, the common emitter potential (for convenience, "V_Ecomm")
Becomes higher, Q ₆Drive off. As a result, I
_FourIs all Q_FiveFlow through the Q to form a differential pair_Five, Q₆
Switching on and off is very fast.
The intended behavior is obtained.

By the way, in order to obtain such an operation, it is essential to use the transistors Q ₅ and Q ₆ forming a differential pair in the non-saturation region. Once in the saturation region,
This is because, as described at the beginning, extra charge is accumulated in the base of the transistor in the on state. For Q _5, Q ₆ and does not saturate the, Q _5, the collector of Q ₆ - it is necessary to suppress the emitter voltage within a specified voltage. The specified voltage depends on the transistor characteristics, but is approximately 0.2V
It is about 0.3V, which is by no means a large value. When the collector-emitter voltage exceeds this specified voltage, the operation in the non-saturated region is no longer possible, and a decrease in operating speed cannot be avoided.

Therefore, in the conventional current switching type logic circuit, the operation in the non-saturation region is maintained by making the emitter current constant and limiting the magnitude of the collector current. For example, the collector-emitter voltage V _{CE5 of} Q ₅
Is given by the following equation (1).

[0008]

[Equation 1]

[0009] The collector potential of Q ₅ extends from the power supply voltage V _CC is a potential obtained by subtracting the voltage drop R ₃ a (R ₃ · I _4), the potential difference between the potential and the common emitter potential V _eComm is defined The size of I ₄ is optimally designed so as to be within the voltage.

[0010]

However, in such a conventional current switching type logic circuit, an error of the common emitter potential V _Ecomm is unavoidable, and especially when used in a low voltage power supply, operational stability is improved. There was a problem of being damaged. If the values of R ₃ and I ₄ are ideal, the common emitter potential V _Ecomm is given by the following equation (2).

[0011]

(Equation 2)

Where V_BE3Is Q_ThreeBase-emitter
Voltage, V_BE5Is Q_FiveThe base-emitter voltage of
, Q_ThreeAnd Q_FiveIf you make the same process,
_BE3= V _BE5Therefore, these are "2V_BEAnd put
In other words, the equation (2) becomes the following equation (3). Sand
Chi, V_EcommIs the power supply voltage V_CCTo V_BE2 steps down
Given in rank.

[0013]

(Equation 3)

Substituting equation (3) into equation (1), the following equation (4) is obtained.

[0015]

(Equation 4)

What can be said from this equation (4) is that even if R
_ThreeAnd I_FourEven if the value of _BEVariation
If it does, V is proportional to the variation._CE5Changes
Therefore, it will hinder the operation in the unsaturated region.
It is. V_BEThe cause of the dispersion of
One (fixed error) and one due to temperature change (variable error)
There are two types of difference). As an example, the fixed error is 50 mV,
Variable error 250mV (however, the error per 1 ° C is 2mV
And operating temperature range is -40 ℃ to + 85 ℃ up to 125 ℃
And the calculation example)_BEGiven the formula
In (4), “2 · V_BE", So V_CE5Is 5
Double of 0mV + 250mV (that is, 600mV)
It will include a large error. So, of course, this
Since it is necessary to secure a margin more than the error,
In addition, it cannot be used with a low-voltage power supply where it is difficult to secure a margin.
There was a problem.

Therefore, the present invention has been made in view of the above technical problems, and eliminates the base-emitter voltage (V _BE ) of a transistor from the determinants of the common emitter potential, thereby reducing process error and operating temperature. The purpose is to avoid the influence and thus enable the use in a low-voltage power supply.

[0018]

In order to achieve the above object, the invention according to claim 1 has a first differential transistor and a second differential transistor, and a collector of the first differential transistor. Connect a load resistor between the
Load resistance is also connected between the differential transistor and the power supply, and the emitters of the first differential transistor and the second differential transistor are commonly connected to the first constant current source. In the current switching type logic circuit, the base of the first differential transistor is connected to the emitter of the first emitter follower transistor through the first emitter resistor, and the base of the second differential transistor is connected to the second differential transistor. A second emitter follower transistor connected to the emitter of the second emitter follower transistor via an emitter resistor of the second emitter follower transistor to supply the emitter current of the first and second emitter follower transistors.
Of the constant current source is constituted by a current mirror circuit, and the values of the first emitter resistance and the second emitter resistance are approximately doubled with respect to the value of the load resistance of the reference current side transistor of the current mirror circuit. It is characterized by being sized.

According to a second aspect of the present invention, in the first aspect of the invention, a base current compensating transistor is connected between the base and collector of the reference current side transistor of the current mirror circuit, and the current mirror circuit is connected. It is characterized in that the values of the first emitter resistance and the second emitter resistance are approximately one time larger than the value of the load resistance of the reference current side transistor of the circuit.

Alternatively, the invention according to claim 3 has a first differential transistor and a second differential transistor,
A load resistor is connected between the collector of the differential transistor and the power source, a load resistor is also connected between the second differential transistor and the power source, and the first differential transistor and the second differential transistor are connected. In a current switching type logic circuit configured by connecting the emitter of a differential transistor to a first constant current source in common, the base of the first differential transistor is connected to the emitter of a first emitter follower transistor, The base of the second differential transistor is connected to the emitter of the second emitter follower transistor, and the bases of the first and second emitter follower transistors are respectively connected to the differential outputs of the preceding differential amplification stage. , A constant current source of the differential amplification stage is configured by a current mirror circuit, and the load current value of the reference current side transistor of the current mirror circuit The value of the common load resistor of the differential transistors of the dynamic amplification stage is characterized by the almost doubled.

According to the first or second or third aspect of the present invention, the base-emitter voltage of the first or second emitter follower transistor and the first or second difference are determined by the base-emitter voltage of the transistor of the current mirror circuit. The base-emitter voltage of the dynamic transistor is canceled. Therefore, the problematic base-emitter voltage can be eliminated from the deciding element of the common emitter potential of the first and second differential transistors, the influence of process error and operating temperature can be avoided, and use in a low voltage power supply can be avoided. You can enable it.

[0022]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a diagram showing an embodiment of a current switching type logic circuit according to the invention described in claim 1. The same components as those in the conventional example (FIG. 4) are designated by the same reference numerals. The current switching type logic circuit of the present embodiment has an input section 1 and an output section 2 as in the conventional example, but the configuration of the emitter follower section 10 connecting them is partially different (broken line portion).

In this figure, Q₁~ Q₆, Q_Ten~ Q₁₂
Is a bipolar transistor, R₁~ R_Four, R_Ten~ R₁₂Is
Resistance, V_i1, V_i2Is the input voltage, V_out1, V_out2Is the output power
Pressure, V_CCIs a power supply voltage, 4 and 7 are constant current sources, and I₁, I_FourIs
It is a constant current. The relation of resistance is R₁= R_Two, R_Three= R
_Four, R₁₁= R₁₂And, 2 · R_Ten= R₁₁(=
R ₁₂).

Here, Q ₅ corresponds to the first differential transistor described in the gist of the invention, and Q ₆ corresponds to the second differential transistor. R ₃ is the collector of Q ₅ and the power source V
It corresponds to the load resistance connected between _CC , R ₄ corresponds to the load resistance connected between the collector of Q ₆ and the power supply, and
The constant current source 7 includes a first differential transistor (Q ₅ ) and a second differential transistor (Q ₅ ).
Corresponding to a constant current source connected to the common emitter of the differential transistor (Q ₆ ) of FIG.

The base of the first differential transistor (Q ₅ ) is connected to one end of a resistor R ₁₁ corresponding to the first emitter resistor, and the other end of R ₁₁ is connected to the first emitter follower transistor. It is connected to the corresponding emitter of Q ₃ . The base of the second differential transistor (Q ₆ ) is connected to one end of a resistor R ₁₂ corresponding to the second emitter resistor, and the other end of R ₁₂ corresponds to the second emitter follower transistor. It is connected to the emitter of Q ₄ .

Q _{10 to} Q ₁₂ surrounded by a broken line constitute a so-called current mirror circuit, and the first and second parts are formed.
Function as a second constant current source 11 for keeping the emitter currents of the emitter follower transistors (Q ₃ and Q ₄ ) of the above. I ₁₀ is a reference current of the current mirror circuit, and I ₁₁ and I ₁₂ are output currents having a one-to-one relationship with the reference current. That is, there is a relation of I ₁₀ = I ₁₁ = I ₁₂ .

In such a configuration, as in the conventional example, the base potential of Q ₅ is V ₅ , the base potential of Q ₆ is V ₆ , the common emitter potential of Q ₅ and Q ₆ is V _Ecomm, and R _{3 is} R _3. And I ₄ are idealized, V of this embodiment is
_Ecomm is given by the following equation (5).

[0028]

(Equation 5)

Since I ₁₁ = I ₁₂ and R ₁₁ = R ₁₂ , V _Ecomm does not change even if I ₁₁ in formula (5) is replaced with I ₁₂ and R ₁₁ is replaced with R ₁₂ . Below, I ₁₁
And R ₁₁ . The conventional formula corresponding to the formula (5) is the formula (3). Comparing the two equations (3) and (5),
In this embodiment, terms indicating the voltage drop of the R ₁₁ (-I ₁₁ · R
₁₁ ) is increasing. Since I ₁₁ of this term is equal to the reference side current I ₁₀ of the current mirror circuit, it is given by the following equation (6).

[0030]

(Equation 6)

Vx is a potential on one end side of the load resistor R ₁₀ , and V _BE10 is a potential on the other end side of the load resistor R ₁₀ .
That is, the term “Vx−V _BE10 ” in the equation (6) represents the voltage drop of the load resistance R ₁₀ . V _BE11 is the base-emitter voltage of Q ₁₁ , and if it has undergone the same manufacturing process as Q ₃ and Q ₅ , it is equivalent to V _BE3 and V _BE5 and has the same temperature characteristics. There is.

Substituting equation (6) into equation (5) above yields
(7), and V_BE10= V _BETherefore, the formula
(7) becomes the following equation (8).

[0033]

(Equation 7)

[0034]

(Equation 8)

There are two V _BE terms in equation (8). One is “2 · V _BE ” and the other is “(R ₁₁ / R ₁₀ ) · V _BE ”. The former exists also in the conventional example, but the latter is a term peculiar to the present embodiment. To erase "2 ・ V _BE ", press "R ₁₁ /
The answer to "R ₁₀ " should be "2". That is, the value of R ₁₁ (and R ₁₂ ) may be doubled with respect to the value of R ₁₀ . If such a relationship is set, the second term (−2 · V _BE + (R ₁₁ / R ₁₀ ) · V _BE ) on the right side of the above equation (8) is erased, so that the following equation (9) is eventually obtained. , V _Ecomm can be obtained in a pure form that is not affected by V _BE .

[0036]

(Equation 9)

Therefore, by substituting the equation (9) into the equation (1), the following equation (10) is obtained, and V _CE5 can be stabilized, and in particular, a low voltage power source in which it is difficult to secure a margin. In this way, it is possible to provide a useful technology that can be used without any problems, which is not available in the conventional technology.

[0038]

(Equation 10)

FIG. 2 is a diagram showing an embodiment of the current switching type logic circuit according to the invention described in claim 2, and is a modification of the above embodiment. The same components as those in the above embodiment are designated by the same reference numerals. The difference from the above embodiment is the current mirror circuit 11 'of the emitter follower section 10'. Specifically, one of the differences is that a base current compensation transistor Q ₁₃ is inserted between the base and collector of Q ₁₀ in order to avoid the influence of the base currents of Q ₁₀ and Q ₁₁ . According to this, the deviation of the current mirror ratio due to the base currents of Q ₁₀ and Q ₁₁ , that is, the collector current of Q ₁₁ is smaller than the current flowing through R ₁₀ on the reference side by the amount of the base current of Q ₁₀ + the base current of Q _11. Since it is possible to avoid the problem of mismatching of the current mirror characteristics such as the above, it is particularly suitable for an application requiring accuracy of the current mirror ratio.

The other difference is that the base current compensating transistor Q ₁₃ is inserted, and R ₁₀ and R
_The point is that the ratio of the values of ₁₁ (and R ₁₂ ) is 1: 1. That is, the answer of "R ₁₁ / R ₁₀ " is "1". The following expression (11) is I ₁₀ (= I ₁₁ = I ₁₂ ) in this embodiment.
It is an expression of. The difference from the corresponding equation (6) in the above embodiment is that V _BE is doubled. The increased V _BE is the base-emitter voltage of the base current compensation transistor Q ₁₃ .

[0041]

[Equation 11]

Substituting equation (11) into equation (5), the following equation (12) is obtained. To erase V _BE , use "R ₁₁ /
R ₁₀ the answer to the question of the "must be set to" 1 ".

[0043]

(Equation 12)

FIG. 3 is a diagram showing one embodiment of a current switching type logic circuit according to the invention of claim 3. The same components as those in the conventional example (FIG. 4) are designated by the same reference numerals. In the present embodiment, the output unit 2 and the emitter follower unit 3 have the same configuration as the conventional example, but the configuration of the input unit 20 is partially different (the broken line region). That is, the constant current source of the input section 20 is connected to the bipolar transistors Q ₂₀ , Q ₂₁ and the load resistor R.
It is composed of a current mirror circuit 21 consisting of ₂₀
The difference is that the ratio of the value of the common load resistance R ₂₁ of the differential transistors Q ₁ and Q ₂ of the input section 20 to the value of R ₂₀ is 1: 2.

In such a structure, the output unit 2 is commonly used.
Emitter potential V_EcommIs given by the following equation (13).
This formula has the same form as the formula (5) of the first embodiment, and R₂₀
And R _{twenty one}By making the ratio of
_EcommMore V_BEThe effect of can be eliminated.

[0046]

(Equation 13)

In the above description, a bipolar transistor is taken as an example, but the current switching type logic circuit composed of MOS transistors is not excluded. Rather, the temperature variation of the threshold voltage V _{th of the} MOS transistor (corresponding to V _BE of bipolar) is larger than that of bipolar, so it is preferable to apply it to the MOS type.

[0048]

According to the present invention, the base-emitter voltage (V _BE ) of the transistor can be eliminated from the determinants of the common emitter potential, and the influence of process error and operating temperature can be avoided. Therefore, in particular, it is possible to provide a useful circuit technique that can be used even with a low-voltage power supply without any trouble.

[Brief description of the drawings]

FIG. 1 is a configuration diagram of an embodiment according to the first aspect of the present invention.

FIG. 2 is a configuration diagram of one embodiment according to the invention described in claim 2;

FIG. 3 is a configuration diagram of an embodiment according to the invention of claim 3;

FIG. 4 is a configuration diagram of a conventional example.

FIG. 5 is a general configuration diagram of a constant current source.

[Explanation of symbols]

Q _3: the first emitter follower transistor Q _4: second emitter follower transistor Q _5: first differential transistor Q _6: second differential transistors Q _10: the reference current-side transistor R _3: the load resistance R ₄ : Load resistance R ₁₀ : load resistance R ₁₁ : first emitter resistance R ₁₂ : second emitter resistance V _CC : power supply 7: first constant current source 11: second constant current source

Claims (3)

[Claims] 1. A first differential transistor and a second differential transistor, wherein a load resistor is connected between the collector of the first differential transistor and a power supply, and the second differential transistor and the A current switching logic circuit configured by connecting a load resistor also to a power source and connecting the first differential transistor and the second differential transistor to the first constant current source with the emitters of the first differential transistor and the second differential transistor in common. In, the base of the first differential transistor is connected to the emitter of the first emitter follower transistor via a first emitter resistor, and the base of the second differential transistor is connected via a second emitter resistor. A second constant current source connected to the emitter of the second emitter follower transistor and supplying the emitter current of the first and second emitter follower transistors is a current mirror. And the value of the first emitter resistance and the value of the second emitter resistance are approximately twice as large as the value of the load resistance of the reference current side transistor of the current mirror circuit. Current switching type logic circuit. 2. A base current compensating transistor is connected between a base and a collector of the reference current side transistor of the current mirror circuit, and the load current value of the reference current side transistor of the current mirror circuit is compared with the load resistance value of the transistor. 2. The current switching type logic circuit according to claim 1, wherein the values of the first emitter resistance and the second emitter resistance are set to approximately 1 times. 3. A first differential transistor and a second differential transistor, wherein a load resistance is connected between the collector of the first differential transistor and a power supply, and the second differential transistor and the A current switching logic circuit configured by connecting a load resistor also to a power source and connecting the first differential transistor and the second differential transistor to the first constant current source with the emitters of the first differential transistor and the second differential transistor in common. At the base of the first differential transistor is connected to the emitter of a first emitter follower transistor, the base of the second differential transistor is connected to the emitter of a second emitter follower transistor, Each base of the second emitter follower transistor is connected to the differential output of the preceding differential amplification stage, and the constant current source of the differential amplification stage is configured by a current mirror circuit. In addition, the value of the common load resistance of the differential transistor of the differential amplification stage is almost doubled the value of the load resistance of the reference current side transistor of the current mirror circuit. .