JPH07106561A - Semiconductor device - Google Patents

Abstract

PURPOSE:To make difficult generation of short-channel effect by making shallower the junction depth of P-type low concentration inpurity diffused region of PMOSFET. CONSTITUTION:High concentration boron is doped to form a source region 34 and a drain region 36 sandwiching a channel region 33 of an N-type silicon substrate 32 and low concentration indium is doped to form P type impurity low concentration diffused regions 38, 40 in the area closer to the channel than the source/drain regions 34, 36, in order to form PMOSFET of the LDD structure. A polysilicon gate electrode 44 is formed on the channel region through a gate oxide film 42.

Description

Detailed Description of the Invention

[0001]

The present invention relates to an LDD (Lightly-Doped).
Drain structure PMOSFET (P-channel type MOSF)
The present invention relates to a semiconductor device having a PMOSFET having a low impurity concentration and a P-type impurity diffusion region having a shallow junction depth, such as an N-type polysilicon gate PMOSFET.

[0002]

NMO in which hot electrons are a problem
In SFET (N-channel type MOSFET), an LDD structure is used in order to relax a high electric field near the drain. In the LDD structure NMOSFET, an N-type impurity diffusion region having a low donor concentration is provided on the channel side of the source / drain region of the high concentration impurity diffusion region, and the drain depletion layer generated in the pinch-off state is extended to the drain side. Is to alleviate the high electric field in the drain depletion layer.

Since the impurity concentration distribution in the drain junction portion of the PMOSFET is gentler than that of the NMOSFET using arsenic, the electric field applied to the drain depletion layer in the pinch-off state does not become so high, so that the LDD structure is not required. . However, as device miniaturization progresses, PMO of LDD structure is advantageous for measures against hot carriers, shallow source / drain junction, and reduction of lateral diffusion.
SFET is being adopted. In PMOSFET, boron is used as a P-type impurity forming a P-type diffusion region.

A CMOS semiconductor device using a polysilicon gate employs the same N-type polysilicon gate for NMOSFET and PMOSFET. By using the same gate conductive material for both FETs, the process is simplified and the PMO with low mobility is used.
There is an advantage that the SFET becomes a buried channel and mobility can be increased. N-type polysilicon gate P
In the MOSFET, boron is introduced as a P-type impurity on the substrate surface of the channel region in order to adjust the threshold voltage.

FIG. 1 shows a CMOS using an N-type polysilicon gate electrode common to NMOSFET and PMOSFET.
1 shows a semiconductor device together with a manufacturing method. (A) P on the P-type silicon substrate 2 having a specific resistance of about 20 Ωcm
Well 4 and N well 6 are formed. Boron is implanted to form the P well 4, phosphorus is implanted to form the N well 6, and the depth is about 3 μm by high temperature heat treatment at about 1100 ° C.
m P well 4 and N well 6 are formed. Such a system is called a twin-tab system, and has a PMOSFET and an NM.
Both OSFETs can be made in good balance.

(B) A field oxide film 8 for element isolation is formed to a thickness of about 5000 Å by using the LOCOS method.
At this time, in order to prevent the formation of the parasitic transistor,
Boron is introduced into the P well portion below the field oxide film 8 as the inversion preventing impurity diffusion layer 10.

(C) A gate oxide film 12 having a thickness of about 150Å is formed on the substrate surface, and ion implantation is performed on the substrate surface for adjusting the threshold voltage. Ion implantation is PMOSFE
Boron is used for both T and NMOSFET, and is about 0.7.
The implantation amount is determined so that the threshold voltage is V.

(D) A polysilicon film to be a gate electrode is deposited to a thickness of about 3000Å, and is made N-type by phosphorus diffusion to have a low resistance, and then patterned into an electrode shape to form a gate electrode 16.

(E) Next, NMOSFET and PMOSF
Source / drain regions 20, 22 and 2 for ET, respectively
4, 26 are formed. After that, an interlayer insulating film 28 is deposited, a contact hole is opened, a metal wiring 30 is formed, and a CMOS semiconductor device is formed. The source / drain region has an LDD structure, especially in NMOSFET, but is shown as a single drain structure in FIG. 1 for simplicity.

[0010]

The miniaturization of devices is progressing,
As the channel length becomes shorter, the LDD structure of the PMOS
The short channel effect also begins to occur in the FET. In addition, shallow source-drain junctions and reduction of lateral diffusion have been desired. LDD structured PMOS FE
At T, in order to suppress the short channel effect, it is effective to make the junction depth of the P-type low-concentration impurity diffusion region shallow, for example, 0.1 μm or less. However, since boron is used as the P-type impurity in the P-type low-concentration impurity diffusion region and boron has a large diffusion coefficient, it is difficult to make the P-type low-concentration impurity diffusion region shallow.

Therefore, a first object of the present invention is to provide a semiconductor device having a PMOSFET having an LDD structure.
This is to make the junction depth of the P-type low-concentration impurity diffusion region of the MOSFET shallow to make the short channel effect less likely to occur.

CMOS using N-type polysilicon gate
In a semiconductor device, a P-type impurity is introduced into a substrate surface of a channel region of a PMOSFET to adjust a threshold voltage to form a buried channel MOSFET. But,
Also in this case, as the miniaturization progresses and the channel length becomes shorter,
The short channel effect, which is a major problem of buried channel devices, becomes remarkable. As a countermeasure against this, it is effective to make the depth of the P-type undoped diffusion layer on the channel surface as shallow as 0.1 μm or less. However, by using boron as the P-type impurity introduced into the substrate surface of the channel region. Since boron has a large diffusion coefficient, it is difficult to reduce the depth of the P-type impurity diffusion layer on the channel surface.

Therefore, a second object of the present invention is to provide a semiconductor device having an N-type polysilicon gate PMOSFET with a short channel effect by reducing the depth of the P-type undoped diffusion layer on the substrate surface of the channel region of the PMOSFET. Is to make it less likely to happen.

[0014]

Means for Solving the Problems PMOSF of LDD structure
In the present invention applied to a semiconductor device having ET, the PMO
Indium alone or indium and boron are introduced as P-type impurities into the low-concentration impurity diffusion region of the SFET.

In the present invention applied to a semiconductor device having an N-type polysilicon gate PMOSFET, the PMOS FE is used.
Indium alone or indium and boron are introduced as P-type impurities into the substrate surface of the T channel region for adjusting the threshold voltage.

Boron is used as a P-type impurity when forming a P-type impurity diffusion layer in silicon. This is because the group 3 elements other than boron have a low activity value of about 10 ¹⁸ atoms / cm ³ or less as a P-type impurity, and form a high-concentration and low-resistance P-type diffusion layer such as a source / drain region. Because it is impossible to do. However, the concentration of P-type low-concentration impurity diffusion regions of the PMOSFET of the LDD structure is not a high concentration such as high concentration source and drain regions, 10 ¹⁸ atoms / cm ³ or so. Therefore, in the present invention, indium is used for this P-type low concentration impurity diffusion region. Indium has a low activation rate, but P of LDD structure
The activation rate required for the low-concentration impurity diffusion region can be achieved. Since indium has a small diffusion coefficient, the junction depth of the P-type impurity diffusion region of the LDD structure can be made as shallow as 0.1 μm or less.

When the concentration of the P-type impurity diffusion region of only indium is less than the required concentration of the P-type low-concentration impurity diffusion region of the LDD structure, boron is introduced to fill the insufficient concentration. In this case, it is possible to form the P-type low-concentration impurity diffusion region shallower than the P-type low-concentration impurity diffusion region by using only boron.

The P-type impurity low-concentration diffusion region formed on the substrate surface of the channel region of the N-type polysilicon gate PMOSFET has a maximum of 10 ¹⁸ atoms / cm ³ . Indium has a low activation rate, but this buried channel type PMOSF
It can be used to form a P-type impurity low concentration diffusion region on the channel surface of ET. Since indium has a small diffusion coefficient, the junction depth of the P-type impurity low-concentration diffusion region can be made as shallow as 0.1 μm or less.

Also in this case, when the concentration of the P-type impurity diffusion region only for indium is less than the required concentration of the P-type impurity diffusion region on the channel surface, the amount not satisfied is supplemented by the introduction of boron. In this case, it is possible to form the P-type low-concentration impurity diffusion region shallower than the P-type low-concentration impurity diffusion region by using only boron.

[0020]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 2 shows a PMOSFET having an LDD structure according to the present invention.
An example applied to Surface concentration is about 1 × 10 ¹⁷
A source region 34 and a drain region 36 are formed by introducing boron at a high concentration across the channel region 33 of the N-type silicon substrate or the N well 32 of atoms / cm ³ .
A P-type impurity low-concentration diffusion region 38.40 in which indium is introduced at a low concentration is formed on the channel region side of the source / drain regions 34 and 36.

A film thickness of about 10 is formed on the channel region on the substrate.
A polysilicon gate electrode 44 having a film thickness of about 3000Å is formed through a 0Å gate oxide film 42. On the side surface of the gate electrode, a sidewall 46 of a silicon oxide film used for forming an impurity diffusion region of LDD structure is formed. Reference numeral 48 denotes an interlayer insulating film, and the aluminum-based metal wiring 50 is connected to the source region, the drain region, and the gate electrode through contact holes formed in the interlayer insulating film 48.

Next, a method of manufacturing the PMOSFET of FIG. 2 will be described with reference to FIG. (A) A gate oxide film 42 of about 100 Å is formed on an N-type silicon substrate or N well 32 having a surface concentration of about 1 × 10 ¹⁷ atoms / cm ³ , and a polysilicon film 44 of about 3000 Å is formed thereon. The polysilicon film 44 and the gate oxide film 42 are patterned into a gate electrode shape by photolithography and etching.

(B) Indium ion implantation is performed to form a P-type impurity low-concentration diffusion region of LDD structure.
Implantation of indium is performed at an implantation energy of 50 so that the junction depth of the P-type impurity low-concentration diffusion region becomes about 0.05 μm.
keV, dose 1 × 10 ¹¹ to 1 × 10 ¹⁴ atoms / c
carried out in m ^2.

(C) A high temperature oxide film is formed and etched back to form a sidewall 46 of a silicon oxide film having a thickness of about 1000 Å on the side surface of the gate electrode. In order to form the source region and the drain region of the P-type impurity high-concentration diffusion region, the gate electrode 44 having the sidewalls 56 is used as a mask to implant BF ₂ ions into the substrate or well with an implantation energy of 20 keV and a dose amount of 2 × 1.
It is performed at 0 ¹⁵ atoms / cm ² . The implantation energy and dose amount are not limited to these values, and may be set to commonly used values.

(D) After that, an interlayer insulating film 48 is deposited by a usual method, a contact hole is opened, and a metal wiring 50 is formed. LDD of FIG. 2 created by this method
The PMOSFET having the structure had a channel length of 0.4 μm and a threshold voltage of 0.7 V, and exhibited good operation without a short channel effect. Although not shown in FIG. 3, the element isolation region is formed before the gate oxide film is formed.

Another embodiment in which the present invention is applied to a PMOSFET having an LDD structure is one in which indium and boron are introduced as the P type impurity low concentration diffusion regions 38 and 40 in FIG. In this case, the P-type impurity low concentration diffusion region 3
In the ion implantation for forming 8 and 40, the implantation of indium is performed at an energy of 50 ke so that the junction depth of the P-type impurity low concentration diffusion regions 38 and 40 becomes about 0.05 μm.
The dose is 1 × 10 ¹¹ to 1 × 10 ¹⁴ / cm ² and the implantation of boron is performed at an energy of 1 to 10 keV and a dose of 1 × 10 ¹¹ to 1 × 10 ¹⁴ / cm ² . The structure of the other parts and the manufacturing process of the other parts are the same as in the embodiment of FIG.

A PMOS obtained by introducing both indium and boron into the P-type impurity low concentration diffusion region.
The FET has a channel length of 0.4 μm and a threshold voltage of 0.7.
At V, good operation without short channel effect was shown. Figure 2
Compared with the embodiment described above, the P-type impurity low concentration diffusion region 3
Since the resistances of 8 and 40 were low, the on-current of the transistor was improved by about 10%.

An embodiment in which the present invention is applied to an N-type polysilicon gate CMOS semiconductor device will be described with reference to FIG. P-well 4 on P-type silicon substrate 2 with specific resistance of about 20 Ωcm
And an N well 6 are formed. The surface concentration of both wells is about 1 × 10 ¹⁷ atoms / cm ³ and the depth is about 3 μm.
An NMOSFET is formed in the P well 4 and a P well 6 is formed.
Has a PMOSFET formed therein.

The structure of the NMOSFET is shown in FIG.
Similar to the MOSFET, a source region 20 and a drain region 22 are formed across the channel region, and boron is injected into the surface of the channel region for adjusting the threshold voltage to form the P-type impurity low concentration diffusion region 14. Has been formed.
An N-type polysilicon gate electrode 16 is formed on the channel region via a gate oxide film 12.

In comparison with the conventional PMOSFET shown in FIG. 1, indium is introduced as a P-type impurity in the P-type impurity low concentration diffusion region 15 formed in the channel region for adjusting the threshold voltage. different. The other structure is the same, and the source region 24 and the drain region 26 of the P-type impurity diffusion region are formed across the channel region, and the N-type polysilicon gate electrode 16 is formed on the channel region via the gate oxide film 12. Has been formed. 28 is an interlayer insulating film, and 30 is F through a contact hole of the interlayer insulating film.
It is an aluminum-based metal wiring connected to each part of ET.

A method of manufacturing the embodiment of FIG. 4 will be described with reference to FIGS. (A) Similar to FIG. 1, a P well 4 and an N well 6 are formed on the surface of a P type silicon substrate 2. (B) Similar to FIG. 1, the field oxide film 8 for element isolation and the inversion preventing impurity diffusion layer 10 are formed by using the LOCOS method.

(C) Ion implantation for adjusting the threshold voltage of the PMOSFET is performed. Conventionally, boron is implanted after forming a buffer oxide film for preventing channeling or after forming the gate oxide film 12 as shown in FIG. 1C, but in this embodiment, indium is implanted so that the gate oxide film is formed. Ion implantation of indium is performed before forming 12. In the implantation of indium, the region where the NMOSFET is formed is covered with the resist layer 11 so that the indium is implanted only in the region where the PMOSFET is formed. The implantation of indium has an energy of about 50 KeV and a dose of 1 × 10 ¹⁰ to 1 × 10 so that the junction depth of the P-type impurity diffusion layer on the channel surface is about 0.05 μm.
Perform at ¹³ / cm ² .

(D) Next, about 100 Å of the gate oxide film 1
Form 2. In order to adjust the threshold voltage of the NMOSFET, the PMOSFET formation region is covered with a resist layer, and boron ions are implanted into the NMOSFET formation region. The implantation of boron ions is performed with an energy of 10 KeV and a dose of about 1 × 10 ¹² atoms / cm ² .

(E) Similar to (D) of FIG. 1, the gate electrode 16 is formed. (F) After that, as in FIG. 1, NMOSFET and PMO
Source / drain regions 20 and 22 for SFET, respectively
24 and 26 are formed, then an interlayer insulating film 28 is deposited, a contact hole is opened, and a metal wiring 30 is formed to form a CMOS semiconductor device.

The minimum channel length of the CMOS semiconductor device manufactured according to this embodiment is PMOSFET and NMOSFE.
T is about 0.4 μm, and the threshold voltage is PMOSF
The ET was 0.8 V and the NMOSFET was 0.6 V. Especially, the PMOSFET showed good operation without the short channel effect.

In another embodiment in which the present invention is applied to a CMOS semiconductor device, both indium and boron are introduced into the P-type low concentration impurity diffusion layer 15 on the channel surface for adjusting the threshold voltage of the PMOSFET. .

In order to manufacture the semiconductor device of the embodiment in which indium and boron are both introduced into the P type low concentration impurity diffusion layer 15, boron is implanted in the step (D) of FIG. 5 for adjusting the threshold voltage of the NMOSFET. After that, the NMOSFET formation region is covered with a resist layer, and boron ions are applied to the PMOSFET formation region with an energy of 1 to 10 KeV and a dose of 1 ×.
It is performed at 10 ¹¹ to 1 × 10 ¹⁴ / cm ² .

According to the embodiment in which both indium and boron are introduced into the P type low concentration impurity diffusion region 15 on the channel surface of the PMOSFET, the minimum channel length is PMOSFE.
Both T and NMOSFET are about 0.4 μm, and the threshold voltage is 0.6V for both PMOSFET and NMOSFET.
In particular, the PMOSFET showed good operation without the short channel effect. Although the source / drain region is shown as a single drain structure in FIG.
It is preferable that T has an LDD structure.

[0039]

In the invention in which the present invention is applied to the PMOSFET having the LDD structure, by using indium having a small diffusion coefficient in the formation of the P type impurity low concentration diffusion region, LD
The junction depth of the P-type low-concentration impurity diffusion region of the D structure is about 0.
Since it can be made as shallow as 1 μm or less, it is possible to achieve a PMOSFET in which a short channel effect is unlikely to occur. By using indium and boron together to form the P-type impurity low-concentration diffusion region of the LDD structure, the junction depth of the P-type impurity low-concentration diffusion region can be made as shallow as 0.1 μm or less, and the P-type impurity low-concentration region can be further reduced. The resistance of the concentration diffusion region can be lowered, and the on-current of the transistor can be increased.

The present invention is an N-type polysilicon gate CMOS.
In the invention applied to the semiconductor device, by using indium for the ion implantation for adjusting the threshold voltage of the PMOSFET, the depth of the P-type layer on the channel surface of the buried channel PMOSFET can be made as shallow as about 0.1 μm. Therefore, the minimum channel length, which could not be formed in the past, is about 0.
A 4 μm buried channel type PMOSFET can be realized. Further, by using both indium and boron for ion implantation for adjusting the threshold voltage of the PMOSFET, the depth of the P-type impurity low-concentration diffusion region on the channel surface of the buried channel PMOSFET is reduced to about 0.
It is possible to realize a buried channel type PMOSFET having a low threshold voltage while keeping it as shallow as 1 μm or less.

[Brief description of drawings]

FIG. 1 is a process sectional view showing a method of manufacturing a conventional N-type polysilicon gate CMOS semiconductor device.

FIG. 2 is a cross-sectional view showing an embodiment in which the present invention is applied to a PMOSFET having an LDD structure.

FIG. 3 is a process sectional view showing the manufacturing method of the embodiment in FIG.

FIG. 4 is a sectional view showing an embodiment in which the present invention is applied to an N-type polysilicon gate CMOS semiconductor device.

FIG. 5 is a process sectional view showing a front half of the manufacturing method according to the embodiment of FIG. 4;

FIG. 6 is a process sectional view showing a latter half of the manufacturing method according to the embodiment of FIG. 4;

[Explanation of symbols]

2 P-type silicon substrate 12,42 Gate oxide film 16,44 Gate electrode 20, 22, 24, 26, 34, 36 Source / drain region 15 Diffusion layer of channel surface by indium 32 N-type silicon substrate 38, 40 LDD by indium P-type impurity low concentration diffusion region of structure

Claims (4)

[Claims] 1. A semiconductor device having an LDD-structured PMOSFET, wherein indium is introduced as a P-type impurity into a low-concentration impurity diffusion region of the PMOSFET. 2. A semiconductor device having an LDD-structured PMOSFET, wherein indium and boron are introduced as P-type impurities in a low-concentration impurity diffusion region of the PMOSFET. 3. N-type polysilicon gate PMOSFET
In the semiconductor device having the above-mentioned structure, P is formed on the substrate surface of the channel region of the PMOSFET for adjusting the threshold voltage.
A semiconductor device in which indium is introduced as a type impurity. 4. N-type polysilicon gate PMOSFET
In the semiconductor device having the above-mentioned structure, P is formed on the substrate surface of the channel region of the PMOSFET for adjusting the threshold voltage.
A semiconductor device in which indium and boron are introduced as type impurities.