JPH07106551A - Electric charge detecting element - Google Patents
Electric charge detecting elementInfo
- Publication number
- JPH07106551A JPH07106551A JP5239261A JP23926193A JPH07106551A JP H07106551 A JPH07106551 A JP H07106551A JP 5239261 A JP5239261 A JP 5239261A JP 23926193 A JP23926193 A JP 23926193A JP H07106551 A JPH07106551 A JP H07106551A
- Authority
- JP
- Japan
- Prior art keywords
- channel
- sensing channel
- charge
- region
- sensing
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Landscapes
- Solid State Image Pick-Up Elements (AREA)
Abstract
Description
【0001】[0001]
【産業上の利用分野】本発明は、高感度の電荷検出素子
の構造に関し、特にCCDイメージセンサ等のような微
少な信号電荷を高い感度で検出する必要のある素子の素
子製造に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a structure of a high-sensitivity charge detection device, and more particularly to the manufacture of a device such as a CCD image sensor which needs to detect a minute signal charge with high sensitivity.
【0002】[0002]
【従来の技術】例えば、固体撮像素子の電荷検出部を説
明する。図5は株式会社東芝のS.Oosawaらによ
って1988年International Conf
erence on Solid State Dev
ice and Materials(Fxtende
d Abstractspp.355−358)にて発
表されたフローティング表面検出器の断面図を示すもの
で、n型基板1の表面にp- ウェル層2を形成し、基板
より高濃度のn型領域であるセンシングチャネル5とp
+ 領域のソース及びドレイン領域20,21と、前記セ
ンシングチャネル5上に形成されたゲート酸化膜4と、
ゲート酸化膜4上に形成されたフローティングゲート1
2と、フローティングゲート12上に形成された厚い絶
縁層15と、厚い絶縁膜15上に形成されたバイアスゲ
ート14と、からなる。2. Description of the Related Art For example, a charge detector of a solid-state image pickup device will be described. Figure 5 shows Toshiba S.I. 1988 International Conf by Ozawa et al.
erence on Solid State Dev
ice and Materials (Fxende
d Abstractsspp. 355-358), which shows a cross-sectional view of a floating surface detector, in which a p - well layer 2 is formed on the surface of an n-type substrate 1 and a sensing channel 5 which is an n-type region having a higher concentration than the substrate. And p
Source and drain regions 20 and 21 of the + region, the gate oxide film 4 formed on the sensing channel 5,
Floating gate 1 formed on gate oxide film 4
2, a thick insulating layer 15 formed on the floating gate 12, and a bias gate 14 formed on the thick insulating film 15.
【0003】前記センシングチャネル5は、断面図平面
に垂直な方向に電荷を電送するCCDに接続され、埋込
チャネル(図示せず)内を信号電荷が転送されて来る。
転送された来た信号電荷がセンシングチャネル5内に蓄
積されると、センシングチャネル5内の電位分布が変化
されてゲート酸化膜4とセンシングチャネル5との界面
電位およびフローティングゲート12電位が変化する。
この電位変化により、ホールをキャリアとし、ゲート酸
化膜4およびセンシングチャネル5界面をp型表面チャ
ネルとするトランジスタが動作する。The sensing channel 5 is connected to a CCD that transfers electric charges in a direction perpendicular to the plane of the sectional view, and signal charges are transferred in an embedded channel (not shown).
When the transferred signal charges are accumulated in the sensing channel 5, the potential distribution in the sensing channel 5 is changed and the interface potential between the gate oxide film 4 and the sensing channel 5 and the floating gate 12 potential are changed.
Due to this potential change, the transistor using holes as carriers and the interface between the gate oxide film 4 and the sensing channel 5 as a p-type surface channel operates.
【0004】[0004]
【発明が解決しようとする課題】このトランジスタは、
センシング容量を非常に小さくできるうえ、寄生容量が
ほとんど無いので、高感度の動作が可能となる。また、
センシングチャネルは、完全に空乏化させる条件で信号
転送するから、信号電荷の完全転送が可能となり、1/
fノイズなどが非常に低く抑えられる。This transistor is
Since the sensing capacitance can be made extremely small and there is almost no parasitic capacitance, highly sensitive operation is possible. Also,
Since the sensing channel transfers signals under the condition of being completely depleted, it becomes possible to transfer signal charges completely.
f noise and the like can be suppressed to a very low level.
【0005】東芝は、76μV/e- 高感度64μV.
rms(雑音等価信号〜1.2エレクトロンrms)以
下という低雑音を両立したと報告しているが、図5に示
すように、このトランジスタのソースとドレインがp-
ウェルのような導電性であり、キャリアが信号電荷とは
反対符号という問題点がある。p- ウェルは、通常接地
されるからソースとかドレインには、ウェル内の全ての
領域からホールが拡散することとなる。したがって、こ
のホールによる暗電流のショートノイズの影響が問題に
なると考えられる。Toshiba uses 76 μV / e - high sensitivity of 64 μV.
Although it has been reported that the low noise of rms (noise equivalent signal to 1.2 electron rms) or less is achieved at the same time, as shown in FIG. 5, the source and drain of this transistor are p − −.
There is a problem that the carrier is conductive like a well, and the carrier has the opposite sign to the signal charge. Since the p - well is normally grounded, holes are diffused into the source or the drain from all regions in the well. Therefore, it is considered that the influence of the dark current short noise due to the holes becomes a problem.
【0006】また、入射光のある場合に、ホールは電子
の数と同じ数だけ発生するが、電子についてはオーバー
フロードレインがあるのに対し、ホールについては確実
に機能するドレインの構造がない。周辺部にp- ウェル
の接触があるが、画素部からの距離は非常に長くなるの
で、強い入射光が入る場合などに、一時的に増加したホ
ールの漏れ電流により信号電流が上昇する現象が発生す
る可能性がある。When incident light is present, holes are generated by the same number as the number of electrons. However, while electrons have overflow drains, holes do not have a functioning drain structure. Although there is a p - well contact in the peripheral part, the distance from the pixel part is very long. Therefore, when strong incident light enters, there is a phenomenon that the signal current rises due to the temporarily increased leakage current of holes. Can occur.
【0007】このような問題を解決するために、基板を
p+ 型として電子の水平オーバーフロードレイン構造を
止めるとか、電荷検出部のウェルを画素部に独立させる
とか、といった方法があるが、これらはほとんど不能で
ある。本発明の目的は、上述した従来技術の問題を解決
するためのもので、キャリアがエレクトロンであるトラ
ンジスタを用いて電子の電荷量を検出することができる
電荷検出装置を提供することである。それによって暗電
流によるショートノイズを低下させ、感度を改善しよう
とするものである。In order to solve such a problem, there are methods such as using a substrate of p + type to stop the horizontal overflow drain structure of electrons, or making the well of the charge detection section independent of the pixel section. Almost impossible. An object of the present invention is to solve the above-mentioned problems of the prior art, and to provide a charge detection device capable of detecting the charge amount of electrons by using a transistor whose carrier is an electron. Thereby, short noise due to dark current is reduced and sensitivity is improved.
【0008】[0008]
【課題を解決するための手段】本発明はp型チャネルト
ランジスタを用いた表面領域にキャリアとして電子を用
いたn型チャネルトランジスタを用い、n型センシング
チャネルの表面にp型チャネルのトランジスタが形成さ
れ、センシングチャネルとそれぞれのソース・ドレイン
との間のn+ 領域の表面部分がpウェル層で形成される
反転可能なチャネル分離領域を形成している。センシン
グチャネル表面に、センシングチャネルとは反対導電型
の領域を形成することにより、フローティングゲート下
方に、電子の表面チャネルが形成され、センシングチャ
ネルへ転送される電荷量に対応して表面チャネルが変形
される。また、センシングチャネルとソース、およびセ
ンシングチャネルとドレイン間の表面反転可能なチャネ
ル分離領域を設けることで、ソースおよびドレインから
表面チャネル領域に電流が流れ、埋込チャネル領域には
流れない構造となる。The present invention uses an n-type channel transistor using electrons as carriers in the surface region using a p-type channel transistor, and a p-type channel transistor is formed on the surface of an n-type sensing channel. The surface portion of the n + region between the sensing channel and each source / drain forms an invertible channel isolation region formed by the p well layer. By forming a region of the opposite conductivity type to the sensing channel on the surface of the sensing channel, a surface channel of electrons is formed below the floating gate, and the surface channel is deformed according to the amount of charges transferred to the sensing channel. It Further, by providing the surface-reversible channel separation region between the sensing channel and the source and between the sensing channel and the drain, a current flows from the source and the drain to the surface channel region, but does not flow to the buried channel region.
【0009】このように検出される電荷と同じ導電型の
キャリアが流れるトランジスタを用いることで、ウェル
層からの暗電流の問題が解決され、暗電流に起因するシ
ョートノイズが低減されて、さらに高感度の電荷検出素
子が提供されるようになる。また、強い光が入射される
場合の信号出力の上昇現象等を心配する必要がない。ソ
ース,ドレイン領域を形成するために、追加したp+ 領
域の形成工程も省略できる。By using a transistor in which carriers of the same conductivity type as the detected charges flow, the problem of dark current from the well layer is solved, short noise due to dark current is reduced, and the noise is further increased. A sensitive charge detection element is provided. In addition, there is no need to worry about a phenomenon such as an increase in signal output when strong light is incident. It is also possible to omit the step of forming an additional p + region for forming the source and drain regions.
【0010】[0010]
【実施例】以下、添付図面に基づいて本発明の一実施例
をCCDのイメージセンサの電荷検出部に利用する場合
を例として説明する。図1は、CCDにより信号電荷が
転送される方向の断面構造図である。n型Si基板1の
表面にp- ウェル層2が形成され、前記p- ウェル層2
の表面部位にn型埋込チャネル3とn型センシングチャ
ネル5、p型表面チャネル6およびリセットドレイン7
がそれぞれ所定領域上に形成され、その上部にはゲート
酸化膜4が形成され、リセットゲート13およびCCD
転送電極8,9,10,出力ゲート11,フローティン
グゲート12が前記ゲート酸化膜4上に形成され、前記
フローティングゲート12上に厚い絶縁層15とバイア
スゲート14がそれぞれ形成された構造となっている。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A preferred embodiment of the present invention will be described below with reference to the accompanying drawings, in which the charge detecting portion of a CCD image sensor is used. FIG. 1 is a sectional structural view in the direction in which signal charges are transferred by the CCD. the n-type Si surface of the substrate 1 p - well layer 2 is formed, the p - well layer 2
The n-type buried channel 3, the n-type sensing channel 5, the p-type surface channel 6 and the reset drain 7 on the surface part of the
Are formed on predetermined regions, and a gate oxide film 4 is formed on the predetermined regions, and the reset gate 13 and the CCD are formed.
Transfer electrodes 8, 9, 10, an output gate 11, and a floating gate 12 are formed on the gate oxide film 4, and a thick insulating layer 15 and a bias gate 14 are formed on the floating gate 12, respectively. .
【0011】これらのうち、本発明に直接的に関係され
る部分は、参照符号5,6,12,14,15で示した
部分で構成される領域であり、これらの部分の垂直方向
断面図を図3に示した。これらの領域はCCDにより転
送電荷を検出して動作するn型表面チャネルトランジス
タに対応する。CCDイメージセンサの場合、入射光に
より各画素のフォトダイオードから発生した信号電荷
は、CCDにより埋込チャネル3内に転送されて図1の
右方からセンシングチャネル5へ流入する。Of these, the portions directly related to the present invention are the regions constituted by the portions indicated by reference numerals 5, 6, 12, 14, and 15, and the vertical sectional views of these portions. Is shown in FIG. These regions correspond to n-type surface channel transistors which operate by detecting transfer charges by the CCD. In the case of a CCD image sensor, the signal charges generated from the photodiode of each pixel by the incident light are transferred into the embedded channel 3 by the CCD and flow into the sensing channel 5 from the right side in FIG.
【0012】この時、リセットドレイン7,リセットゲ
ート13,バイアスゲート14,出力ゲート11および
CCD転送電荷8,9,10は、それぞれ適当な電圧に
バイアスされ、信号電荷を転送するチャネルの電位形状
は図2に示すようなものとなる。センシングチャネル5
に信号電荷が流入すれば、センシングチャネル5内の電
位が変化し、センシングチャネル領域6の表面電位も変
化する。At this time, the reset drain 7, the reset gate 13, the bias gate 14, the output gate 11 and the CCD transfer charges 8, 9 and 10 are respectively biased to appropriate voltages, and the potential shape of the channel for transferring the signal charges is changed. The result is as shown in FIG. Sensing channel 5
When the signal charge flows in, the potential inside the sensing channel 5 changes and the surface potential of the sensing channel region 6 also changes.
【0013】センシングチャネルを含む基板深さの方向
の断面構造と、これに対応する電位分布を図4(a),
(b)に示す。センシングチャネル5内に電荷の無い場
合の電位分布を実線で、飽和される時まで電荷の流入さ
れた場合の電位分布を破線で示した。The cross-sectional structure in the direction of the substrate depth including the sensing channel and the corresponding potential distribution are shown in FIG.
It shows in (b). The potential distribution in the case where there is no charge in the sensing channel 5 is shown by a solid line, and the potential distribution in the case where a charge flows into the sensing channel 5 is shown by a broken line.
【0014】埋込チャネルとセンシングチャネルとのチ
ャネル分離領域の断面構造と、これに対応する電位分布
を図4(c),(d)に示した。このような信号電荷に
対応する表面チャネル6の電位分布変化により信号電荷
の検出が行われる。この構造の特徴は、センシングチャ
ネル5の表面に、センシングチャネルとは反対導電型で
あるp型表面チャネル6領域があるので、これにより表
面が電子についての表面チャネルとなることである。ま
た、センシングチャネル5とソース16およびドレイン
17間には、p- ウェル領域2が存在するので、埋込チ
ャネル3に対するチャネル分離帯としての役割をする。
この領域は、基板表面は反転されて表面チャネルとして
動作するので、チャネル分離帯の表面電位をセンシング
チャネル上の表面チャネル表面電位より深い電位になる
ように設計すれば、ソースからドレインへの電流の流れ
を防げることはない。The cross-sectional structure of the channel separation region between the buried channel and the sensing channel and the corresponding potential distribution are shown in FIGS. 4 (c) and 4 (d). The signal charge is detected by such a change in the potential distribution of the surface channel 6 corresponding to the signal charge. The feature of this structure is that the surface of the sensing channel 5 has a p-type surface channel 6 region having a conductivity type opposite to that of the sensing channel, so that the surface becomes a surface channel for electrons. Further, since the p − well region 2 exists between the sensing channel 5 and the source 16 and the drain 17, the p − well region 2 serves as a channel separation band for the buried channel 3.
In this region, the substrate surface is inverted and operates as a surface channel, so if the surface potential of the channel separation band is designed to be deeper than the surface channel surface potential on the sensing channel, the current from the source to the drain can be reduced. There is no stopping the flow.
【0015】[0015]
【発明の効果】以上説明したように、本発明によれば、
電子の電荷量を、電子をキャリアとするトランジスタに
より検出する素子が実現できる。前述した実施例におい
て信号電荷が電子である場合について説明したが、信号
電荷がホールである場合においても、同様に本発明を実
施できる。また、センシングチャネルまで信号を転送す
る素子もCCDのみならず低い転送損失によって電荷を
転送する素子であれば、本発明が目的とする効果を得る
事が可能となる。As described above, according to the present invention,
It is possible to realize an element in which the amount of charge of electrons is detected by a transistor having electrons as carriers. Although the case where the signal charge is an electron has been described in the above-described embodiments, the present invention can be similarly implemented when the signal charge is a hole. Further, if the element that transfers the signal to the sensing channel is not only the CCD but also the element that transfers the charge with a low transfer loss, the effect of the present invention can be obtained.
【図1】本発明の電荷検出素子の電荷が転送される方向
の素子断面構造図である。FIG. 1 is an element cross-sectional structural view of a charge detection element of the present invention in a direction in which charges are transferred.
【図2】図1の素子構造に相応するシリコン基板内の電
位分布図である。FIG. 2 is a potential distribution diagram in a silicon substrate corresponding to the device structure of FIG.
【図3】本発明の電荷検出素子の電荷が転送される方向
に垂直な方向の素子断面構造図である。FIG. 3 is an element cross-sectional structural view of a charge detection element of the present invention in a direction perpendicular to a direction in which charges are transferred.
【図4】本発明の電荷検出素子の部分的な断面構造及び
これに対応する電位分布図である。FIG. 4 is a partial cross-sectional structure of a charge detection element of the present invention and a potential distribution diagram corresponding thereto.
【図5】従来の電荷検出素子の断面構造図である。FIG. 5 is a sectional structural view of a conventional charge detection element.
1 n型基板 2 p- ウェル層 3 n型埋込チャネル層 4 ゲート酸化膜 5 センシングチャネル領域(n型) 6 表面チャネル領域(p型) 7 リセットドレイン(n+) 8,9,10 CCD転送電極 11 出力ゲート 12 フローティングゲート 13 リセットゲート 14 バイアスゲート 15 厚い絶縁層 16 ソース(n+) 17 ドレイン(n+)1 n-type substrate 2 p - well layer 3 n-type buried channel layer 4 gate oxide film 5 sensing channel region (n type) 6 surface channel region (p type) 7 reset drain (n + ) 8, 9, 10 CCD transfer Electrode 11 Output gate 12 Floating gate 13 Reset gate 14 Bias gate 15 Thick insulating layer 16 Source (n + ) 17 Drain (n + )
Claims (1)
型のフローティング表面チャネルが立体的に交差し、前
記電荷センシングチャネル内の電荷量に対応して前記フ
ローティング表面チャネル表面電位が変動する構造を有
する電荷検出素子において、 埋込型の電荷センシングチャネル表面にその電荷センシ
ングチャネルとは反対導電性の領域を有し、かつ前記フ
ローティング表面チャネルに形成されるソースとドレイ
ンのそれぞれと前記電荷センシングチャネルとの間に表
面が反転可能な埋込チャネル分離領域を有し、前記フロ
ーティング表面チャネルと前記電荷センシングチャネル
のキャリアが同一符号の電荷であることを特徴とする電
荷検出素子。1. A structure in which a buried type charge sensing channel and a surface type floating surface channel are three-dimensionally intersected, and the surface potential of the floating surface channel fluctuates according to the amount of charge in the charge sensing channel. In the charge detection element, a buried type charge sensing channel surface has a region having a conductivity opposite to that of the charge sensing channel, and each of the source and drain formed in the floating surface channel and the charge sensing channel. A charge detection element having a buried channel separation region whose surface is invertible therebetween, and carriers of the floating surface channel and the charge sensing channel are charges of the same sign.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP23926193A JP3375389B2 (en) | 1993-09-01 | 1993-09-01 | Charge detection element |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP23926193A JP3375389B2 (en) | 1993-09-01 | 1993-09-01 | Charge detection element |
Publications (2)
Publication Number | Publication Date |
---|---|
JPH07106551A true JPH07106551A (en) | 1995-04-21 |
JP3375389B2 JP3375389B2 (en) | 2003-02-10 |
Family
ID=17042138
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP23926193A Expired - Fee Related JP3375389B2 (en) | 1993-09-01 | 1993-09-01 | Charge detection element |
Country Status (1)
Country | Link |
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JP (1) | JP3375389B2 (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN102931202A (en) * | 2012-02-21 | 2013-02-13 | 华中师范大学 | Free charge pixel detector |
Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS61214465A (en) * | 1985-03-19 | 1986-09-24 | Matsushita Electric Ind Co Ltd | Solid-state image pickup device |
JPS6417469A (en) * | 1987-07-13 | 1989-01-20 | Toshiba Corp | Output detector for charge transfer element |
-
1993
- 1993-09-01 JP JP23926193A patent/JP3375389B2/en not_active Expired - Fee Related
Patent Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS61214465A (en) * | 1985-03-19 | 1986-09-24 | Matsushita Electric Ind Co Ltd | Solid-state image pickup device |
JPS6417469A (en) * | 1987-07-13 | 1989-01-20 | Toshiba Corp | Output detector for charge transfer element |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN102931202A (en) * | 2012-02-21 | 2013-02-13 | 华中师范大学 | Free charge pixel detector |
CN102931202B (en) * | 2012-02-21 | 2016-06-29 | 华中师范大学 | Free charge pixel detector |
Also Published As
Publication number | Publication date |
---|---|
JP3375389B2 (en) | 2003-02-10 |
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