KR100251688B1 - Amplification type solid state image pick-up device - Google Patents

Abstract

In the amplifying solid-state image pickup device of the present invention, a first gate region is formed around the source region as a photoelectric conversion region, and a second gate region is formed adjacent to the outside of the gate region, and accumulated in the first gate region. In an amplifying solid-state image pickup device for discharging signal charges through the second gate area, the center of the source area is displaced from the center of the pixel.

Description

Amplified solid state imaging device

Fig. 1A is a schematic plan view showing one example of the amplified solid-state image pickup device of the present invention (in a state in which the relationship between the horizontal and vertical directions is reversed, i.e., rotated 90 degrees).

Fig. 1B is an enlarged cross-sectional view of line B-B of the amplifying solid-state image pickup device shown in Fig. 1A.

Fig. 2 is a potential distribution diagram in the depth direction under a first gate area during signal charge accumulation operation in the amplifying solid-state image pickup device shown in Figs. 1A and 1B.

3A and 3B are potential distribution diagrams for explaining the excellent effect of the amplified solid-state image pickup device of the present invention, and FIG. 3A is a depth direction under the first gate area during reading in the amplified solid-state image pickup device shown in FIGS. 1A and 1B. Potential distribution of.

Fig. 3B is a potential distribution diagram under the first gate area at the time of reading in the conventional amplifying solid-state image pickup device.

Fig. 4A is a schematic plan view showing another embodiment of the amplified solid-state image pickup device of the present invention (with the relationship between the horizontal and vertical directions reversed, i.e., rotated 90 degrees).

4B is an enlarged cross-sectional view of the B-B line of the amplifying solid-state image pickup device shown in FIG. 4A.

Fig. 5 is a potential distribution diagram in a depth direction under a first gate area during signal charge accumulation operation in the amplifying solid-state image pickup device shown in Figs. 4A and 4B.

Fig. 6A is a schematic plan view showing a CMD type pixel (with the relationship between the horizontal and vertical directions reversed, i.e., rotated 90 degrees).

Fig. 6B is an enlarged cross-sectional view of the B-B line of the CMD type pixel of Fig. 6A.

Fig. 7 is a potential distribution diagram in a depth direction under a gate region of a CMD type pixel.

8A and 8B are schematic views for explaining the TGMIS type amplifying solid-state image pickup device, and Fig. 8A is a schematic plan view of a plurality of pixels.

Fig. 8B is an enlarged cross-sectional view of the B-B line of the TGMIS type amplifying solid-state image pickup device of Fig. 8A.

Fig. 9 is a potential distribution diagram in a depth direction under a first gate area during a signal charge accumulation operation in a TGMIS type amplifying solid-state image pickup device.

10 is a schematic cross-sectional view showing a BDMIS type amplifying solid-state image pickup device.

Fig. 11 is a schematic sectional view showing still another example of the amplifying solid-state image pickup device of the present invention.

12 is a schematic sectional view showing another example of an amplifying solid-state image pickup device of the present invention; And

Fig. 13 is a schematic sectional view showing still another example of the amplifying solid-state image pickup device of the present invention.

[Purpose of invention]

[Technical field to which the invention belongs and the prior art in that field]

The present invention relates to an amplifying solid-state image pickup device. More specifically, the present invention relates to an amplifying solid-state image pickup device having a low driving voltage and excellent pixel characteristics.

As the solid state imaging device, a charge coupled device (CCD) type is the mainstream, and is widely used in various fields. In a CCD solid-state imaging device, incident light is photoelectrically converted by a photodiode or a metal oxide semiconductor (MOS) diode, and the accumulated signal charge is introduced into a high sensitivity charge detector through a CCD transmission channel and converted into a voltage signal. For this reason, the CCD solid state image pickup device has advantages of high S / N ratio and high output voltage.

However, miniaturization and multiplexing of the solid state imaging device have progressed, and the pixel size has become smaller, and therefore the amount of charges that can be transferred to the CCD becomes smaller. For this reason, the fall of dynamic range becomes a serious problem. In addition, since the CCD is driven by several edges of the clock signal, the load capacity is large and the driving voltage is high. Therefore, there is also a problem in that power consumption is rapidly increased by the multi-pixel.

In order to cope with such a problem, an amplifying solid-state imaging device has been proposed in which a signal charge is amplified in a pixel without being read out and then read by a scanning circuit after amplifying the signal charge in the pixel. In this amplifying solid-state imaging device, there is no restriction on the amount of signals due to reading, and the dynamic range is advantageous over the CCD. Further, the amplifying solid-state imaging device is driven with respect to the horizontal / vertical scanning line of the pixel including the signal reading pixel, so that the driving voltage is lower and the power consumption is smaller than that of the CCD.

In general, a transistor is used for amplification in the pixel. The amplifying solid-state imaging device is classified into a silicon intensifier target (SIT) type, a bipolar type, a MOS type, and the like by the types of transistors used for amplification. Since the signal read scan circuit has a simple structure of the MOS type and is easy to manufacture, the MOS type is preferable. Therefore, since the amplifying transistor in the pixel is also the MOS type, both the scan circuit and the transistor are formed monolithically. The configuration of the entire MOS amplifying solid-state imaging device is very desirable.

Among amplifying solid-state imaging devices employing MOS transistors, a device including only a single MOS transistor in a pixel is preferable in terms of increasing pixel density. As such a type, pixels of a charge modulation device (CMD) type, a floating gate amplifier (FGA) type, and a bulk charge modulation device (BCMD) type have been reported.

6A and 6B show CMD type pixels. This pixel was described in Nakamura et al. "Gate accumulation MOS phototransistor image sensor" in the International Association of Television Association p57 in 1986. Hereinafter, the general structure of the pixel will be described.

As shown in Fig. 6B, an n-type well layer 16 is formed as a buried channel on the p-type semiconductor substrate 15, and a gate is formed on the n-type well layer 16 through an insulating film (e.g., an oxide film; not shown). The electrode 17 is formed. The n-type well layer 16 is formed with a source 18 and a drain 19 having a high concentration n layer (n ⁺ layer) separated by the gate electrode 17.

When the above-described CMD type pixel is applied to a two-dimensional image sensor, as shown in Fig. 6A, the gate electrode 17 (with the relationship between the horizontal and vertical directions reversed, i.e., rotated by 90 degrees), Horizontal rows are common, VG (i), VG (i + 1),... It is connected to the clock line marked with,. In addition, each vertical row of the source 18 has a common signal line VS (i), VS (i + 1),... Is connected to. On the other hand, the drain 19 is applied with a voltage VD around the periphery of each pixel.

Next, the operation of the CMD type pixel will be described with reference to FIG. First, the gate voltage applied to the gate electrode 17 during signal accumulation is lowered to VL, and signal charges (holes) generated by photoelectric conversion are accumulated at the interface between the semiconductor and the insulating film. Electrons flow out through the drain 19 in this period. Next, at the time of signal reading, the gate voltage is increased to the intermediate voltage VM. As a result, since the current between the drain 19 and the source 18 changes in correspondence with the amount of signal charge, the value thereof is read out as an output signal. At this time, the current of another pixel on the same signal line is not detected because the gate electrode 17 is at the VL level.

During pixel reset, the signal charge is cleared and prepared for the next signal accumulation. By raising the gate voltage to VH, as shown in Fig. 7, a potential gradient monotonously decreasing (reducing) in the depth direction is obtained. As a result, signal charges accumulated in the semiconductor / insulating film interface are discharged to the semiconductor substrate 15 directly below it, as indicated by broken lines in FIG. 6B.

In the CMD type pixel, there is a problem that it is difficult to realize an amplifying solid-state imaging device having a low driving voltage. The reason for this is that in the CMD type pixel, the concentration of the buried channel must be increased in order to increase the accumulation density of the signal charges. When the buried channel concentration is increased, the gate voltage during the reset operation becomes very high.

As an amplifying solid-state imaging device which solves the above problems, for example, there is a TGMIS (Twin Gate MOS Image Sensor) type amplifying solid-state imaging device proposed by the applicant in Japanese Patent Application No. 94-303953. This TGMIS amplification type solid-state image pickup device photoelectrically converts light incident on a gate region of a MOS transistor formed on a semiconductor substrate, and changes the potential change of the MOS transistor in the apparatus according to the signal charge accumulated in the gate region. The structure which outputs is adopted.

Referring to Figs. 8A and 8B, a TGMIS type amplifying solid-state imaging device will be described. As shown in FIG. 8B, an n-type well layer 23 is formed on or near the p-type semiconductor substrate 20, and the first gate electrode (eg, an oxide film) is formed on the well layer 23. 21) is formed. The first gate electrode 21 constitutes a first gate region serving as a photoelectric conversion region. In the well layer 23, a source (source region) 24 and a drain (drain region) 25 are formed. The first gate electrode 21 constitutes a MOS transistor. The source 24 and the drain 25 are of high concentration n layers (n ⁺ layers).

In this specification, the terms "source" and "source area", and "drain" and "drain area" are used as required by the contents.

In addition, on the semiconductor substrate 20, a second gate electrode 22 is formed through the insulating film adjacent to the first gate electrode 21. The second gate electrode constitutes a second gate region. As shown in Fig. 8A (with the relationship between the horizontal and vertical directions reversed, i.e. rotated 90 degrees), a first gate region serving as a photoelectric conversion region is formed around the source 24 around it. do. The horizontal rows of the first gate electrode 21 are common to VA (i), VA (i + 1),... It is connected to the clock line marked with,. The horizontal rows of the second gate electrodes 22 are commonly VB (i), VB (i + 1),... It is connected to the clock line marked with,. Each vertical row of the source 24 has a common VS (j), VS (j + 1),... It is connected to the signal line marked with,. A drain voltage VD is applied to the drain 25 in the periphery of each pixel.

The reset operation in the apparatus configured as described above will be described. As used herein, "reset operation" means discharging signal charge. In the apparatus having such a configuration, signal charges (holes) generated by photoelectric conversion are accumulated in the semiconductor / insulating film interface of the first gate region. The signal charges flow out to the semiconductor substrate 20 through the second gate region, thereby removing the accumulated signal charges. In this way, the reset operation is executed. According to the TGMIS type amplifying solid-state imaging device, a reset channel is formed on or near the surface of the semiconductor substrate 20 directly below the second gate electrode 22, and a predetermined voltage is applied to the second gate electrode 22. By applying the potential barrier slightly smaller, the signal charge is simply reset. For this reason, the gate voltage at the time of the reset operation can be reduced. Therefore, according to the TGMIS type amplifying solid-state imaging device, the problem of the CMD type pixel can be solved.

However, the following problems exist in the TGMIS type amplifying solid-state imaging device. In the TGMIS type amplifying solid-state imaging device, as shown in Fig. 8A, the source region 24 is formed in a square in plan view, and as shown in Fig. 8B, its center coincides with the center 7 of the pixel. One end of the drain 25 is disposed adjacent to one end of the photoelectric conversion region under the first gate electrode 21. For this reason, an interval between the source region 24 and the drain 25 of the pixel, and an interval between the source region 24 and the drain 25 of the pixel side adjacent to the pixel side (that is, adjacent to the second gate electrode 22). Due to the difference, as shown in Fig. 9, the potential of the semiconductor surface of the first gate region is nonuniform in the pixel.

9 will be described in detail below. Fig. 9 is a potential distribution diagram 26 ', 27' in the depth direction in the state where no signal charge is accumulated in the signal charge accumulation operation. As shown in FIG. 9, the potential distribution 26 under the first gate electrode 21 between the source 24 and the second gate electrode 22 and the first between the source 24 and the drain 25. The potential distribution 27 'under the gate electrode 21 is different. For example, in the amplifying solid-state image pickup device, when signal charges are accumulated, a low gate voltage VA (L) =-3.0V is applied to the first gate electrode 21 and an intermediate voltage is applied to the second gate electrode 22. Apply VB (M) = 1.0V. In this case, when no signal charge is accumulated, the surface potential under the first gate electrode 21 between the source 24 and the second gate electrode 22 is the first between the drain 25 and the source 24. 0.2V lower than the surface potential under the gate electrode 21.

When signal charges (holes) are generated by light irradiation, the signal charges tend to be collected at low potentials. Thus, in the TGMIS type amplifying solid-state imaging device, as described above, the signal charges are made with the source 24. It is easy to accumulate under the first gate electrode 21 between the two gate electrodes 22. However, when the signal amount corresponding to the signal charge amount is detected as the potential of the source 24, the maximum value of the potential under the first gate electrode 21 is detected. Therefore, in this apparatus, the potential maximum under the first gate electrode 21 between the drain 25 and the source 24 is detected.

In this way, when the potential distribution under the first gate electrode 21 is not uniform, there is the following problem. When the amount of signal charge accumulated in the pixel is small, under the first gate electrode 21 between the drain 25 and the source 24, it is possible to obtain a change in potential in the semiconductor that properly reflects the amount of signal charge accumulated in the entire pixel. Therefore, the sensitivity to the signal charge amount becomes low. Therefore, in the TGMIS type amplifying solid-state imaging device, it is difficult to obtain a sensor output (source potential) corresponding to the signal charge, which causes insufficient detection accuracy.

In addition, even in such an amplifying solid-state imaging device, the demand for multiplexing and miniaturization increases, and it is necessary to reduce the pixel size. However, when the pixel size is reduced, the drain 25 is closer to the photoelectric conversion region. For this reason, the influence of the drain voltage is increased, and the potential value under the first gate electrode 21 is increased. Therefore, in the compact amplification solid-state imaging device, the potential value becomes closer to the drain voltage, resulting in a problem that the dynamic range is lowered.

The amplifying solid-state imaging device of the present invention includes a source region, a first gate region surrounding the source region and serving as a photoelectric conversion region, and a second gate formed adjacent to the first gate region on a side opposite the source region. A region, the signal charges accumulated in the first gate region through the second gate region; The center of the source region is displaced from the center of the pixel.

In one embodiment of the present invention, the first gate region is a portion of a transistor formed on or near the surface of the semiconductor substrate, and the transistor outputs a change in the electrical signal in accordance with the accumulation amount of the signal charge generated by the photoelectric conversion; The second gate region is formed on a surface of the semiconductor substrate; The reset of the signal charges in the second gate area is performed inside the semiconductor substrate.

In another embodiment of the present invention, the first gate region is a portion of a transistor formed on or near the surface of the semiconductor substrate, and the transistor outputs a change in the electrical signal in accordance with the accumulation amount of the signal charge generated by the photoelectric conversion; The second gate region is formed on a surface of the semiconductor substrate; The reset drain is provided on or near the surface of the semiconductor substrate at an end adjacent to the second gate region; Reset of the signal charges is performed in the reset drain via the second gate region; The change in the electrical signal is output by the transistor in accordance with the change generated in the current flowing between the source region and the semiconductor substrate, and the semiconductor substrate acts as a drain.

In another embodiment of the present invention, the first gate region is a part of a transistor formed on or near the surface of the semiconductor substrate, and the transistor outputs a change in the electrical signal in accordance with the accumulation amount of the signal charge generated by the photoelectric conversion. ; The second gate region is formed on a surface of the semiconductor substrate; The reset drain is provided on or near the surface of the semiconductor substrate in the second gate region.

In another embodiment of the present invention, the field blocking portion is formed in the vicinity of the surface of the semiconductor substrate on the side of the second gate region opposite to the portion adjacent to the first gate region.

In another embodiment of the present invention, the center position of the source region is displaced from the center of the pixel toward the second gate region.

In another embodiment of the present invention, the source region is shaped such that the distance between the center of the pixel and the center of the source region adjacent to the second gate region is longer than the distance between the center of the pixel and the opposite end of the source region. Have

Accordingly, the present invention provides the following advantages: (1) providing an amplifying solid-state image pickup device capable of obtaining a sensor output corresponding to a signal charge and having an excellent detection accuracy, and (2) having a good dynamic range and thus Provided are an amplifying solid-state image pickup device suitable for multiplexing and miniaturization, and (3) providing an amplifying solid-state image pickup device with low driving voltage and excellent pixel characteristics.

[Configuration and Function of Invention]

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the drawings, but the present invention is not limited thereto.

Example 1

Fig. 1A is a schematic plan view of a preferred example of the amplifying solid-state image pickup device of Embodiment 1 of the present invention (the relationship between the horizontal direction and the vertical direction is reversed, i.e., rotated by 90 °), and Fig. 1B is the BB of Fig. It is an enlarged cross-sectional view of the line.

As shown in FIG. 1B, a first gate electrode (gate region) 2 and a second gate electrode (gate region) 3 are formed on the p-type semiconductor substrate 1 through a gate insulating film (not shown). have. One end of the second gate electrode 3 is adjacent to the first gate electrode 2. An n-type well layer 4 is formed on the surface side of the semiconductor substrate 1 under the first gate electrode 2, and a source (source region) 5 and a drain (drain region) 6 are formed in the well layer 4. And a first gate electrode 2, a source and a drain MOS transistor, and an n ⁺ diffusion layer.

As shown in FIG. 1A, a first gate region serving as a photoelectric conversion region is formed around the source 5. Each horizontal row of the first gate electrode 2 has a common VA (i), VA (i + 1),... It is connected to the clock line marked with,. The horizontal rows of the second gate electrodes 3 are common to VB (i), VB (i + 1),... It is connected to the clock line marked with,. The vertical rows of the source 5 are commonly VS (j), VS (j + 1),... It is connected to the signal line VS (j) denoted by,. A drain voltage VD is applied to each drain 6 around each pixel.

The material of the semiconductor substrate 1 is Si, and the conditions such as the substrate concentration are as follows.

Substrate Concentration: 1 × 10 ¹⁵ cm ^-3

Well layer concentration: 3 × 10 ¹⁵ cm ^-3

Well layer thickness: 1.5㎛

Gate insulating film thickness: 80nm

The material of the gate electrode and the gate electrode is not particularly limited, but a gate electrode configuration and / or a material of the gate electrode which is usually used in an amplifying solid-state imaging device is employed.

As shown in FIG. 1B, the vertical center 8 of the source region 5 is the direction of the second gate electrode 3 from the center of the pixel (ie, the center position of the first gate electrode 2) 7. to Position is displaced by. In contrast, in the amplified solid-state imaging device used in a conventional amplified solid-state imaging device (for example, the TGMIS amplified solid-state imaging device first proposed by the present applicant as described above), the vertical center of the source region 5 is Coincides with the center position 7 of the pixel.

Displacement ( ) Varies depending on the use of the device, the size of the pixel, the applied voltage, and the like. For example, in the present embodiment, when the vertical center 8 of the source region coincides with the center position 7 of the pixel, the ends and the drain region 6 of the source region 5 and the second gate electrode 3 are arranged. The distance from the end of is 1.5 μm, and in this case (in accordance with the other conditions described above), the displacement amount ( ) Is 0.4 μm.

In the amplified solid-state image pickup device having such a configuration, when light hυ is incident through the first gate electrode 2, electron-hole pairs are generated by photoelectric conversion. Electrons flow out to the drain 6, and holes accumulate in the semiconductor / insulation film interface of the well layer 4, and become signal charges. At this time, a predetermined constant voltage (5 V in this embodiment) is applied to the drain 6.

When signal charges are accumulated, the potential of the well layer 4 changes in correspondence with the accumulated signal charges. In the amplifying solid-state image pickup device of the present invention, the change amount is read as a potential change of the source 5, and output signal is converted. On the other hand, the discharge of the signal charges (i.e., the reset operation) sends the signal charges to the semiconductor substrate 1 along the path indicated by the broken arrow in Fig. 1B by lowering the potential barrier under the second gate electrode 3. Is achieved.

2, the center 8 of the source region 5 is located at the center position 7 of the pixel. The effect by being located at the displaced position by this will be described. For simplicity, a relatively low gate voltage (VA (L) =-3.0 V) is applied to the first gate electrode 2 during signal charge accumulation, and an intermediate voltage VB ( A case of applying M) = 1.0 V) will be described.

When the source 5 is installed near the center 7 of the pixel (ie, when the center 8 of the source 5 coincides with the center 7 of the pixel: for example, FIGS. 8A and FIG. In the case of the 8b amplified solid-state image pickup device) as described above, when no signal charge is present, the semiconductor surface potential under the first gate electrode 2 between the source 5 and the second gate electrode 3 is The voltage is 0.2V lower than that of the semiconductor surface potential under the first gate electrode 2 between the drain 6 and the source 5. In other words, the semiconductor surface potential under the first gate electrode 2 becomes nonuniform. For this reason, as described above, variations in the semiconductor potential that properly reflect the amount of signal charges accumulated in the entire pixel cannot be obtained, and the sensitivity to the amount of signal charges is low.

On the other hand, as in the present embodiment, the center 8 of the source 5 in the pixel is in the direction of the second gate electrode 3 from the center 7 of the pixel. In the case where the signal charge is displaced by, the potential of the semiconductor surface under the first gate electrode 2 between the source 5 and the second gate electrode 3 is reduced to the second gate electrode 3 when no signal charge is accumulated. Due to the influence of the constant applied voltage (5.0V) of the adjacent drain 6, it becomes as deep as 0.1V. That is, since the source 5 is affected as the source 5 approaches the drain 6 adjacent to the second gate electrode 3, the potential becomes 0.1V deeper.

On the other hand, the potential of the semiconductor under the first gate electrode 2 between the drain 6 and the source 5 is less affected by the increase in the distance between the source 5 and the drain 6, 0.1V than conventional As shallow as possible.

Therefore, the center 8 of the source region 5 is directed toward the second gate region 3. The potential distribution under the first gate electrode 2 between the source 5 and the second gate electrode 3 by positioning the displacement door as much as (ie, with the optimum displacement according to the use of the device, the pixel size, and the applied voltage). 26, and the difference between the potential distribution 27 under the first gate electrode 2 between the source 5 and the drain 6 (as shown in FIG. 2) becomes smaller compared to the conventional apparatus shown in FIG. do. In other words, the overall potential distribution 26 becomes deep while the overall potential distribution 27 becomes shallow. For this reason, the difference of the semiconductor surface potential which exists in the conventional apparatus shown in FIG. 9 is eliminated. As a result, as shown by the symbol? In FIG. 2, the semiconductor surface potential under the first gate electrode 2 between the source 5 and the second gate electrode 3, and the source 5 and drain 6 The surface potential of the semiconductor under the first gate electrode 2 in between coincides with each other. For this reason, according to this embodiment, the sensor output corresponding to the amount of signal charge accumulated in the whole pixel can be obtained, and the device excellent in the detection accuracy is obtained.

The vertical center of the source (5) (8) In excess of the optimum displacement (0.4 μm in this embodiment) and closer to the second gate electrode 3, the first gate electrode between the source 5 and the second gate electrode 3. As the semiconductor surface potential under 2) becomes deeper and the semiconductor surface potential under the first gate electrode 2 between the source 5 and the drain 6 becomes thinner, a difference in surface potential is generated. Therefore, the optimum amount corresponding to the use of the device, the size of the pixel, and the like ( It is important to displace the vertical center 8 of the source 5 from the pixel center 8 by.

Next, by comparing FIG. 3A and FIG. 3B, the advantages of the amplifying solid-state imaging device of the present invention in the read operation will be described. Fig. 3A is a potential distribution diagram in the depth direction under the first gate area at the time of reading in the amplified solid-state image pickup device shown in Figs. 1A and 1B of the present invention, and Fig. 3B is a conventional amplification type solid-state image pickup device. In the depth direction under the first gate region at the time of reading. In Fig. 3A, reference numeral 30 denotes a potential distribution under the first gate electrode 2 between the source 5 and the second gate electrode 3, and reference numeral 31 denotes a potential distribution between the source 5 and the drain 6; The potential distribution under one gate electrode 2 is shown. In FIG. 3B, the potential distributions 30 'and 31' respectively correspond to the potential distributions 30 and 31 in FIG. 3A.

In this embodiment, in the read operation, the intermediate voltage VA (M) = 0.0V is applied to the first gate electrode 2 and the high voltage VB (H) = 5.0V is applied to the second gate electrode 3. do. The value (ie, the maximum value) of the deepest point of the potential of the semiconductor under the first gate electrode 2 is detected as the source voltage.

When it is desirable to reduce the voltage applied to the drain 6 for the purpose of lowering the driving voltage, lowering the power consumption, and the like of the amplifying solid-state image pickup device, the detectable source potential cannot exceed the drain voltage. The potential under the electrode 2 must be reduced to widen the dynamic range defined as the amplitude of the voltage that can be read out. As apparent by comparing the potential distributions of FIGS. 3A and 3B, the center 8 of the source region 5 is moved from the center 7 of the pixel to the second gate electrode 3. By displacing by this (by displacing 0.4 mu m in this embodiment), the value (maximum value) of the deepest point of the semiconductor potential distribution under the first gate region can be reduced. For this reason, when a voltage of 5.0 V is applied to the drain 6, the amplifying solid-state image pickup device of the present invention can improve the dynamic range by 0.1 V as compared with the conventional device shown in Fig. 3B.

Example 2

Fig. 4A is a schematic plan view of another preferred embodiment of the core of the present invention (state in which the relationship between the horizontal and vertical directions is reversed, i.e. rotated by 90 °), and Fig. 4B is an enlarged sectional view of the line B-B in Fig. 4A. For the sake of simplicity, parts corresponding to the first embodiment are denoted by the same reference numerals and description thereof will be omitted.

In the amplifying solid-state image pickup device of this embodiment, as shown in Fig. 4A, the source region 5 in the pixel is formed in a rectangle (as opposed to a square), and the source region 5 in the pixel center 7 is formed. The distance to the end portion on the side of the second gate region 3 is longer than the distance from the pixel center 7 to the end portion on the opposite side of the source region 5. As a result, the potential of the semiconductor surface under the first gate electrode is made uniform.

Specifically, in the present embodiment, the width of the first gate region 2 between the source region 5 and the second gate region 3 is shortened to 0.8 µm from 1.5 µm, and instead, the source region ( The end portion at the side of the second gate region 3 in 5) was elongated to change the shape of the source region 5 from the above-described square (see Fig. 8A) to a rectangle.

According to the device of this embodiment, since the second gate region 3 side of the source region 5 is long, the second gate region side of the source region 5 has a drain 6 adjacent to the second gate region 3. ) Will be affected. For this reason, as shown in Fig. 5, the potential distribution 28 of the semiconductor surface under the first gate region 2 between the source region and the second gate region 3 is deepened, similarly to the first embodiment, The difference in surface potential that exists when the center of the source region 5 coincides with the pixel center 7 is eliminated. Thus, as shown in Fig. 5, the surface potential can be made uniform in the first gate region (indicated by reference numeral 29 in Fig. 5 is the semiconductor surface potential distribution under the first gate region between the source region and the drain region). For this reason, similarly to the first embodiment, the sensor output corresponding to the amount of signal charge accumulated in the entire pixel can be obtained, thereby obtaining an element having excellent detection accuracy.

The shape of the source region 5 is not limited to rectangular, and may be appropriately changed according to the use of the device, the pixel size, and the like. That is, the distance from the pixel center 7 to the end portion of the second gate region 3 side of the source region 5 is the pixel center 7 so that the semiconductor surface potential under the first gate electrode 2 is uniform. It may be longer than the distance from the end of the source region 5 to the opposite side. Therefore, any shape other than square having the pixel center 7 as the shape center can be widely selected in this embodiment.

Example 3

The present invention is applicable not only to the TGMIS amplified solid-state image pickup devices (Figs. 1A, 1B and 4A, 4B) described in Examples 1 and 2, but also to the amplified solid-state image pickup devices having other structures. This embodiment and the following Examples 4 and 5 will be described in detail.

This embodiment describes the application of the present invention to a BDMIS (Bulk Drain MOS Image Sensor) type solid state imaging device which was first proposed in Japanese Patent Application No. 95-51641.

Fig. 10 is a schematic plan view showing an example of a BDMIS type solid state imaging device. In the device, signal charges generated by incident light (electrons in this embodiment) are accumulated below the first gate electrode VA, and the potential under the first gate electrode VA changes depending on the accumulation situation. As a result, the current (holes in this embodiment) flowing between the source VS and the drain VD changes, and the current change is output to the outside as a signal.

Compared with the TGMIS type element, the BDMIS type element is characterized by (a) the semiconductor substrate 100 acting as a drain VD; (b) The signal charges are discharged from the surface of the semiconductor substrate 100 to the reset drain VR through the second gate electrode VB.

10 shows an example in which the signal charge is electrons, but when the signal charge is holes, the conductivity of the semiconductor layer 104 and the p + layer 100 may be reversed.

Fig. 11 is a schematic sectional view of an example in which the present invention is applied to a BDMIS type solid state image pickup device. For convenience, only the cross section of one pixel portion is shown. In this element, the center of the source region is from the center of the pixel (ie, the center of the first gate electrode VA) to the left and in the direction of the second gate electrode VB which is a signal reset gate. Displaced by In other words, the source region 5 is displaced so that the potential under the first gate electrode VA is uniform in the signal charge accumulation portion of the pixel.

Displacement ( Is converted according to the use of the device, the size of the pixel, the applied voltage, and the like. For example, in this embodiment, the distance between the center and the end of the first gate electrode VA is 1.5 占 퐉, and the appropriate displacement amount (in accordance with the other conditions described above) in this case ( ) Is 0.2 μm.

In the BDMIS type solid state image pickup device, signal reading is performed by flowing a current through the third gate electrode VC to the semiconductor substrate 100 (acting as a drain). As is apparent from Fig. 11, this embodiment is effective when applied to a BDMIS type solid state image pickup device of the type in which the read current flows only in one direction along the surface of the semiconductor substrate 100 and finally flows to the substrate 100 side.

Alternatively, similarly to Embodiment 2, the same applies to Embodiments 4 and 5 described later, in which the potential under the first gate electrode VA can be made uniform in the signal charge accumulation portion of the pixel by changing the shape of the source region. to be.

Example 4

12 is a schematic sectional view showing still another example of the amplifying solid-state image pickup device of the present invention. In this embodiment, the present application will be described in the case where the present invention is applied to a TGMIS type solid-state image pickup device of the surface reset type first proposed in Japanese Patent Application No. 96-19199.

As shown in Fig. 12, the difference between the element of the present embodiment and the TGMIS type solid-state image pickup device first proposed in Japanese Patent Application No. 94-303953 is that the reset drain VR is formed on the surface of the substrate 100 or the same. It is installed nearby. In the device, the signal charge accumulated on the lower side of the first gate electrode VA is reset on or near the surface of the substrate 100 on the lower side of the second gate electrode VB adjacent to the first gate electrode VA. A drain VR is provided, and signal charges are discharged to the reset drain VR through the second gate electrode VB.

In this element, the center of the source region VS is at the center of the signal charge storage portion (the center of the first gate electrode VA). As a result, it is displaced toward the second gate electrode VB. For this reason, the potential of the first gate electrode VA becomes uniform at the signal charge accumulation portion of the pixel. In this embodiment, the distance between the center and the end of the first gate electrode VA is 1.5 占 퐉, and the appropriate displacement amount according to the other conditions described above in this case ( ) Is 0.4 µm. As described above, the displacement amount ( ) Is appropriately changed depending on the use of the device, the size of the pixel, the applied voltage, and the like.

Example 5

Fig. 13 is a schematic cross-sectional view showing still another example of the amplifying solid-state scratching device of the present invention. In this embodiment, the present application will be described in the case where the present invention is applied to a TGMIS type solid state image pickup device in which an electric field blocking means is provided on or near the substrate surface, which was first proposed in Japanese Patent Application No. 96-19200.

As shown in Fig. 13, the difference between the device of this embodiment and the TGMIS type solid-state imaging device first proposed in Japanese Patent Application No. 94-303953 is that part of the second gate area adjacent to the first gate area. The field blocking means 105 (for example, a trench structure) is provided on the surface of or near the semiconductor substrate 100 on the opposite side.

By providing the electric field blocking means 105, a function is provided to prevent the occurrence of a ridge that interferes with the reset operation of the signal in the middle of the potential distribution along the depth direction on the surface of the substrate 100. Therefore, the electric field blocking means 105 can discharge the signal charges to the substrate 100 side.

In this element, the center of the source region VS is at the center of the signal charge storage portion (the center of the first gate electrode VA). As a result, it is displaced toward the second gate electrode VB, so that the potential under the first gate electrode VA becomes uniform in the signal charge accumulation portion of the pixel.

As described above, in the conventional TGMIS type amplifying solid-state image pickup device, the source region is provided near the center of the pixel (that is, the center of the source region coincides with or almost coincides with the center of the pixel). Since the portion between the source region and the second gate region under the first gate region is further separated from the drain than the portion of the first gate electrode between the drain and the source region, the influence of the voltage applied to the drain is relatively small. . As a result, the potential of the semiconductor surface under the first gate region between the source region and the second gate region becomes low, thereby accumulating signal charges (holes). In other words, the potential of the semiconductor surface under the first gate electrode becomes uneven. For this reason, fluctuations in the potential of the semiconductor which properly reflect the amount of signal charge accumulated in the entire pixel cannot be obtained, and the sensitivity to the amount of signal charge becomes low.

In contrast, according to the amplifying solid-state imaging device of the present invention, the center 8 of the source region is moved from the center 7 of the pixel. By displacing as much as possible, the potential of the semiconductor surface under the first gate region can be made uniform. This is accomplished by the following mechanism: a portion (one end) of the source region is brought close to the second gate region, so that the potential of the semiconductor surface under the first gate region between the source region and the second gate region is in the drain of the adjacent pixel. The surface potential is changed in a direction to solve the nonuniformity by being deepened by the influence of the applied voltage (influence according to the proximity to the second gate region).

Thus, by optimizing the distance between the source region and the second gate region, the surface potential under the first gate region (first gate electrode) between the source region and the second gate region and the first gate between the drain region and the source region The surface potential under an area can be made the same. Therefore, the potential of the semiconductor surface under the first gate region can be made uniform.

[Effects of the Invention]

According to the present invention, there are two means for displacing the source region at the center of the pixel, for example: (i) displacing the center position of the source region in the direction of the second gate region from the center of the pixel; And / or (ii) the source region is formed such that the distance from the pixel center to the end portion of the second gate region side of the source region has a shape longer than the distance from the pixel center to the end portion on the opposite side of the source region.

As a result, signal charges are uniformly accumulated under the first gate region in the pixel, whereby the potential of the semiconductor reflecting the amount of signal charge accumulated in the entire pixel can be obtained. Therefore, the sensitivity of the sensor output with respect to the accumulated signal charge amount (for example, holes) can be improved, and an element having excellent detection accuracy can be obtained.

On the other hand, when a part (one end) of the source region is far from the drain region, the influence of the voltage applied to the drain in the semiconductor under the first gate region between the source region and the drain region is weakened, so that the potential of the potential in the substrate depth direction is reduced. The maximum value becomes small. For this reason, the potential of the MOS transistor detected as the source potential becomes small. Thus, the range that can be detected at the source potential cannot be higher than the voltage applied to the drain. When only a constant low voltage is applied to the drain and the detectable voltage is limited to the constant low voltage, according to the present invention, by displacing the center of the source region from the center of the pixel, that is, part of the source region (one end) By disposing the at the drain region far away, the dynamic maximum defined by the amplitude of the voltage that can be read out can be further improved by reducing the potential maximum in the substrate.

Application of the amplifying solid-state imaging device of the present invention having the above advantages to an amplifying solid-state imaging device makes it possible to realize an amplifying solid-state imaging device with low driving voltage, low power consumption, and excellent device characteristics.

Various other modifications may be made to those skilled in the art without departing from the spirit and scope of the invention. Accordingly, the scope of the appended claims should not be limited to the above description, but should be construed broadly.

Claims (15)

A source region, a first gate region surrounding the source region and serving as a photoelectric conversion region, and a second gate region formed adjacent to the first gate region on a side facing the source region, wherein the second gate region is formed on the first gate region. Discharge the accumulated signal charges through the second gate area; An amplifying solid-state image pickup device in which the center of the source region is displaced from the center of the pixel. The semiconductor device according to claim 1, wherein the first gate region is a part of a transistor formed on or near the surface of the semiconductor substrate, and the transistor outputs a change in an electrical signal in accordance with the accumulation amount of signal charge generated by photoelectric conversion; The second gate region is formed on a surface of the semiconductor substrate; An amplifying solid-state image pickup device in which the reset of the signal charges in the second gate area is performed inside the semiconductor substrate. The semiconductor device according to claim 1, wherein the first gate region is a part of a transistor formed on or near the surface of the semiconductor substrate, and the transistor outputs a change in an electrical signal in accordance with the accumulation amount of signal charge generated by photoelectric conversion; The second gate region is formed on a surface of the semiconductor substrate; The reset drain is provided on or near the surface of the semiconductor substrate at an end adjacent to the second gate region; Reset of the signal charge is performed in the reset drain via the second gate region; And the change of the electrical signal is output by the transistor in accordance with the change generated in the current flowing between the source region and the semiconductor substrate, wherein the semiconductor substrate acts as a drain. The semiconductor device according to claim 1, wherein the first gate region is part of a transistor formed on or near the surface of the semiconductor substrate, and the transistor outputs a change in the electrical signal in accordance with the accumulation amount of the signal charge generated by the photoelectric conversion; The second gate region is formed on a surface of the semiconductor substrate; And the reset drain is provided on or near the surface of the semiconductor substrate in the second gate region. 2. An amplifying solid-state image pickup device according to claim 1, wherein an electric field blocking portion is formed in and near the surface of the semiconductor substrate on the side of the second gate region opposite to the portion adjacent to the first gate region. The amplifying solid state image pickup device according to claim 1, wherein the center position of the source region is displaced from the center of the pixel toward the second gate region. The amplifying solid state image pickup device according to claim 1, wherein the center position of the source region is displaced from the center of the pixel toward the second gate region. 4. The amplifying solid-state image pickup device according to claim 3, wherein the center position of the source region is displaced from the center of the pixel toward the second gate region. The amplifying solid-state image pickup device according to claim 4, wherein the center position of the source region is shifted from the center of the pixel toward the second gate region. 6. The amplifying solid state image pickup device according to claim 5, wherein the center position of the source region is displaced from the center of the pixel toward the second gate region. The amplification type of claim 1, wherein the source region has a shape in which a distance between a center of a pixel and a center of a source region adjacent to the second gate region is longer than a distance between a center of the pixel and an opposite end of the source region. Solid state imaging device. The amplification type of claim 2, wherein the source region has a shape in which a distance between a center of a pixel and a center of a source region adjacent to the second gate region is longer than a distance between a center of the pixel and an opposite end of the source region. Solid state imaging device. The amplification type of claim 3, wherein the source region has a shape in which a distance between a center of a pixel and a center of a source region adjacent to the second gate region is longer than a distance between a center of the pixel and an opposite end of the source region. Solid state imaging device. The amplification type of claim 4, wherein the source region has a shape in which a distance between the center of the pixel and the center of the source region adjacent to the second gate region is longer than the distance between the center of the pixel and the opposite end of the source region. Solid state imaging device. The amplification type of claim 5, wherein the source region has a shape in which a distance between the center of the pixel and the center of the source region adjacent to the second gate region is longer than the distance between the center of the pixel and the opposite end of the source region. Solid state imaging device.