JPH0697322A - Resin-sealed semiconductor device - Google Patents

Resin-sealed semiconductor device

Info

Publication number
JPH0697322A
JPH0697322A JP4243886A JP24388692A JPH0697322A JP H0697322 A JPH0697322 A JP H0697322A JP 4243886 A JP4243886 A JP 4243886A JP 24388692 A JP24388692 A JP 24388692A JP H0697322 A JPH0697322 A JP H0697322A
Authority
JP
Japan
Prior art keywords
island
package
semiconductor element
mount
resin
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP4243886A
Other languages
Japanese (ja)
Inventor
Noriyasu Kawamura
法靖 川村
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Priority to JP4243886A priority Critical patent/JPH0697322A/en
Publication of JPH0697322A publication Critical patent/JPH0697322A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L24/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49503—Lead-frames or other flat leads characterised by the die pad
    • H01L23/49513—Lead-frames or other flat leads characterised by the die pad having bonding material between chip and die pad
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/2901—Shape
    • H01L2224/29011—Shape comprising apertures or cavities
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/2919—Material with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8319—Arrangement of the layer connectors prior to mounting
    • H01L2224/83194—Lateral distribution of the layer connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)

Abstract

PURPOSE:To provide a resin-sealed semiconductor device in which the generation of cracks going through the inside of a package is suppressed to improve the reliability thereof. CONSTITUTION:Since the fixing strength of a semiconductor element 16 to the mount face 15 of to is so formed as to be smaller than the adhering strength between the sealing resin materials forming a package 18 and the mount rear face 19 of the island 14, even when moisture is absorbed to the inside of the package 18 and condensed there and vaporized at high temperature effected at the time of mounting, the vapor pressure is effected on the fixing part between the mount face 15 of the island 14 which is small in a fixing strength and the semiconductor element 16. Separation is brought about in the fixing part to form an air gap by which the pressure is absorbed, and however, the semiconductor element 16 and the island 14 act as structural materials, so that the concentration of a stress at the end part of the island 14 is relaxed and the generation of cracks reaching the outer surface of the package 18 is suppressed to greatly improve reliability of the device.

Description

【発明の詳細な説明】Detailed Description of the Invention

【０００１】[0001]

【産業上の利用分野】本発明は、樹脂封止半導体装置に
関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a resin-sealed semiconductor device.

【０００２】[0002]

【従来の技術】半導体素子の高集積化、実装の高密度化
にともない表面実装型の樹脂封止半導体装置が広く用い
られるようになってきている。このような樹脂封止半導
体装置は、リードや枠部等と共にリードフレームに設け
られたアイランドのマウント面に半導体素子を搭載し、
その後封止樹脂材料による成形によって所定形状のパッ
ケージを形成し、リードの成形及びリードフレームの枠
部からの切離しが行われて形成される。2. Description of the Related Art Surface mounting type resin-sealed semiconductor devices have been widely used as semiconductor elements have been highly integrated and packaging has been made denser. In such a resin-sealed semiconductor device, a semiconductor element is mounted on a mount surface of an island provided on a lead frame together with leads and a frame portion,
After that, a package having a predetermined shape is formed by molding with a sealing resin material, and the leads are molded and separated from the frame portion of the lead frame.

【０００３】そして、プリント基板などへの実装はＶＰ
Ｓ（Ｖａｐｏｒ Ｐｈａｓｅ Ｓｏｌｄｅｒｉｎｇ）等
のリフロー半田付けによって行われ、樹脂封止半導体装
置は全体が２００℃以上の高温にさらされる。その際、
封止樹脂材料による成形を行ってから実装されるまでの
間に、パッケージの外表面等を通じてパッケージ内に吸
収され凝集した水分が気化し、この時の蒸気圧による作
用によって樹脂封止半導体装置に信頼性上の問題が生じ
ることがある。The mounting on a printed circuit board or the like is VP.
The entire resin-sealed semiconductor device is exposed to a high temperature of 200 [deg.] C. or higher, which is performed by reflow soldering such as S (vapor phase soldering). that time,
Moisture that has been absorbed and condensed in the package through the outer surface of the package, etc. evaporates between the time when the resin is molded with the encapsulating resin material and the time it is mounted. Reliability issues can arise.

【０００４】以下、その問題について図５を参照して説
明する。図５は樹脂封止半導体装置の断面図で、１は半
導体素子、２はアイランド３及びリード４が形成された
リードフレーム、５は半導体素子１の電極パッドとリー
ド４の内端部とを接続するボンディングワイヤ、６はパ
ッケージである。The problem will be described below with reference to FIG. FIG. 5 is a cross-sectional view of a resin-sealed semiconductor device. 1 is a semiconductor element, 2 is a lead frame on which an island 3 and leads 4 are formed, and 5 is an electrode pad of the semiconductor element 1 and an inner end of the lead 4 Bonding wire 6 is a package.

【０００５】パッケージ６内に吸収された水分はパッケ
ージ６とリードフレーム２のアイランド３との界面など
の接着が十分に行われにくい部位に凝集し、実装時の高
温にさらされる。この高温によって水分は気化し、気化
に伴う内部圧力の上昇によってパッケージ６内のアイラ
ンド３とパッケージ６の封止樹脂材料との接着部に剥離
が生じ、空隙７が形成され外表面に膨らみを生じる。こ
の空隙７の形成によってパッケージ６には外表面には至
らない内部クラック８や場合によっては外表面にまで達
する大きなクラック９が発生する。The moisture absorbed in the package 6 is condensed at a portion such as an interface between the package 6 and the island 3 of the lead frame 2 where adhesion is not sufficiently achieved, and is exposed to a high temperature during mounting. Due to this high temperature, the water vaporizes, and due to the rise in the internal pressure due to the vaporization, peeling occurs at the bonding portion between the island 3 in the package 6 and the sealing resin material of the package 6, and a void 7 is formed, causing bulging on the outer surface. . Due to the formation of the voids 7, internal cracks 8 that do not reach the outer surface and, in some cases, large cracks 9 that reach the outer surface occur in the package 6.

【０００６】そして外表面に至るクラック９が発生した
場合、樹脂封止半導体装置は耐湿性の著しい劣化等によ
って信頼性が低下する。すなわち、実装した機器の使用
にともないクラック９を通して樹脂封止半導体装置内に
使用雰囲気中の水分を含めた腐食性のガスが入り、時間
経過にしたがって半導体素子１の正常な作動が得られな
いようになる。When the crack 9 extending to the outer surface occurs, the reliability of the resin-sealed semiconductor device is deteriorated due to remarkable deterioration of moisture resistance. That is, corrosive gas including moisture in the atmosphere of use enters into the resin-sealed semiconductor device through the crack 9 as the mounted device is used, and normal operation of the semiconductor element 1 may not be obtained over time. become.

【０００７】一方、このような状況に対し、アイランド
３の半導体素子１が搭載されていない面に対するパッケ
ージ６の封止樹脂材料の接着力を増加させるようにし、
パッケージ６内のアイランド３とパッケージ６の封止樹
脂材料との接着部に空隙７が形成されないようにするこ
とが試みられているが、十分な結果が得られるものとは
なっていない。On the other hand, in such a situation, the adhesive force of the sealing resin material of the package 6 to the surface of the island 3 on which the semiconductor element 1 is not mounted is increased,
Attempts have been made to prevent the voids 7 from being formed in the bonding portion between the island 3 in the package 6 and the sealing resin material of the package 6, but the result has not been sufficient.

【０００８】[0008]

【発明が解決しようとする課題】上記のように実装時に
高温が作用して内部の水分の気化し、これによる内部圧
力の上昇でパッケージにその外表面にまで達するクラッ
クが生じ、このクラックを通しての吸湿等により樹脂封
止半導体装置及び実装機器の信頼性を低下させてしま
う。このような状況に鑑みて本発明はなされたもので、
その目的とするところは実装に際し高温が作用してもパ
ッケージの外表面にまで達するクラックの発生が抑制さ
れ、信頼性が大幅に向上した樹脂封止半導体装置を提供
することにある。As described above, the high temperature acts at the time of mounting to vaporize the internal moisture, and the rise of the internal pressure by this causes a crack reaching the outer surface of the package. The moisture absorption or the like reduces the reliability of the resin-sealed semiconductor device and the mounted equipment. The present invention has been made in view of such a situation,
It is an object of the present invention to provide a resin-sealed semiconductor device in which the occurrence of cracks reaching the outer surface of the package is suppressed even when a high temperature is applied during mounting, and the reliability is greatly improved.

【０００９】[0009]

【課題を解決するための手段】本発明の樹脂封止半導体
装置は、リードフレームに設けられたアイランドのマウ
ント面に半導体素子を搭載し封止樹脂材料でパッケージ
を成形してなる樹脂封止半導体装置において、アイラン
ドのマウント面への半導体素子の固着強度が、パッケー
ジを形成する封止樹脂材料とアイランドのマウント裏面
との接着強度より小さくなるように形成されていること
を特徴とするものであり、また、アイランドのマウント
面への半導体素子の固着強度が、パッケージを形成する
封止樹脂材料と半導体素子のマウント裏面との接着強度
より小さくなるように形成されていることを特徴とする
ものである。A resin-sealed semiconductor device of the present invention is a resin-sealed semiconductor in which a semiconductor element is mounted on a mount surface of an island provided in a lead frame and a package is molded with a sealing resin material. In the device, the fixing strength of the semiconductor element to the mount surface of the island is formed to be smaller than the adhesive strength between the sealing resin material forming the package and the back surface of the mount of the island. The adhesive strength of the semiconductor element to the mount surface of the island is smaller than the adhesive strength between the sealing resin material forming the package and the back surface of the mount of the semiconductor element. is there.

【００１０】[0010]

【作用】上記のように構成された樹脂封止半導体装置
は、アイランドのマウント面への半導体素子の固着強度
が、パッケージを形成する封止樹脂材料とアイランドの
マウント裏面との接着強度より小さくなるよう形成され
ている構成であり、また封止樹脂材料と半導体素子のマ
ウント裏面との接着強度より小さくなるように形成され
ている構成としたことにより、パッケージ内部に水分が
吸収され凝集されていて実装時に作用する高温によって
気化した場合でも、その蒸気圧は固着強度が小さいアイ
ランドのマウント面と半導体素子の固着部分に作用し、
この固着部分に剥離が生じ空隙が形成されて圧力が吸収
される。この時半導体素子及びアイランドが、それぞれ
が剥離した両側の部分の構造部材として作用するのでア
イランド端部での応力集中が緩和され、パッケージの外
表面にまで達するクラックの発生が抑制される。そのた
め樹脂封止半導体装置及び実装機器の信頼性が大幅に向
上する。In the resin-sealed semiconductor device configured as described above, the fixing strength of the semiconductor element to the mount surface of the island is smaller than the adhesive strength between the sealing resin material forming the package and the back surface of the mount of the island. Since it is formed so as to be smaller than the adhesive strength between the sealing resin material and the back surface of the mount of the semiconductor element, moisture is absorbed and aggregated inside the package. Even when vaporized by the high temperature that acts during mounting, the vapor pressure acts on the mounting surface of the island with a small bonding strength and the bonding portion of the semiconductor element,
Peeling occurs at this fixed portion, a void is formed, and the pressure is absorbed. At this time, since the semiconductor element and the island act as structural members of the separated portions on both sides, stress concentration at the end of the island is relieved and cracks reaching the outer surface of the package are suppressed. Therefore, the reliability of the resin-sealed semiconductor device and the mounted equipment is significantly improved.

【００１１】[0011]

【実施例】以下、本発明の実施例を図面を参照して説明
する。Embodiments of the present invention will be described below with reference to the drawings.

【００１２】先ず、第１の実施例を図１により説明す
る。図１は断面図で、１１は樹脂封止半導体装置であ
る。半導体装置の形成段階では、４２アロイ等の材料で
形成されたリードフレーム１２にはリード１３や図示し
ない枠部等と共に、アイランド１４が設けられている。
このアイランド１４のマウント面１５上には、略方形平
板状の半導体素子１６が固着され搭載されている。半導
体素子１６のマウント面１５への固着は、マウント面１
５と半導体素子１６の平担面との間にエポキシ系樹脂の
接着層１７を介在させるようにして行われている。First, a first embodiment will be described with reference to FIG. FIG. 1 is a sectional view, and 11 is a resin-sealed semiconductor device. At the stage of forming a semiconductor device, an island 14 is provided on a lead frame 12 made of a material such as 42 alloy together with the leads 13 and a frame portion (not shown).
On the mount surface 15 of the island 14, a substantially rectangular flat plate-shaped semiconductor element 16 is fixedly mounted. The semiconductor element 16 is fixed to the mount surface 15 by the mount surface 1
5 and the flat surface of the semiconductor element 16 with an adhesive layer 17 of epoxy resin interposed.

【００１３】そしてアイランド１４に半導体素子１６を
固着した状態で、例えば７０ｗｔ％の酸化珪素（ＳｉＯ
2 ）のフィラーを含むエポキシ系樹脂の封止樹脂材料に
よる成形によって、薄型で方形平板状をなす所定形状の
パッケージ１８を形成して樹脂封止が行われる。このパ
ッケージ１８の成形によってアイランド１４のマウント
裏面１９や半導体素子１６のマウント裏面２０には、直
接封止樹脂材料が硬化して接着される。With the semiconductor element 16 fixed to the island 14, for example, 70 wt% of silicon oxide (SiO 2
By molding the epoxy resin containing the filler of 2 ) with a sealing resin material, a thin, rectangular flat plate-shaped package 18 having a predetermined shape is formed and resin sealing is performed. By this molding of the package 18, the sealing resin material is directly cured and adhered to the mount back surface 19 of the island 14 and the mount back surface 20 of the semiconductor element 16.

【００１４】その後、さらにリード１３の成形及びリー
ドフレーム１２の枠部からの切離しが行われて樹脂封止
半導体装置１１は形成される。なお２１は半導体素子１
６の電極パッドとリード１３の内端部とを接続するボン
ディングワイヤである。After that, the lead 13 is further molded and separated from the frame portion of the lead frame 12, so that the resin-sealed semiconductor device 11 is formed. 21 is a semiconductor element 1
6 is a bonding wire for connecting the electrode pad 6 and the inner end of the lead 13.

【００１５】この樹脂封止半導体装置１１の形成では、
接着層１７を介してのアイランド１４のマウント面１５
上への半導体素子１６の固着強度は、接着層１７を形成
する接着剤を選択することによって、パッケージ１８の
成形を行った封止樹脂材料とアイランド１４のマウント
裏面１９との接着強度より小さくなるように形成され、
また同じく封止樹脂材料と半導体素子１６のマウント裏
面２０との接着強度に比べても小さくなるように形成さ
れている。In the formation of this resin-sealed semiconductor device 11,
Mount surface 15 of island 14 via adhesive layer 17
The adhesion strength of the semiconductor element 16 to the upper side is smaller than the adhesion strength between the sealing resin material used to form the package 18 and the mount back surface 19 of the island 14 by selecting the adhesive forming the adhesive layer 17. Is formed as
Similarly, the adhesive strength between the sealing resin material and the mount back surface 20 of the semiconductor element 16 is smaller than that of the adhesive.

【００１６】このように構成されているため、プリント
基板などへの実装をリフロー半田付けによって行い樹脂
封止半導体装置１１を高温にさらした場合、パッケージ
１８内に吸収されパッケージ１８とリードフレーム１２
のアイランド１４との界面などに凝集した水分は気化
し、パッケージ１８の内部圧力が上昇すると、この圧力
の上昇によって接着強度が小さいアイランド１４のマウ
ント面１５への半導体素子１６の固着部に剥離が生じ
る。これによってアイランド１４のマウント面１５と半
導体素子１６の間に上昇圧力に対応する空隙が形成され
る。With this structure, when the resin-encapsulated semiconductor device 11 is mounted on a printed circuit board or the like by reflow soldering and exposed to high temperature, it is absorbed in the package 18 and the package 18 and the lead frame 12 are absorbed.
The water condensed at the interface with the island 14 and the like is vaporized, and when the internal pressure of the package 18 rises, the pressure rises to peel off the fixing portion of the semiconductor element 16 to the mount surface 15 of the island 14 having a small adhesive strength. Occurs. As a result, a space corresponding to the rising pressure is formed between the mount surface 15 of the island 14 and the semiconductor element 16.

【００１７】そして、空隙の形成に際してアイランド１
４と半導体素子１６がそれぞれ構造部材としてパッケー
ジ１８内部で働くため、外表面に微小の膨らみが生じる
のみであり、空隙は蒸気の存在できる空間として圧力を
緩和するように作用し、パッケージ１８の内部から外表
面に至るクラック等の発生はみられなかった。またパッ
ケージ１８の外表面のクラック等からの内部への吸湿が
なく、経時的に樹脂封止半導体装置１１の特性が劣化す
ることもなかった。Then, when forming the voids, the island 1 is formed.
4 and the semiconductor element 16 each work as a structural member inside the package 18, so that only a small bulge is generated on the outer surface, and the void acts as a space in which vapor can be present so as to relieve the pressure. No occurrence of cracks or the like from the surface to the outer surface was observed. Further, there was no moisture absorption inside due to cracks or the like on the outer surface of the package 18, and the characteristics of the resin-encapsulated semiconductor device 11 did not deteriorate over time.

【００１８】なおパッケージ１８は、アイランド１４の
マウント面１５と半導体素子１６の間に形成される空隙
の大きさが、パッケージ１８の外表面等を通じて内部に
吸収される水分量が限られたものであるので、パッケー
ジ１８の強度等から予め推定でき、空隙が形成によって
外表面に至るクラック等の発生がないように設計されて
形成されている。In the package 18, the size of the void formed between the mount surface 15 of the island 14 and the semiconductor element 16 is such that the amount of moisture absorbed inside through the outer surface of the package 18 is limited. Therefore, the package 18 can be preliminarily estimated from the strength of the package 18 and the like, and is designed and formed so that the formation of the void does not cause a crack or the like reaching the outer surface.

【００１９】また、上述の実施例のように形成される本
発明の作用は、発明者等が行った有限要素法による応力
解析によっても裏付けられるものである。以下、その解
析結果について図２及び図３により説明する。図２は本
発明に係る剥離時の樹脂封止半導体装置内部の等応力線
図であり、図３は従来例に係る剥離時の樹脂封止半導体
装置内部の等応力線図である。そして図２及び図３の各
部位の符号は第１の実施例に対応させて付してある。Further, the operation of the present invention formed as in the above-described embodiment is supported by the stress analysis by the finite element method performed by the inventors. The analysis result will be described below with reference to FIGS. 2 and 3. FIG. 2 is an iso-stress diagram inside the resin-sealed semiconductor device at the time of peeling according to the present invention, and FIG. 3 is an iso-stress line diagram inside the resin-sealed semiconductor device at the time of peeling according to the conventional example. The reference numerals of the respective parts in FIGS. 2 and 3 are given in correspondence with the first embodiment.

【００２０】応力解析はパッケージ１８の外形が１４ｍ
ｍ角で、１．４ｍｍ厚のものとし、樹脂封止半導体装置
の中央断面の１／２領域を解析対象としている。また図
２及び図３は、アイランド１４のマウント面１５と半導
体素子１６間の剥離、すなわちマウント面１５での剥離
の場合と、アイランド１４のマウント裏面１９とパッケ
ージ１８の成形を行った封止樹脂材料間の剥離、すなわ
ちマウント裏面１９での剥離の場合における２次元解析
による最大主応力分布を（ＭＰａ）を単位とし、各応力
値を（ ）内に示すもので、応力集中は共にアイランド
１４の端部近傍において生じている。For the stress analysis, the outer shape of the package 18 is 14 m.
The area is m-square and has a thickness of 1.4 mm, and a half area of the central cross section of the resin-sealed semiconductor device is an analysis target. 2 and 3 show a case where the mounting surface 15 of the island 14 is peeled off from the semiconductor element 16, that is, the mounting surface 15 is peeled off, and the mount back surface 19 of the island 14 and the package 18 are molded. The maximum principal stress distribution by two-dimensional analysis in the case of delamination between materials, that is, delamination on the mount back surface 19 is shown in () with each stress value shown in parentheses. It occurs near the edge.

【００２１】そして、マウント面１５での剥離の方がマ
ウント裏面１９での剥離に比べてパッケージ１８の変形
が小さく、アイランド１４の端部の応力集中が穏やかな
ものとなっている。これはマウント裏面１９での剥離で
は蒸気圧をパッケージ１８だけで受けるために、変形が
大きくなり著しい応力集中が生じるのに対し、マウント
面１５での剥離では半導体素子１６とアイランド１４が
構造部材として働き、アイランド１４の端部近傍での応
力集中が平均化されることによるからである。The peeling on the mount surface 15 causes less deformation of the package 18 than the peeling on the mount back surface 19, and the stress concentration at the end of the island 14 is gentle. This is because the peeling on the mount back surface 19 receives the vapor pressure only by the package 18, so that the deformation is large and a remarkable stress concentration occurs. On the other hand, the peeling on the mount surface 15 uses the semiconductor element 16 and the island 14 as structural members. This is because it works and the stress concentration near the ends of the island 14 is averaged.

【００２２】なお、半導体素子１６のマウント裏面２０
とパッケージ１８の成形を行った封止樹脂材料間の剥
離、すなわちマウント裏面２０での剥離の場合も、アイ
ランド１４のマウント裏面１９での剥離の場合と同様の
応力集中が生じる。The mount back surface 20 of the semiconductor element 16
Also in the case of peeling between the encapsulating resin materials on which the package 18 is molded, that is, the peeling on the mount back surface 20, the same stress concentration as in the case of peeling on the mount back surface 19 of the island 14 occurs.

【００２３】次に、第２の実施例を図４により説明す
る。図４は断面図で、２２は樹脂封止半導体装置であ
り、アイランド１４のマウント面１５と半導体素子１６
の平担面との間の一部分にエポキシ系樹脂の接着層２３
を形成するようにして、マウント面１５上に半導体素子
１６が固着され搭載されている。Next, a second embodiment will be described with reference to FIG. FIG. 4 is a cross-sectional view, 22 is a resin-sealed semiconductor device, and includes a mount surface 15 of the island 14 and a semiconductor element 16.
Epoxy resin adhesive layer 23 on a part between the flat surface of the
The semiconductor element 16 is fixedly mounted on the mount surface 15 so as to form the.

【００２４】このため、一部のみが接着層２３を介して
アイランド１４のマウント面１５上に接着されている半
導体素子１６の固着強度は、パッケージ１８の成形を行
った封止樹脂材料とアイランド１４のマウント裏面１９
との接着強度より小さくなるように形成され、また同じ
く封止樹脂材料と半導体素子１６のマウント裏面２０と
の接着強度に比べても小さくなるように形成されてい
る。Therefore, the fixing strength of the semiconductor element 16 which is only partially adhered to the mount surface 15 of the island 14 via the adhesive layer 23 depends on the sealing resin material used for molding the package 18 and the island 14. Mount back side 19
And the sealing resin material and the mount back surface 20 of the semiconductor element 16 are also smaller than the adhesive strength.

【００２５】以上のように本実施例が構成されているの
で、実装する場合には第１の実施例と同様の作用・効果
が得られるものである。Since this embodiment is constructed as described above, when it is mounted, the same action and effect as those of the first embodiment can be obtained.

【００２６】尚、本発明は上記の各実施例のみに限定さ
れるものではなく、要旨を逸脱しない範囲内で適宜変更
して実施し得るものである。It should be noted that the present invention is not limited to the above-described embodiments, but can be implemented with appropriate modifications within the scope of the invention.

【００２７】[0027]

【発明の効果】以上の説明から明らかなように、本発明
は、アイランドのマウント面への半導体素子の固着強度
が、パッケージを形成する封止樹脂材料とアイランドの
マウント裏面との接着強度より小さくなるよう形成され
ている構成としたことにより、高温が実装時に作用する
ような場合でもパッケージの外表面にまで達するクラッ
クの発生が抑制されて樹脂封止半導体装置及び実装機器
の信頼性が大幅に向上する等の効果が得られる。As is apparent from the above description, according to the present invention, the adhesion strength of the semiconductor element to the mount surface of the island is smaller than the adhesive strength between the sealing resin material forming the package and the back surface of the mount of the island. Since the structure is formed so that the occurrence of cracks reaching the outer surface of the package is suppressed even when high temperature acts at the time of mounting, the reliability of the resin-sealed semiconductor device and mounted equipment is significantly improved. Effects such as improvement can be obtained.

【図面の簡単な説明】[Brief description of drawings]

【図１】本発明の第１の実施例を示す断面図である。FIG. 1 is a sectional view showing a first embodiment of the present invention.

【図２】本発明における剥離時の樹脂封止半導体装置内
部の等応力線図である。FIG. 2 is an iso-stress diagram inside a resin-sealed semiconductor device at the time of peeling according to the present invention.

【図３】従来例における剥離時の樹脂封止半導体装置内
部の等応力線図である。FIG. 3 is an iso-stress diagram inside a resin-sealed semiconductor device at the time of peeling in a conventional example.

【図４】本発明の第２の実施例を示す断面図である。FIG. 4 is a sectional view showing a second embodiment of the present invention.

【図５】従来の樹脂封止半導体装置の問題点を説明する
ために示す断面図である。FIG. 5 is a cross-sectional view shown for explaining problems of a conventional resin-sealed semiconductor device.

【符号の説明】[Explanation of symbols]

１２…リードフレーム １４…アイランド １５…アイランドのマウント面 １６…半導体素子 １７…接着層 １８…パッケージ １９…アイランドのマウント裏面 ２０…半導体素子のマウント裏面 12 ... Lead frame 14 ... Island 15 ... Island mounting surface 16 ... Semiconductor element 17 ... Adhesive layer 18 ... Package 19 ... Island mount back surface 20 ... Semiconductor element mount back surface

Claims (2)

【特許請求の範囲】[Claims] 【請求項１】 リードフレームに設けられたアイランド
のマウント面に半導体素子を搭載し封止樹脂材料でパッ
ケージを成形してなる樹脂封止半導体装置において、前
記アイランドのマウント面への前記半導体素子の固着強
度が、前記パッケージを形成する封止樹脂材料と前記ア
イランドのマウント裏面との接着強度より小さくなるよ
うに形成されていることを特徴とする樹脂封止半導体装
置。1. A resin-sealed semiconductor device in which a semiconductor element is mounted on a mount surface of an island provided on a lead frame and a package is molded with a sealing resin material, wherein the semiconductor element is mounted on the mount surface of the island. A resin-encapsulated semiconductor device, which is formed so that a fixing strength is smaller than an adhesion strength between a sealing resin material forming the package and a back surface of a mount of the island. 【請求項２】 アイランドのマウント面への半導体素子
の固着強度が、パッケージを形成する封止樹脂材料と前
記半導体素子のマウント裏面との接着強度より小さくな
るように形成されていることを特徴とする請求項１記載
の樹脂封止半導体装置。2. The adhesion strength of the semiconductor element to the mount surface of the island is formed to be smaller than the adhesive strength between the sealing resin material forming the package and the mount back surface of the semiconductor element. The resin-encapsulated semiconductor device according to claim 1.
JP4243886A 1992-09-14 1992-09-14 Resin-sealed semiconductor device Pending JPH0697322A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP4243886A JPH0697322A (en) 1992-09-14 1992-09-14 Resin-sealed semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP4243886A JPH0697322A (en) 1992-09-14 1992-09-14 Resin-sealed semiconductor device

Publications (1)

Publication Number Publication Date
JPH0697322A true JPH0697322A (en) 1994-04-08

Family

ID=17110455

Family Applications (1)

Application Number Title Priority Date Filing Date
JP4243886A Pending JPH0697322A (en) 1992-09-14 1992-09-14 Resin-sealed semiconductor device

Country Status (1)

Country Link
JP (1) JPH0697322A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN108352330A (en) * 2015-12-30 2018-07-31 德州仪器公司 Printing adhesion deposition for mitigating integrated circuit layering

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN108352330A (en) * 2015-12-30 2018-07-31 德州仪器公司 Printing adhesion deposition for mitigating integrated circuit layering

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