JPH0694797A - Ic test device - Google Patents

Abstract

PURPOSE:To automatically perform the offset adjustment of a driver driving an IC to be tested and a comparator comparing the output of the IC to be tested with a reference value. CONSTITUTION:Offset automatic correction circuits 3 are arranged between an input data level power supply 1a applying voltage of a level driving an IC and a driver 7 and between an output data level power supply applying the reference value of the output voltage of the IC and comparators 8a,8b. The input voltages of the driver 7 and the comparators 8a,8b are set to 0V and the offset voltage at this time is measured by an internal voltmeter 10 and a computer 2 calculates a correction value for setting the offset voltage to 0 to load a resistor with said value. The correction value is inputted to an amplifier 6 through a D/A converter 5 to adjust offset.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an IC test system, and more particularly to a VLSI test system for testing multi-pin devices.

[0002]

2. Description of the Related Art FIG. 3 is a block diagram of a conventional IC test system of this type for one pin. In the figure, 1a
Is an input data level power supply, 1b is an output data level power supply, 7 is a driver which gives an input signal to the IC under test, 8
a and 8b are comparators for comparing the output signal of the IC under test with the reference voltage output from the output data level power supply, and 9
Is an analog switch, 10 is an internal voltmeter that measures the output voltage of the driver 7, comparators 8a and 8b, and 11 is a control input terminal to which the test pattern generated by the pattern generator is input (depending on the level input to this terminal). Driver 7 outputs a signal of H or L level), 12 is an input / output terminal connected to a pin of the IC under test, 13 is an output terminal of a comparator, 14 is a variable resistor for offset adjustment, and SW ₁ to SW ₁ . SW ₃ is a switch.

Next, the offset adjusting operation of this system will be described. FIG. 4 is a flowchart showing the offset voltage correction process of the driver 7. First, the switches SW ₁ and SW ₃ are closed, the switch SW ₂ is opened, and a signal for the driver 7 to be in the H side output state is input from the control input terminal 11. In this state, the output voltages VIH and VIL of the input data level power supply are both set to 0V (step 41),
The output voltage of the driver 7 at this time is measured by the internal voltmeter 10 (step 42). The variable resistor 14 on the H side is adjusted so that the output voltage of the driver 7 becomes 0 (step 43). Next, a signal is input from the control input terminal 11 so that the output state of the driver is an L level signal, and the above steps are repeated.

Next, the offset of the comparator is adjusted. First, the switches SW ₁ and SW ₃ are opened, the switch SW ₂ is closed, and the output terminal 13 of the comparator 8a on the H side is connected to the internal voltmeter 10 by a wiring (not shown). Input 0V from the input / output terminal 12, and swing the output voltage VOH of the output data level power supply 1b in the vicinity of 0V.
When the output of the comparator 8a changes from L level to H level, VOH becomes 0V,
Adjust the variable resistor 14 of a. H side comparator 8
When the adjustment of a is completed, the output terminal 13 of the L-side comparator 8b is connected to the internal voltmeter 10, and the same adjustment is performed for the variable resistor 14 of the L-side comparator.

Next, an IC test method will be described. Now, it is assumed that the input / output terminal 12 is connected to the input pin of the IC under test. In this case, switch SW ₁
Is closed and the switch SW ₂ is opened. Depending on the type of IC under test (ECL type, CMOS type, etc.), a signal from one of the input data level power supplies 1a is selected and input to the driver 7 by the analog switch 9. A test pattern is input to the control input terminal 11 from the pattern generator. The driver 7 outputs a signal of H or L level according to the input test pattern.

When the pin of the IC under test connected to the input / output terminal 12 is the output pin, the switch SW ₁ is opened and the switch SW ₂ is closed. The output of one of the output data level power supplies 1b is selected by the analog switch 9 in accordance with the type of the IC under test and input to the comparators 8a and 8b. From the output data level power supply 1b, as the VOH, the voltage of the H level reference value (lowest reference value) is again V
As the OL, the voltage of the L level reference value (highest reference value) is output.

The output signal of the IC under test is input to the comparators 8a and 8b via the input / output terminal 12. It is assumed that the IC under test is outputting an H level signal, and if the value exceeds the H level reference value, the H side comparator 8a outputs an H level signal. Otherwise, the comparator 8a outputs an L level signal. If the output of the IC under test is L and its value is below the reference value, the L-side comparator 8b outputs an L-level signal, and if the value exceeds the reference value, the comparator 8b outputs an H-level signal. Output. The signals output from the comparators 8a and 8b are taken out through the output terminal 13 and compared with the pattern to be output by the non-defective product in the IC tester.

[0008]

In the above-mentioned conventional IC test system, the offset voltage of the driver and the comparator is corrected by visually observing the internal voltmeter and manually adjusting the variable resistor. There was a problem that it took a long time.

[0009]

An IC test system according to the present invention is an input data level power supply for generating a voltage of a level to be input to an IC under test, and an input for correcting an output voltage output from the input data level power supply. A correction circuit, a driver that receives an output signal of the input correction circuit and outputs a drive signal of an IC under test, and a correction of the input correction circuit that is necessary to measure the output offset voltage of the driver and set it to 0 An output data level power supply for generating a reference level voltage of the output signal of the IC under test, and a mechanism for setting the correction amount in the input correction circuit. An output correction circuit for correcting the reference level voltage output from the power supply; a comparator for comparing the output voltage of the output correction circuit with the output signal level of the IC under test; The input offset voltage of the comparator is measured, 0V output offset voltage of the comparator when the output value of the output data level power is 0V
And a mechanism for determining a correction amount of the output correction circuit necessary for the above and setting the correction amount in the output correction circuit.

[0010]

Embodiments of the present invention will now be described with reference to the drawings. FIG. 1 is a block diagram showing an embodiment of the present invention. In the figure, only the circuit for one pin of the IC under test is shown. In the figure, reference numeral 1a denotes an input data level power supply for giving a level of a signal to be input to the IC under test,
2 is a computer, 3 is a register 4, bipolar output type D
A / A converter 5 and amplifier 6 are provided for automatic offset correction circuit, 7 is a driver for giving an input signal for driving the IC under test, and 8a and 8b are I under test.
A comparator for comparing the output signal of C and the reference voltage (correction voltage by the offset automatic correction circuit) output from the output data level power supply, 9 is an analog switch, 10
Is an internal voltmeter that measures the output voltage of the driver 7 and the comparators 8a and 8b, and 11 is a control input terminal to which the test pattern generated by the pattern generator is input (driver 7 depending on the level input to this terminal A signal of H or L level is output), 12 is an input / output terminal connected to a pin of the IC under test, 13 is an output terminal of the comparator, and SW _{1 to} SW ₃ are switches.

Next, the offset correction operation of this embodiment will be described with reference to FIGS. FIG. 2 is a flowchart showing the driver offset voltage correction process of this embodiment. The switch S is used for offset correction of the driver 7.
W ₁ and SW ₃ are closed and switch SW ₂ is open. The output state of the driver 7 is set to the H side by the signal from the control input terminal 11, and the output voltage of the input data level power supply 1a is set to 0V (step 21). Next, the output voltage of the D / A converter 5 in the automatic offset correction circuit 3 is set to 0V.
(Step 22).

Next, the output offset voltage of the driver 7 is measured by the internal voltmeter 10 (step 23), and the result is stored in the memory of the computer 2 (step 24).
The computer 2 calculates an offset correction voltage from the measurement result (step 25) and loads the data into the register 4 in the automatic correction circuit 3 (step 26). The D / A converter 5 in the automatic correction circuit 3 converts the data loaded in the register 4 into an analog voltage value (step 2
7), and apply the value to one input terminal of the amplifier 6.
As a result, the H level input signal VIH corrected to be necessary for canceling the H level output offset of the driver 7 is input to the driver 7.

Next, the output state of the driver 7 is set to the L side by the signal from the control input terminal 11, and the same process as above is repeated. However, if the L side output voltage of the data level power supply 1a and the output voltage of the D / A converter of the L side automatic correction circuit 3 are set to 0V at the same time in the previous correction process, start from step 23. Good.

When the correction of the H-side and L-side input voltages of the driver 7 is completed, the offset correction of the comparators 8a and 8b is performed. First, the switches SW ₁ and SW ₃ are opened and the switch SW ₂ is closed, and the output terminal 13 of the H-side comparator 8 a is connected to the internal voltmeter 10. In this state, 0V is input from the input / output terminal 12, and the output of the D / A converter of the H-side offset automatic correction circuit 3 is set to 0V. In this state, the output voltage VOH of the output data level power supply (not shown) is swung in the vicinity of 0 V, and VOH when the output of the comparator 8a is switched from the H level to the L level
Calculate the voltage value of. The computer 2 stores the voltage value and loads the value into the register of the offset automatic correction circuit 3.

When the correction for the H-side comparator 8a is completed, the output terminal 13 of the comparator 8a is disconnected from the internal voltmeter 10, and the output terminal of the L-side comparator 8b is connected to the internal voltmeter 10 instead, and the offset is set in the same manner as above. Make a correction.

By programming the above process as an offset automatic adjustment program and executing this program, the offset adjustment can be automatically performed.

The offset correction voltage data thus obtained is stored in an auxiliary storage device such as a disk,
Automatic offset correction circuit 3 when starting the system
So that it is loaded into register 4 of. In addition, I under test
The test method for C is not different from that of the conventional example, and therefore its explanation is omitted.

[0018]

As described above, the IC test system of the present invention includes the driver for driving the IC under test and the correction circuit for automatically correcting the offset of the comparator for comparing the output signal of the IC with the reference value. According to the present invention, the adjustment of the offset voltage can be performed without relying on the manual observation of the voltmeter and the manual adjustment of the variable resistor, and the test man-hour can be reduced. When testing a multi-pin VLSI (or ULSI), the adjustment time can be greatly reduced.

[Brief description of drawings]

FIG. 1 is a block diagram of an embodiment of the present invention.

FIG. 2 is a flowchart showing an offset voltage correction process of the embodiment of FIG.

FIG. 3 is a block diagram of a conventional example.

FIG. 4 is a flowchart showing a conventional offset voltage correction process.

[Explanation of symbols]

 1a Input data level power supply 1b Output data level power supply 2 Computer 3 Offset automatic correction circuit 4 Register 5 Bipolar output type D / A converter 6 Amplifier 7 Driver 8a, 8b Comparator 9 Analog switch 10 Internal voltmeter 11 Control input terminal 12 Input / output Terminal 13 Output terminal of comparator 14 Variable resistor for offset adjustment

Claims (2)

[Claims] 1. An input data level power supply that generates a voltage of a level to be input to an IC under test, an input correction circuit that corrects an output voltage output from the input data level power supply, and an output signal of the input correction circuit. A driver that receives the output signal of the IC under test and an output offset voltage of the driver are measured,
And a mechanism for determining a correction amount of the input correction circuit necessary for the setting and setting the correction amount in the input correction circuit. 2. An output data level power supply for generating a reference level voltage of an output signal of an IC under test, an output correction circuit for correcting a reference level voltage output by the output data level power supply, and an output voltage of the output correction circuit. A comparator for comparing the output signal levels of the IC under test and an input offset voltage of the comparator, and when the output value of the output data level power supply is 0V, the output offset voltage of the comparator is set to 0V. An IC test system comprising: a mechanism for determining a necessary correction amount of the output correction circuit and setting the correction amount in the output correction circuit.