JPH069331B2 - Timer device - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a timer device having an n-bit programmable counter, which realizes a 2n-bit prescale value with a simple configuration.

<Prior Art> In a conventional timer having an n-bit programmable counter, a timer device having a 2n-bit prescale value has a configuration as shown in FIG.

In the figure, (15) is a 2n-bit prescale decrement that obtains a divided clock φp of φ / N1 by down-counting the basic clock φ input to the terminal (15a) with a 2n-bit prescale value N1 as an initial value. (16) is a 2n-bit prescale register that presets a 2n-bit prescale value N1 in the prescale decrementer (15), and (17) is an n-bit prescale value N2 as an initial value. An n-bit timer decrementer that down-counts the divided clock φp and outputs a timer count end output φp / N2 which is 1 / N2 of the divided clock φp, (18) is an n-bit prescale value N2
To the timer decrementer (17), an n-bit timer register, (19) a timer control register for controlling timer start / stop commands, and (20) a timer control register (19 ) Controls the circuits other than the timer control register (19) so that the timer operates in the mode specified by), and prescale decrementer (15), prescale register (16), timer decrementer (17) , A timer control for controlling the exchange of data between the timer registers (18).

The operation will be briefly described below.

When the start command signal is output from the timer control (20), the prescale value N1 held in the prescale register (16) is preset in the prescale degrimmer (15). Also, the prescale value N2 held in the timer register (18) is the timer decrementer.
It is preset to (17).

The prescale decrementer (15) downcounts the basic clock φ input to the terminal (15a) with the prescale value N1 as an initial value, and outputs a divided clock φp of φ / N1. Then, the timer decrementer (1
In 7), the prescale value N2 is used as an initial value to down-count the divided clock φp, and when the value becomes [0], the timer count end φp / 2 is output.

That is, the timer count end output is φ / N1N2 with respect to the basic clock φ.

<Problems to be Solved by the Invention> As described above, the conventional timer device having the n-bit programmable counter has a 2n-bit prescale decrementer (15) in order to realize a 2n-bit prescale value. ) And a 2n-bit prescale register (16) are indispensable. Therefore, if the prescale value becomes large, a programmable counter having a large number of bits is required, and the circuit scale and the circuit arrangement scale become large.

The present invention solves such a problem, and is a timer device provided with an n-bit programmable counter, which realizes a 2n-bit prescale value with a simple configuration.

<Means for Solving the Problems> A description will be given with reference to FIG. 1 showing a typical embodiment of the present invention.

This invention is an n-bit decrementer means (decrementer circuit (8)).
And a prescale upper port means (prescale upper port circuit (5)) for holding the upper n bits of the 2n-bit prescale value and a prescale lower port means for holding the 2n bit and the lower n bits of the prescale value. (Prescale lower port circuit (7)), timer port means (timer port circuit (1)) for holding an n-bit timer value, lower n bits of the 2n-bit prescale value are decrementer means (decrementer) Circuit (8)), and a first programmable counter means for obtaining a first divided output corresponding to the lower n bits of the prescale value by counting the basic clock with the preset value as an initial value, Corresponding to the digit weight of the least significant bit of the upper n bits of the 2n-bit prescale value based on the first frequency division output Register means (correction register circuits (3), (4)) for holding the correction value as a constant and this value are preset in the decrementer means (decrementer circuit (8)), and this preset value is used as an initial value. Second programmable counter means for obtaining a second frequency division output corresponding to the weight of the least significant bit of the upper n bits of the prescale value by counting the basic clock as; On the basis of the above, the upper n bits of the 2n-bit prescale value are preset in the decrementer means (decrementer circuit (8)), and the second divided output is counted by using the preset value as an initial value, Third programmable counter means for obtaining a third divided output corresponding to the upper n bits of the prescale value, and the n-bit timer value based on the third divided output Is preset in the decrementer means (decrementer circuit (8)), the preset frequency value is used as an initial value to count the third frequency division output, and a fourth frequency division output corresponding to the timer value is obtained. The programmable counter means (1) and the fourth frequency division output are used as timer outputs.

<Operation> FIG. 2 (a), (b) showing the operation of a typical embodiment of the present invention.
Will be explained.

(i) The lower n bits of the 2n-bit prescale value are preset in the decrementer means (decrementer circuit (8)), and the preset clock is used as an initial value to count the basic clock, thereby lowering the prescale value. Obtain the first divided output corresponding to n bits.

(ii) A correction value corresponding to the digit weight of the least significant bit of the upper n bits of the 2n-bit prescale value is provided to the decrementer means (decrementer circuit (8)) based on the first frequency division output. The preset clock is preset and the basic clock is counted using this preset value as an initial value to obtain a second frequency division output corresponding to the digit weight of the least significant bit of the upper n bits of the prescale value.

(iii) Based on the second frequency division output, the upper n bits of the 2n-bit prescale value are preset in the decrementer means (decrementer circuit (8)), and the preset value is used as an initial value for the second Counting the frequency-divided output of the third prescale value corresponding to the upper n bits
Get the divided output of.

(iv) The n-bit timer value is changed to the decrementer means (decrementer circuit) based on the third frequency division output.
(8)) is preset, and the preset frequency is used as an initial value to count the third frequency division output to obtain the fourth frequency division output corresponding to the timer value.

Since the fourth frequency-divided output is used as the timer output through the step of, the decrementer can be realized by an n-bit decrementer.

<Example> A typical example of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing a typical embodiment of the present invention,
2 (a) and 2 (b) are flowcharts showing the same operation, and FIG. 3 is a timing chart of the respective control signals.

This will be described with reference to FIG.

(1) is a timer port circuit (TMR) that holds an n-bit timer value.

(2) is a timer register circuit (TMR REG), which has the same value as the timer port circuit (TMR) (1) as an initial value, but when the timer operation starts, this value is set every preset number of clocks described later. The value is input to the decrementer circuit (DEC) (8), subtracted (-1) by this decrementer circuit (DEC) (8), and the value is returned to the timer register circuit (TMRREG) (2). . This value is retained until the next operation. T in the figure
MR → TMRREG is a timer port circuit (TMR)
Data read signal from (1) to timer register circuit (TMRR REG) (2), TMRREG → DEC is data output signal from timer register circuit (TMR REG) (2) to decrementer circuit (DEC) (8), DEC
→ TMRREG is a data read signal from the decrementer circuit (DEC) (8) to the timer register circuit (TMRREG) 2.

(3) is for correcting the digit weight of the least significant bit of the upper n bits of the 2n-bit prescale value,
It is a first digit weight correction register circuit (OO REG) having a weight correction value of the digit of the least significant bit of the upper n bits of the 2n-bit prescale value. In the present invention, the 2n-bit prescale value is divided into upper n bits and lower n bits, and the prescale values corresponding to these upper n bits and lower n bits are decremented by an n-bit decrementer circuit (DE).
C) (8) is separately subtracted (-1) and counted.
Therefore, in order to count the upper n bits, it is necessary to count the weight of the digit of the least significant bit of the upper n bits of the prescale value (that is, the correction value) and then count the upper n bits. Since the correction value is a constant corresponding to the digit weight, the first digit weight correction register circuit (OO REG) (3) can be realized with a simple circuit configuration.

In the figure, OOREG → DEC is the decrementer circuit (D) from the first digit weight correction register circuit (OOREG) (3).
This is a signal for sending data to EC) (8).

(4) is the second digit weight correction register circuit (FFREG)
Then, the first digit weight correction register circuit (OO REG)
This is a register having a correction value subtracted (-1) from the contents of (3). This is a correction to be made when the decrementer circuit (DEC) (8) is counting the value of another register because the counting operation is increased only once. Since this correction value is a constant corresponding to the digit weight, the second digit weight correction circuit (FF REG) (4) can be realized with a simple circuit configuration.

In the figure, FFREG → DEC is the second digit weight correction register circuit (FF REG) (4) to the decrementer circuit (D
This is a signal for sending data to EC) (8).

(5) is a prescale upper port circuit (PREU) for holding the upper n bits of the 2n-bit prescale value.
P).

(6) is the prescale upper port circuit (PR
E UP) (5) is a prescale upper register circuit (UP REG) having the same value. When the timer operation is started and the weight of the digit of the least significant bit of the upper n bits of the prescale value (that is, the correction value) is counted,
The value of the prescale upper register circuit (UP REG) (6) is input to the decrementer circuit (DEC) (8), and the value is subtracted (-1) by this decrementer circuit (DEC) (8) to obtain the value. It is returned to the prescale upper register circuit (UP REG) (6). This value is retained until the next operation.

In the figure, PREUP → UPREG is a data read signal from the prescale upper port circuit (PRE UP) (5) to the prescale upper register circuit (UP REG) (6), and UPREG → DEC is a prescale upper register circuit (UP REG) ) (6) to the decrementer circuit (DE
C) Data sending signal to (8), DEC → UPREG
Is a data read signal from the decrementer circuit (DEC) (8) to the prescale upper register circuit (UP REG) (6).

(7) is a prescale lower port circuit (PRE L) for holding the lower n bits of the 2n-bit prescale value.
OW).

Reference numeral (8) is an n-bit decrementer circuit (DEC) (8) that counts down (-1) the basic clock by using a preset value as an initial value.

In the figure, DEC1 is the output when the value of the decrementer circuit (DEC) (8) is [1], DEC0 is the output when the value of the decrementer circuit (DEC) (8) is [0], and TMRφ is the decrementer circuit ( This is the basic clock input to the DEC) (8).

(9) is a timer control register circuit (TMR CONT) for defining the timer operation.
It has a bit for the stop command signal.

(10) is a prescale upper zero flag circuit (UZ) for defining the prescale operation mode. When the prescale upper port circuit (PRE UP) (5) is [0], its output becomes [1]. .

(11) is a prescale lower zero flag circuit (LZ) for defining the prescale operation mode. When the prescale lower port circuit (PRE LOW) (7) is [0],
The output is [1].

(12) is a timer sequencer circuit (TIMER SEQUENCE) that sets the next operation by checking the current timer operation.
R).

(13) is a timer control circuit (TI) for outputting control signals (various control signals described above) necessary for the next timer operation.
MER CONTROL).

In the figure, (14a) and (14b) are first and second data buses for transmitting the various data, STOR → TMR is a timer port circuit (TMR) (1), a timer register circuit (TMR REG ) (2) control signal for setting data, STOR → PREUP is a prescale upper port circuit (PRE UP) (5), prescale upper register circuit (UP REG) (6) control signal for setting data, STOR → PRELOW is a control signal that sets data in the prescale lower port circuit (PRE LOW) (7), STOR → CONT is a control word that includes start / stop command signals in the timer control register circuit (TMR CONT) (9) The control signal for resetting, RESET, is the timer port circuit (TM
R) (1), timer register circuit (TMR REG)
(2), prescale upper port circuit (PRE UP)
(5), prescale upper register circuit (UP REG)
(6), prescale lower port circuit (PRE LOW)
(7) and timer control register circuit (TMR
CONT) (9) is a control signal for resetting.

That is, prescale lower port circuit (PRE LOW)
Output of (7) (lower n of the 2n-bit prescale value
Bit) is preset in the decrementer circuit (DEC) (8), the basic clock is counted with this preset value as an initial value, and a first divided output corresponding to the lower n bits of the prescale value is obtained. 1 programmable counter means.

Based on this first frequency division output, the output of the first digit weight correction register circuit (OO REG) (3) (the weight correction value of the least significant bit of the upper n bits of the 2n-bit prescale value) ) Is preset in the decrementer circuit (DEC) (8), the basic clock is counted using this preset value as an initial value, and the weight of the digit of the least significant bit of the upper n bits of the prescale value (that is, correction And a first programmable counter means for obtaining a second frequency division output corresponding to (value).

In the first programmable counter means, when another register value is contained in the decrementer circuit (DEC) (8), a one-time counting error occurs, so in order to correct it, the second digit weight correction Register circuit (FF RE
The output of G) (4) may be preset in the decrementer circuit (DEC) (8) to obtain the second frequency division output.

Based on this second frequency division output, the main force of the prescale upper register circuit (UP REG) (6) (upper n bits of the 2n-bit prescale value) is preset in the decrementer circuit (DEC) (8). The preset value is used as an initial value to count the second frequency-divided output to form a third programmable counter means for obtaining a third frequency-divided output corresponding to the upper n bits of the prescale value.

A timer register circuit (TMR RE that holds the n-bit timer value is based on the third frequency division output.
G) (2) output (n-bit timer value) is preset in the decrementer circuit (DEC) (8), the preset value is used as an initial value to count the third frequency division output, and the timer value And fourth programmable counter means for obtaining a fourth frequency-divided output corresponding to.

Then, in this embodiment, there are the following three operation modes.

(i) Mode 0 (UZ = 1, LZ = 1) When the outputs of the prescale upper zero flag circuit (UZ) (10) and the prescale lower zero flag circuit (LZ) (11) are both [1], the fourth Only the programmable counter means operates.

(ii) Mode 1 (UZ = 1, LZ = 0) Prescale upper zero flag circuit (UZ) (10) output is [1], prescale lower zero cell flag circuit (LZ) (11)
, The first and fourth programmable counter means operate. That is, the prescale operation corresponding to the lower n bits of the 2n-bit prescale value is performed.

(iii) Mode 2 (UZ = 0, LZ = 0) When the outputs of the prescale upper zero flag circuit (UZ) (10) and the prescale lower zero flag circuit (LZ) (11) are both [0], the first, The second, third and fourth programmable counter means operate.

(iv) Mode 3 (UZ = 0, LZ = 1) When the output of the prescale upper zero flag circuit (UZ) (10) is [0] and the output of the prescale lower zero flag circuit (LZ) is [1], The second, third and fourth programmable counter means operate. That is, the prescale operation corresponding to the upper n bits of the 2n-bit prescale value is performed.

The operation of the mode 2 of this embodiment will be described below with reference to FIGS. 2 (a) and 2 (b).

The basic operation is as described in the section of <Operation>. In order to see the operation at each step in the flowchart of FIGS. 2 (a) and 2 (b), the step corresponding to this operation is numbered. The numbers correspond to the respective numbers in the timing chart of FIG.

First, the timer value is set in the timer port circuit (TMR) (1), and the prescale upper port circuit (PRE UP)
(5), prescale lower port circuit (PRE LOW)
In (7), the upper n bits and lower n bits of the 2n-bit prescale value are preset. Then, the timer operation is started.

Step 1: Prescale lower port circuit (PRE LOW) 7 data (lower n bits) is decrementer circuit (DEC)
Preset to (8), subtract this preset value as the initial value (-1), and the value is [0] (DEC0 occurs)
When the value becomes [0] (DEC0 is generated), the frequency division output (OOREG → DEC) corresponding to the lower bit is output.

Step 2: Based on this frequency division output, the data (correction value) of the first digit weight correction register circuit (OO REG) (3) is preset in the decrementer circuit (DEC) (8), and this preset value is set. The subtraction (-1) is performed as an initial value, and the subtraction (-1) operation is repeated until the value becomes [1] (DEC1 is generated). When the value becomes [1] (DEC1 is generated), the correction is performed. Frequency division output corresponding to the value (UPREG → DE
C) is output.

Step 3: Based on this divided output, the data (upper n bits) of the prescale upper port circuit (PRE UP) (5) is moved to the prescale upper register circuit (UP REG) (6), and this data is decremented. The circuit (DEC) (8 is preset, the subtraction (-1) is performed, and the value is returned to the prescale upper register circuit (UP REG) (6).
The value is determined, and the operation from step 2 onward is repeated until the value of the decrementer circuit (DEC) (8) is [1].
When (DEC1 is generated), the frequency division output (FFREG → DEC) corresponding to the upper n bits is output.

Step 4: Based on the frequency division output, the data (correction value) of the second digit weight correction register circuit (FF REG) (4) is preset in the decrementer circuit (DEC) (8), and this preset value is set. The subtraction (-1) is performed as an initial value, and the subtraction (-1) operation is repeated until the value becomes [1] (DEC1 is generated). When the value becomes [1] (DEC1 is generated), the correction is performed. Frequency division output corresponding to the value (UPREG → DE
C) is output.

Step 5: Based on this frequency division output, the data of the prescale upper register circuit (UP REG) (6) is preset in the decrementer circuit (DEC) (8) and subtracted (-1) to pre-set the value. Scale upper register circuit (UP REG)
While returning to (6), the [0] (DEC0) value is output.

By this output, the prescale upper port circuit (PRE
UP) (5) data (upper n bits) is transferred to the prescale upper register circuit (UP REG) (6).

Step 6: Based on this output, the timer register circuit (TMR
REG) (2) data (n-bit timer value) is preset in the decrementer circuit (DEC) (8) and subtracted (-
1) and set the value to the timer register circuit (TMR R
EG) (2), determine the value, and repeat the operation from step 1 onwards, and when the value of the decrementer circuit (DEC) (8) becomes [0] (DEC0 occurs), the timer output (INT) is obtained.

Although the examples considered to be typical of the present invention have been described above, the present invention is not necessarily limited to these examples, and has the constitutional requirements referred to in the present invention, and achieves the object referred to in the present invention. However, it can be appropriately modified and implemented within a range having the following effects.

<Effects of the Invention> The present invention combines the frequency division output corresponding to the upper n bits and the lower order n bits of the 2n-bit prescale value and the frequency division output corresponding to the digit weight of the least significant bit of the upper n bits. The 2n-bit prescale value is realized by each programmable counter means that obtains the frequency-divided output corresponding to the 2n-bit prescale value and further obtains the frequency-divided output corresponding to the timer value based on the frequency-divided output. The prescaler decrementer circuit and the register circuit may be n-bit ones, and the circuit scale and the circuit layout scale are halved, which has a practical advantage of being inexpensive.

[Brief description of drawings]

FIG. 1 is a block diagram showing the configuration of a typical embodiment of the timer device of the present invention, FIGS. 2 (a) and 2 (b) are flow charts showing the same operation, FIG. 3 is the same timing chart, and FIG. FIG. 4 is a block diagram showing a configuration of a conventional timer device.

Claims (1)

[Claims] 1. An n-bit decrementer means, a prescale upper port means for holding upper n bits of a 2n-bit prescale value, and a prescale lower port means for holding lower n bits of a 2n-bit prescale value. Timer port means for holding an n-bit timer value, lower n bits of the 2n-bit prescale value are preset in the decrementer means, and the preset clock is used as an initial value to count the basic clock, First programmable counter means for obtaining a first divided output corresponding to the lower n bits of the scale value, and the lowermost n bits of the upper n bits of the 2n-bit prescale value based on the first divided output A correction value corresponding to the weight of the digit of the bit is preset in the decrementer means, and the preset value is Second programmable counter means for counting the basic clock as the period value to obtain a second divided output corresponding to the digit weight of the least significant bit of the high order n bits of the prescale value; Based on the circular output, the upper n bits of the 2n-bit prescale value are preset in the decrementer means, and the preset value is used as an initial value for the second
Third programmable counter means for obtaining the third frequency division output corresponding to the upper n bits of the prescale value by counting the frequency division output of the prescale value; and the n bits based on the third frequency division output. Fourth programmable counter means for presetting the timer value of No. 1 to the decrementer means, counting the third divided output with this preset value as an initial value, and obtaining a fourth divided output corresponding to the timer value. And a timer device characterized in that the fourth frequency division output is used as a timer output.