JPH0691074B2 - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPH0691074B2 JPH0691074B2 JP60067717A JP6771785A JPH0691074B2 JP H0691074 B2 JPH0691074 B2 JP H0691074B2 JP 60067717 A JP60067717 A JP 60067717A JP 6771785 A JP6771785 A JP 6771785A JP H0691074 B2 JPH0691074 B2 JP H0691074B2
- Authority
- JP
- Japan
- Prior art keywords
- film
- silicon nitride
- semiconductor device
- sin
- assg
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
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Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
Description
【発明の詳細な説明】 〔産業上の利用分野〕 本発明は、半導体基板に複数個のMOS FET等の素子が形
成された半導体装置に関する。The present invention relates to a semiconductor device in which a plurality of elements such as MOS FETs are formed on a semiconductor substrate.
〔発明の概要〕 本発明は、半導体基板に形成した保護膜上に、不純物含
有シリケート・ガラス膜および水素を含む窒化シリコン
膜を少なくとも有する半導体装置において、 保護膜と、水素を含む窒化シリコン膜との間に、５重量
％以下のＰ（燐）を含むシリケート・ガラス膜と窒化シ
リコン膜とを設けることにより、 半導体基板と保護膜との界面に存在する電荷の密度を低
下させるとともに、Al（アルミニウム）系配線材の腐食
を防止するものである。SUMMARY OF THE INVENTION The present invention is a semiconductor device having at least an impurity-containing silicate glass film and a silicon nitride film containing hydrogen on a protective film formed on a semiconductor substrate, wherein a protective film and a silicon nitride film containing hydrogen are provided. By providing a silicate glass film containing 5% by weight or less of P (phosphorus) and a silicon nitride film between them, the density of charges existing at the interface between the semiconductor substrate and the protective film is reduced and Al ( This is to prevent corrosion of the aluminum) wiring material.
例えば、ＮチャンネルMOS型FET（電界効果トランジス
タ）あるいはバイポーラ・トランジスタを有するIC（集
積回路）やLSI（大規模集積回路）等の半導体装置にお
いて、半導体基板上にAsSG（砒素シリケート・ガラス）
あるいはSbSG（アンチモン・シリケート・ガラス）等よ
り成るリフロー膜を形成し、さらにこのリフロー膜上に
直接あるいはSiO2層を介してプラズマSi（窒化シリコ
ン）膜を形成した構造が知られている。For example, in a semiconductor device such as an IC (integrated circuit) or an LSI (large-scale integrated circuit) having an N-channel MOS type FET (field effect transistor) or a bipolar transistor, AsSG (arsenic silicate glass) is formed on a semiconductor substrate.
Alternatively, a structure is known in which a reflow film made of SbSG (antimony silicate glass) or the like is formed, and a plasma Si (silicon nitride) film is further formed on this reflow film directly or through an SiO 2 layer.
すなわち、第３図はこのような半導体装置の一例とし
て、ＮチャンネルMOS型FET素子30,30を有するICあるい
はLSIの一部を示している。この第３図において、例え
ばＮ型シリコン半導体基板31の表面に臨んでＰ型領域32
が形成され、このＰ型領域32の表面に臨んで上記FET素
子30,30のソース、ドレイン領域となるN+型領域が拡散
法等により形成されている。ここで、Ｐ型領域32の表面
には選択酸化法等によりSiO2の絶縁保護膜33を形成し、
この保護膜33上にPoLy−Si（多結晶シリコン）より成る
ゲート電極34や配線電極35等を形成した後、PSG（燐シ
リケート・ガラス）,BPSG（ホウ素、燐シリケート・ガ
ラス）,AsSG（アンチモン・シリケート・ガラス）のリ
フロー膜36を形成している。この例えばAsSGのリフロー
膜36は、比較的低温でリフロー処理が行え、Al（アルミ
ニウム）電極35等を形成したときのAlの腐蝕やマイグレ
ーションによる悪影響が少く配線の信頼性が高い等の特
長を有している。次に、AsSGリフロー膜36上に、必要に
応じてAl電極37等を形成した後、表面安定化（パシベー
ション）用のSiN（窒化シリコン）膜38をプラズマCVD法
により被着形成する。このプラズマSiN膜38は、耐湿性
や化学的安定性あるいは物理的安定性に優れ、また比較
的低温で被着形成が行えるという利点を有している。That is, FIG. 3 shows a part of an IC or LSI having N-channel MOS type FET elements 30, 30 as an example of such a semiconductor device. In FIG. 3, for example, the P-type region 32 is exposed to the surface of the N-type silicon semiconductor substrate 31.
Are formed, and N + type regions serving as the source and drain regions of the FET elements 30 and 30 are formed by a diffusion method or the like so as to face the surface of the P type region 32. Here, an insulating protective film 33 of SiO 2 is formed on the surface of the P-type region 32 by a selective oxidation method or the like,
After forming the gate electrode 34 and the wiring electrode 35 made of PoLy-Si (polycrystalline silicon) on the protective film 33, PSG (phosphorus silicate glass), BPSG (boron, phosphorus silicate glass), AsSG (antimony) are formed. A silicate glass reflow film 36 is formed. For example, the reflow film 36 of AsSG has features such that the reflow process can be performed at a relatively low temperature, the adverse effect of Al corrosion and migration when forming the Al (aluminum) electrode 35 is small, and the reliability of wiring is high. is doing. Next, an Al electrode 37 and the like are formed on the AsSG reflow film 36 as needed, and then a SiN (silicon nitride) film 38 for surface stabilization (passivation) is deposited by plasma CVD. This plasma SiN film 38 has the advantages that it is excellent in moisture resistance, chemical stability, and physical stability, and that it can be deposited and formed at a relatively low temperature.
ところで、このようなAsSGリフロー膜36上にプラズマSi
N膜38を積層形成した構造において、いわゆるフォーミ
ング・アニール処理を例えば350〜450℃の温度範囲で30
分〜120分程度行うと、基板のSiとSiO2絶縁保護膜33と
の界面に存在する電荷の密度ＱSSが著るしく増大し、特
に各FET素子30,30間の素子分離領域39の界面電荷密度Ｑ
SSが増加することによって、素子間の絶縁分離が有効に
行えなくなる。すなわち、通常のＱSSの値は１〜５×10
10cm-2程度であるのに対し、上記構成におけるＱSSの値
は１〜５×1212cm-2にも達し、素子分離領域39が略導通
状態に近くなってしまう。By the way, plasma Si is formed on the AsSG reflow film 36.
In the structure in which the N film 38 is formed by stacking, so-called forming / annealing treatment is performed in a temperature range of, for example, 350 to 450 ° C.
After about 10 minutes to 120 minutes, the density Q SS of the electric charges existing at the interface between the Si of the substrate and the SiO 2 insulating protective film 33 is remarkably increased, and especially the element isolation region 39 between the FET elements 30 and 30 is increased. Interface charge density Q
The increase in SS makes it impossible to effectively isolate the elements. That is, the normal value of Q SS is 1 to 5 × 10
While the value of Q SS in the above structure reaches 1 to 5 × 12 12 cm -2 while it is about 10 cm -2 , the element isolation region 39 becomes close to a conductive state.
これは、プラズマSiN膜38〔Ｈ〕（水素）を５〜20atm％
と比較的多量に含んでいる点、および上記リフロー膜36
となるAsSGあるいはSbSG等をCVD形成するときのソース
・ガスにAsCl2やSbCl3等のCl（塩素）系ガスを用いてい
る点が原因となって、上記アニール処理時に、プラズマ
SiN膜38の〔Ｈ〕が移動し、途中のリフロー膜36に捕え
られることなくSi（基板）−SiO2（保護膜）界面にまで
到達して電荷として蓄積され、いわゆるフィールド反転
現象が生じて上記素子分離領域のSi−SiO2界面に擬似的
なＮチャンネルが形成されてしまうからと考えられてい
る。This is plasma SiN film 38 [H] (hydrogen) 5-20 atm%
And the above-mentioned reflow film 36
Due to the fact that a Cl (chlorine) -based gas such as AsCl 2 or SbCl 3 is used as the source gas when CVD-forming AsSG or SbSG, etc.
The [H] of the SiN film 38 moves, reaches the Si (substrate) -SiO 2 (protective film) interface without being caught by the reflow film 36 on the way, and is accumulated as electric charge, causing a so-called field inversion phenomenon. It believed because pseudo N channel Si-SiO 2 interface of the element isolation region is formed.
なお、光CVD法やスパッタリング等により被着形成され
たSiN（窒化シリコン）膜にも水素が含まれており、上
述したプラズマSiN膜と同様な悪影響が生じ得る。It should be noted that the SiN (silicon nitride) film deposited and formed by the photo-CVD method or sputtering also contains hydrogen, and the same adverse effect as that of the plasma SiN film described above may occur.
また、配線電極にAl（アルミニウム）を用いる場合に
は、層間絶縁膜によるAl腐食を防止することが必要とさ
れる。When Al (aluminum) is used for the wiring electrode, it is necessary to prevent Al corrosion due to the interlayer insulating film.
本発明は、このような実情に鑑み、AsSG等のシリケート
・ガラスによりリフロー膜と、水素を含む窒化シリコン
膜とが積層形成された半導体装置における基板と保護膜
との界面の電荷密度の増大を抑えるとともに、Al配線電
極等の腐食を防止可能な半導体装置の提供を目的とす
る。In view of such a situation, the present invention aims to increase the charge density at the interface between a substrate and a protective film in a semiconductor device in which a reflow film made of silicate glass such as AsSG and a silicon nitride film containing hydrogen are stacked. An object of the present invention is to provide a semiconductor device capable of suppressing corrosion and preventing corrosion of Al wiring electrodes and the like.
上述の問題点を解決するために、本発明の半導体装置
は、半導体基板に形成した保護膜上に、少なくとも一層
の不純物を含むシリケート・ガラス膜と、水素を含む窒
化シリコン膜が順次積層形成されてなる半導体装置にお
いて、上記保護膜とシリケート・ガラス膜の間に窒化シ
リコン膜が形成されるとともに、この窒化シリコン膜と
上記水素を含む窒化シリコン膜の間に燐の含有量が５重
量％以下のシリケート・ガラス膜が少なくとも一層形成
されていることを特徴としている。In order to solve the above-mentioned problems, in a semiconductor device of the present invention, at least one layer of a silicate glass film containing impurities and a silicon nitride film containing hydrogen are sequentially formed on a protective film formed on a semiconductor substrate. In the semiconductor device formed as described above, a silicon nitride film is formed between the protective film and the silicate glass film, and the phosphorus content is 5% by weight or less between the silicon nitride film and the silicon nitride film containing hydrogen. Is characterized in that at least one silicate glass film is formed.
保護膜と窒化シリコン膜との間に、５重量％以下のPSG
膜とSiN膜とを設けたことにより、半導体基板と保護膜
との界面に存在する電荷密ＱSSの増大を防止できるとと
もに、Al（アルミニウム）配線電極の腐食も防止でき
る。5% by weight or less of PSG between the protective film and the silicon nitride film
By providing the film and the SiN film, it is possible to prevent an increase in the charge density Q SS existing at the interface between the semiconductor substrate and the protective film and also prevent corrosion of the Al (aluminum) wiring electrode.
以下、本発明に係る好ましい実施例について、図面を参
照しながら説明する。Hereinafter, preferred embodiments of the present invention will be described with reference to the drawings.
第１図は本発明の第１の実施例の要部を示す概略断面図
であり、Si半導体基板１のＰ型領域の表面に臨んで、Ｎ
型のソース領域2Sおよびドレイン領域2Dが例えば拡散法
等によりそれぞれ複数組形成されている。これらのソー
ス領域2Sとドレイン領域2Dとで挾まれた能動領域の上方
には、膜厚の薄いSiO2等より成るゲート絶縁膜3Gを介し
てPoly−Si（多結晶シリコン）より成るゲート電極4Gが
形成されている。ここで、ゲート絶縁膜3Gについては、
Si基板表面に対して例えば選択酸化法を施すことによ
り、他の部分の膜厚の厚い（例えば3000〜8000Å程度
の）フィールド絶縁膜3Fとともに形成すればよい。フィ
ールド絶縁膜3Fには、必要に応じて例えばPoly−Siより
成る配線電極4Wを形成しておけばよい。これらのゲート
絶縁膜3Gおよびフィールド絶縁膜3Fより成る絶縁保護膜
３上には、SiN（窒化シリコン）薄膜５がプラズマCVD法
や減圧CVD法等により被着形成される。このSiN薄膜５
は、約100Å程度あるいはそれ以上で、ストレス等を考
慮して500Å以下の厚みとすることが好ましい。このSiN
薄膜５上には、AsSG（砒素シリケート・ガラス）が例え
ばCVD法により3000〜8000Å程度の厚みに被着形成さ
れ、その後、例えば900℃、10分間程度の加熱によるリ
フロー処理（あるいはガラス・フロー処理）が施され
て、AsSGリフロー膜６が形成されている。このリフロー
処理は、上記加熱時のガラスの流動現象を利用して、エ
ッチング縁部等の段部の傾斜をゆるくし、断線等を防止
するためのものである。FIG. 1 is a schematic cross-sectional view showing the main part of the first embodiment of the present invention.
A plurality of types of source regions 2S and drain regions 2D are formed by, for example, a diffusion method. Above the active region sandwiched by the source region 2S and the drain region 2D, a gate electrode 4G made of Poly-Si (polycrystalline silicon) is provided via a gate insulating film 3G made of thin SiO 2 etc. Are formed. Here, regarding the gate insulating film 3G,
The surface of the Si substrate may be formed together with the field insulating film 3F having a large film thickness (for example, about 3000 to 8000Å) by subjecting the surface of the Si substrate to, for example, a selective oxidation method. A wiring electrode 4W made of, for example, Poly-Si may be formed on the field insulating film 3F, if necessary. A SiN (silicon nitride) thin film 5 is deposited and formed on the insulating protective film 3 including the gate insulating film 3G and the field insulating film 3F by a plasma CVD method, a low pressure CVD method or the like. This SiN thin film 5
Is about 100Å or more, and preferably 500Å or less in consideration of stress and the like. This SiN
AsSG (arsenic silicate glass) is deposited on the thin film 5 by CVD, for example, to a thickness of about 3000 to 8000Å, and then reflow treatment (or glass flow treatment) is performed by heating at 900 ° C. for about 10 minutes. ) Is applied to form the AsSG reflow film 6. This reflow treatment is to prevent the disconnection and the like by making the inclination of the step portion such as the etching edge portion gentle by utilizing the flow phenomenon of the glass at the time of heating.
なお、例えばこのリフロー処理前の上記AsSG被着形成後
には、ソース、ドレイン各領域2S,2Dに対するコンタク
ト用の窓開け処理が施され、ソース、ドレイン各電極7
S,7Dが形成されることにより、ＮチャンネルMOS型FET
（電界効果トランジスタ）の素子が形成されるわけであ
る。Note that, for example, after the AsSG deposition before the reflow treatment, a window opening process for contact with the source and drain regions 2S and 2D is performed, and the source and drain electrodes 7 are formed.
By forming S and 7D, N-channel MOS type FET
The element of (field effect transistor) is formed.
次に、AsSG膜６を例えば層間絶縁膜として用い、このAs
SG膜６上に必要に応じてAl（アルミニウム）等より成る
配線電極8aを形成した後、PSG（燐シリケート・ガラ
ス）を例えばCVD法等により被着形成することにより、P
SG膜９を形成している。このときのPSG膜９の厚みは300
0〜8000Åとしており、Ｐ（燐）の濃度は５重量％以下
としている。Next, the AsSG film 6 is used as, for example, an interlayer insulating film, and the As
After the wiring electrode 8a made of Al (aluminum) or the like is formed on the SG film 6 as required, PSG (phosphorus silicate glass) is deposited by, for example, the CVD method to form P
The SG film 9 is formed. The thickness of the PSG film 9 at this time is 300
It is set to 0 to 8000Å, and the concentration of P (phosphorus) is set to 5% by weight or less.
次に、PSG膜９上に、必要に応じてAl等より成る配線電
極8bを形成した後、プラズマCVD法によりSiN（窒化シリ
コン）膜10を例えば7500〜12000Å（0.75〜1.2μｍ）程
度の厚さに被着形成する。Next, a wiring electrode 8b made of Al or the like is formed on the PSG film 9 if necessary, and then a SiN (silicon nitride) film 10 is formed by a plasma CVD method to a thickness of, for example, 7500 to 12000Å (0.75 to 1.2 μm). It is adhered and formed.
このように、最上層のプラズマSiN膜10とSiO2等の絶縁
保護膜３との間に、Ｐ（燐）濃度が５重量％以下のPSG
膜９との膜厚が約100A程度から500Å以下の範囲のSiN薄
膜５とを設けた構造によれば、絶縁保護膜３のフィール
ド絶縁膜3FとSi基板１との界面電荷密度ＱSSの増大を抑
制することができるのみならず、PSG膜９のＰ濃度が比
較的低いため、Al配線電極8a,8b等の腐食を防止するこ
とができる。また、PSG膜を用いているため、CVD形成し
たSiO2膜に比べて、ストレスの大幅な低減ができ、減圧
CVD法によるPSG膜の形成の導入も可能となって、多層配
線に好適である。As described above, PSG having a P (phosphorus) concentration of 5 wt% or less is provided between the uppermost plasma SiN film 10 and the insulating protective film 3 such as SiO 2.
According to the structure in which the film 9 and the SiN thin film 5 having a film thickness of about 100 A to 500 Å or less are provided, the interface charge density Q SS between the field insulating film 3F of the insulating protective film 3 and the Si substrate 1 is increased. In addition, the P concentration of the PSG film 9 is relatively low, so that corrosion of the Al wiring electrodes 8a, 8b and the like can be prevented. In addition, since the PSG film is used, stress can be significantly reduced compared to the SiO 2 film formed by CVD, and the pressure can be reduced.
Since the formation of the PSG film by the CVD method can be introduced, it is suitable for multilayer wiring.
次に、第２図は本発明の第２の実施例の要部を示す概略
断面図であり、Si基板11上に熱酸化法により形成された
SiO2より成る絶縁保護膜12上には、Poly−Si等より成る
配線電極13が形成され、この上に膜厚が100Å程度以上5
00Å以下のSiN薄膜14がプラズマCVD法や減圧CVD法等に
より被着形成される。このSiN薄膜14上にＰ（燐）濃度
が５重量％以下のPSG膜15が1000Å〜3000Å程度の厚み
に被着形成され、このPSG膜15上にAsSG膜16が3000Å〜8
000Å程度の厚みに被着形成され、リフロー処理され
る。AsSGリフロー膜16上には、必要に応じてAl等の配線
電極17を形成した後、Ｐ（燐）濃度が５重量％以下のPS
G膜18を被着形成する。このPSG膜18上に、必要に応じて
Al等の配線電極19を形成した後、プラズマCVD法によりS
iN膜20を7500Å〜12000Å（0.75μｍ〜1.2μｍ）程度の
膜厚に被着形成する。Next, FIG. 2 is a schematic sectional view showing an essential part of a second embodiment of the present invention, which is formed on the Si substrate 11 by a thermal oxidation method.
A wiring electrode 13 made of Poly-Si or the like is formed on the insulating protective film 12 made of SiO 2 , and a film thickness of 100 Å or more is formed on the wiring electrode 13.
A SiN thin film 14 of 00 Å or less is deposited and formed by a plasma CVD method, a low pressure CVD method, or the like. A PSG film 15 having a P (phosphorus) concentration of 5 wt% or less is deposited on the SiN thin film 14 to a thickness of about 1000Å to 3000Å, and an AsSG film 16 on the PSG film 15 is 3000Å to 8
It is deposited to a thickness of about 000Å and reflowed. After forming a wiring electrode 17 of Al or the like on the AsSG reflow film 16 as needed, PS with a P (phosphorus) concentration of 5 wt% or less is formed.
The G film 18 is deposited. On this PSG film 18, if necessary
After forming the wiring electrode 19 such as Al, S by the plasma CVD method
The iN film 20 is deposited to a film thickness of about 7500Å to 12000Å (0.75 μm to 1.2 μm).
この第２の実施例においても、前述した第１の実施例と
同様に、絶縁保護膜12とSi基板11との界面の電荷密度の
増大を抑制でき、Al配線電極17,18の腐食を防止でき
る。Also in the second embodiment, similarly to the above-described first embodiment, it is possible to suppress the increase of the charge density at the interface between the insulating protective film 12 and the Si substrate 11, and prevent the corrosion of the Al wiring electrodes 17 and 18. it can.
なお、本発明は、上述の実施例のみに限定されるもので
はなく、リフロー膜としてはAsSG膜以外にもPSG膜、BPS
G（ホウ素・燐シリケート・ガラス）膜、SbSG（アンチ
モン・シリケート・ガラス）膜や、これらの多層構造を
用いることができる。また、最上層のプラズマSiN膜の
代りに、光CVD法やスパッタリング法等により形成され
た水素を含むSiN膜を用いた場合にも本発明を適用でき
ることは勿論である。The present invention is not limited to the above-described embodiments, and the reflow film may be a PSG film, a BPS film or a BPS film other than the AsSG film.
A G (boron / phosphorus silicate / glass) film, an SbSG (antimony / silicate / glass) film, or a multilayer structure of these can be used. In addition, the present invention can of course be applied to a case where a SiN film containing hydrogen formed by a photo CVD method, a sputtering method or the like is used instead of the uppermost plasma SiN film.
本発明の半導体装置によれば、半導体基板と絶縁保護膜
との間の界面電荷密度ＱSSの増大を抑制すると同時に、
Al配線電極の腐食を防止でき、また、CVD法によるSiO2
膜を層間絶縁膜とする場合に比べてストレスの大幅な低
減を図ることができる。また、減圧CVD法によるPSG膜形
成工程の導入も可能となり、多層配線に適用して好まし
いものである。According to the semiconductor device of the present invention, at the same time as suppressing the increase in the interface charge density Q SS between the semiconductor substrate and the insulating protective film,
Corrosion of Al wiring electrodes can be prevented, and SiO 2 by CVD method
Stress can be significantly reduced as compared with the case where the film is an interlayer insulating film. Further, it becomes possible to introduce a PSG film forming step by a low pressure CVD method, which is preferable when applied to multilayer wiring.
第１図は本発明の第１の実施例の要部を示す概略断面
図、第２図は本発明の第２の実施例の要部を示す概略断
面図、第３図は従来例を示す概略断面図である。 1,11……Si基板 3,12……絶縁保護膜 5,14……SiN薄膜 6,16……AsSG膜 9,15,18……PSG膜 8a,8b,17,19……Al配線電極FIG. 1 is a schematic sectional view showing an essential part of a first embodiment of the present invention, FIG. 2 is a schematic sectional view showing an essential part of a second embodiment of the present invention, and FIG. 3 is a conventional example. It is a schematic sectional drawing. 1,11 …… Si substrate 3,12 …… Insulation protection film 5,14 …… SiN thin film 6,16 …… AsSG film 9,15,18 …… PSG film 8a, 8b, 17,19 …… Al wiring electrode
フロントページの続き (56)参考文献 特開 昭50−40635（ＪＰ，Ａ) 特開 昭52−52379（ＪＰ，Ａ) 特開 昭52−68371（ＪＰ，Ａ) 特開 昭53−48474（ＪＰ，Ａ) 特開 昭54−28571（ＪＰ，Ａ) 特公 昭50−1872（ＪＰ，Ｂ１) 特公 昭49−29107（ＪＰ，Ｂ１) 特公 昭48−11669（ＪＰ，Ｂ１)Continuation of the front page (56) Reference JP-A-50-40635 (JP, A) JP-A-52-52379 (JP, A) JP-A-52-68371 (JP, A) JP-A-53-48474 (JP , A) JP 54-28571 (JP, A) JP-B 50-1872 (JP, B1) JP-B 49-29107 (JP, B1) JP-B 48-11669 (JP, B1)
Claims (1)
とも一層の不純物を含むシリケート・ガラス膜と、水素
を含む窒化シリコン膜が順次積層形成されてなる半導体
装置において、 上記保護膜とシリケート・ガラス膜の間に窒化シリコン
膜が形成されるとともに、この窒化シリコン膜と上記水
素を含む窒化シリコン膜の間に燐の含有量が５重量％以
下のシリケート・ガラス膜が少なくとも一層形成されて
いることを特徴とする半導体装置。1. A semiconductor device in which a silicate glass film containing at least one layer of impurities and a silicon nitride film containing hydrogen are sequentially laminated on a protective film formed on a semiconductor substrate. A silicon nitride film is formed between the glass films, and at least one silicate glass film having a phosphorus content of 5% by weight or less is formed between the silicon nitride film and the silicon nitride film containing hydrogen. A semiconductor device characterized by the above.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP60067717A JPH0691074B2 (en) | 1985-03-30 | 1985-03-30 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP60067717A JPH0691074B2 (en) | 1985-03-30 | 1985-03-30 | Semiconductor device |
Related Child Applications (2)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1995304970A Division JP2907765B6 (en) | 1995-10-30 | Semiconductor device | |
| JP12133297A Division JPH1050698A (en) | 1997-05-12 | 1997-05-12 | Semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS61226930A JPS61226930A (en) | 1986-10-08 |
| JPH0691074B2 true JPH0691074B2 (en) | 1994-11-14 |
Family
ID=13352984
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP60067717A Expired - Lifetime JPH0691074B2 (en) | 1985-03-30 | 1985-03-30 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0691074B2 (en) |
Family Cites Families (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5314201B2 (en) * | 1972-07-07 | 1978-05-16 | ||
| US3841726A (en) * | 1973-04-13 | 1974-10-15 | Matthews H & Co | Urn storage assembly |
| JPS5133813B2 (en) * | 1973-08-14 | 1976-09-22 | ||
| JPS5268371A (en) * | 1975-12-05 | 1977-06-07 | Nec Corp | Semiconductor device |
| JPS5252379A (en) * | 1976-07-29 | 1977-04-27 | Sony Corp | Semiconductor device |
| JPS5348474A (en) * | 1976-10-15 | 1978-05-01 | Hitachi Ltd | Electronic parts |
| JPS5428571A (en) * | 1977-08-08 | 1979-03-03 | Hitachi Ltd | Semiconductor device |
| JPS562638A (en) * | 1979-06-21 | 1981-01-12 | Nec Corp | Manufacture of semiconductor device |
| JPS5785246A (en) * | 1980-11-18 | 1982-05-27 | Nippon Denso Co Ltd | Semiconductor device |
| JPS59117133A (en) * | 1982-12-24 | 1984-07-06 | Hitachi Ltd | Semiconductor device |
-
1985
- 1985-03-30 JP JP60067717A patent/JPH0691074B2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JPS61226930A (en) | 1986-10-08 |
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