JP2940316B2 - Semiconductor device and manufacturing method thereof - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly, to a semiconductor device and a method of manufacturing the same in which contact resistance deterioration due to heat treatment during a manufacturing process is prevented.

[0002]

Te is at the p-channel type MOS transistor having BACKGROUND ART p ⁺ -type polysilicon gate electrode, as compared to the p-channel type MOS transistor having an n ⁺ -type polycrystalline silicon gate electrode, more the short channel effect The threshold voltage (V _th ) of the MOS transistor is suppressed.
May be set lower. This is described in, for example, IEE, EEM, Technical, Digest, p418-422 (198).
4), IEEE, IEDM, Technical Di
guest p. 418-422 (1984).

In order to electrically connect a p ⁺ -type impurity diffusion region formed in a semiconductor substrate to a polysilicon wiring, a p ⁺ -type polysilicon film is used as the polysilicon wiring. in use. The p ⁺ -type polycrystalline silicon film has a higher specific resistance than a general metal. Wires and electrodes, since it is formed from a low resistivity material preferably, from p ⁺ polycide film Sekimaku a refractory metal silicide film or the like on a p ⁺ -type polycrystalline silicon film, the wiring and electrodes are formed Sometimes.

The p ⁺ polycide film is made of a high melting point material which does not deteriorate even by heat treatment at a temperature of 900 ° C. or more. Therefore, after the step of forming wirings and electrodes from the p ⁺ polycide film, it is possible to perform a step of forming the BPSG film as an interlayer insulating film and flattening the BPSG film by heat treatment. The semiconductor device manufactured in this manner is described in Japanese Patent Application Laid-Open No. 57-192070.

[0005] Even when a BPSG film is not used as an interlayer insulating film, heat treatment is required after the formation of the p ⁺ polycide film in order to activate the p ⁺ -type impurities. During this heat treatment, the boron concentration may be reduced due to outdiffusion of boron. In order to prevent the boron concentration from decreasing, it is necessary to deposit an insulating film on the p ⁺ polycide film before the heat treatment. This is the case, for example, with the Journal of Vacuum Science
And Technology B, Volume 5, p1674
-1688, 1987; V. ac. Sci. an
d Technol. B, vol. 5 p1674-1
688 1987.

[0006]

However, the above-mentioned prior art has the following problems.

It is known that when the p ⁺ polycide film is heat-treated, boron is agglomerated at the interface between the p ⁺ polycide film and the insulating film covering the film, so that the boron concentration in the p ⁺ polycide film is reduced. . This phenomenon is described in, for example, IEE, EEM, Technical, Digest, p407-410 (198).
5), IEEE, IEDM, Technical Di
guest p407-410 (1985).

Specifically, the decrease in the boron concentration causes the following problems. (1) The p ⁺ polycide film is MO
When used as the gate electrode of the S transistor, the threshold voltage of the MOS transistor fluctuates as the boron concentration decreases. (2) p ⁺ polycide film is p
When used as a wiring contacting the impurity diffusion region, the contact resistance increases as the boron concentration decreases.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and an object of the present invention is to provide a semiconductor device having a polycide wiring whose boron concentration does not decrease by heat treatment, and a method of manufacturing the same. is there.

[0010]

According to the present invention, there is provided a semiconductor device comprising:
A semiconductor device having a polycide wiring on a semiconductor substrate.
Thus, the polycide wiring is formed between the p-type impurity diffusion portion and n
Polycrystalline silicon film having both type impurity diffusion portions
And a high melting point gold formed on the first polycrystalline silicon film.
Metal silicide film and a refractory metal silicide film
Second polycrystalline silicon in which only the formed p-type impurity is diffused.
And a recon film.
You.

In the semiconductor substrate, a p-type impurity diffusion region is provided.
Are formed, and the p-type impurity of the first polycrystalline silicon film is
A pure substance diffusion portion is connected to the p-type impurity diffusion region.
You.

A p-channel type formed on the semiconductor substrate;
A MOS transistor, wherein the p-type impurity is
The diffusion region is the source of the p-channel MOS transistor.
Or drain or drain. Also preferred
In another preferred embodiment, the second polycrystalline silicon
The p-type impurities are spread substantially uniformly in the lateral direction in the recon film.
Has been scattered.

According to another aspect of the present invention, there is provided a semiconductor device on a semiconductor substrate.
An n-channel MOS transistor and a p-channel M
A semiconductor device having an OS transistor, wherein
N composed of an n-type impurity diffusion region formed in a conductive substrate
N-type M having an n-type source and an n-type drain
An OS transistor and a p-type transistor formed in the semiconductor substrate.
-Type source and p-type drain comprising a p-type impurity diffusion region
The p-channel MOS transistor having
A first polycrystalline silicon film, and the first polycrystalline silicon
A refractory metal silicide film formed on the film;
Second polycrystalline silicon formed on point metal silicide film
And a polycide wiring composed of a film.
The crystalline silicon film is formed on the n-type source or the n-type drain.
An n-type impurity diffusion portion connected to the
Source or a p-type impurity connected to the p-type drain
A diffusion portion, and the second polycrystalline silicon film has a p-type
Characterized in that only impurities are diffused.
You.

[0014] The method of manufacturing a semiconductor device of the present invention, a semiconductor
Method of manufacturing semiconductor device having polycide wiring on substrate
Wherein the step of forming the polycide wiring comprises:
Forming a first polycrystalline silicon film on a semiconductor substrate;
A p-type impurity diffusion portion in the first polycrystalline silicon film;
selectively forming an n-type impurity diffusion portion;
1 Refractory metal silicide film formed on polycrystalline silicon film
Performing a second bonding on the refractory metal silicide film.
Forming a polycrystalline silicon film, and the second polycrystalline silicon
Diffusing a p-type impurity over the entire surface of the
It is characterized by the following.

[0015]

According to the semiconductor device of the present invention, since boron agglomeration in the polycide wiring is prevented, the boron concentration in the polycide wiring does not decrease by the heat treatment. As a result, an MO having such a polycide wiring as a gate electrode
The threshold value of the S transistor does not easily change. In addition, stable contact characteristics can be obtained in which the contact resistance between the polycide wiring and the p-type impurity diffusion region does not increase due to the heat treatment.

According to the present invention, there is provided a CMOS semiconductor device in which deterioration of contact characteristics is suppressed by preventing lateral diffusion of impurities in a dual polycide wiring.

[0017]

FIG. 1 shows a partial cross section of a semiconductor device according to the present invention. For simplicity, FIG. 1 shows a single MOS transistor, but the semiconductor device of the present invention is a device in which a plurality of MOS transistors are formed on the same semiconductor substrate. This semiconductor device includes a silicon substrate 1, an element isolation film 2 formed in an element isolation region on the surface of the silicon substrate 1, a MOS transistor formed in each of a plurality of element regions on the surface of the silicon substrate 1, an MO transistor,
Silicon oxide film 9 covering S transistor and BPSG
(Boro-Phospho Silicate Gl
ass) film.

Each MOS transistor is connected to a silicon substrate 1
Source and drain regions (p + type impurity diffusion regions extending from the surface of silicon substrate 1 to the inside) formed therein 3
A gate oxide film (thickness: 10 nm) 4 formed on the silicon substrate 1, a gate electrode 60 formed on the gate oxide film 4, and a silicon oxide film 8 (thickness) formed on the gate electrode 60. : 200 nm). The region shown in FIG. 1 of the silicon substrate 1 is an n-type well region formed on the p-type silicon substrate 1. The MOS transistor may be formed on an n-type silicon substrate.

The source and drain regions 3 are spaced apart from each other at a certain distance (for example, 500 nm) in the horizontal direction in FIG. 1, and the region between the source and drain regions 3 is the channel of the MOS transistor. Forming an area. Gate electrode 60 covers the channel region via gate oxide film 4. According to the potential of the gate electrode 60, a conductive channel for electrically connecting the source and drain regions 3 is formed in the channel region.

The gate electrode 60 of this semiconductor device has p ⁺
Type first polycrystalline silicon film (thickness: 100 nm) 5 and p
A tungsten silicide film (thickness: 200 nm) 6 formed on the ⁺ type polycrystalline silicon film 5 and a p ⁺ type second polycrystalline silicon film (thickness: 100 nm) 7 formed on the tungsten silicide film 6 Has a sandwich-type three-layer polycide structure composed of More specifically, the gate electrode 60 is a part of a long polycide wiring having the above polycide structure. In a semiconductor integrated circuit device having a plurality of MOS transistors, a polycide wiring has a gate electrode portion of each of a group of transistors and a plurality of wiring portions for connecting the gate electrodes. In this specification, an electrode and a wiring having a polycide structure are collectively referred to as a polycide wiring. The width of the polycide wiring of this embodiment is typically 5
It is about 00 nm to 1000 nm. This width may be made smaller for miniaturization.

The thickness of each film constituting the polycide wiring is appropriately set to an arbitrary value according to the design. Further, as the high melting point metal silicide film sandwiched between the first and second polycrystalline silicon films, a film made of another high melting point metal silicide other than tungsten silicide, or a multilayer including a different kind of high melting point metal silicide film It may be a membrane. The important point is that the insulating film is not provided directly on the upper surface of the refractory metal silicide film.

The silicon oxide film 9 prevents impurities (boron and phosphorus) from diffusing into the silicon substrate 1 from the BPSG film 10. A film having a diffusion preventing effect, for example, a silicon nitride film may be used instead of the silicon oxide film 9.

The above-mentioned MOS transistor is a p-channel type MOS transistor. By inverting the impurity conductivity types of the silicon substrate 1 and the source and drain regions 3, an n-channel MOS transistor can be obtained. The polycide wiring can be applied to a CMOS (complementary MOS) semiconductor device. A CMOS semiconductor device is a semiconductor device having a p-channel MOS transistor and an n-channel MOS transistor on the same semiconductor substrate. More specifically, the CMOS semiconductor device has, for example, a p-type silicon substrate and an n-type well formed therein,
An n-channel MOS transistor formed in a p-type silicon substrate and a p-channel MOS transistor formed in an n-type well are provided.

Since the semiconductor device of FIG. 1 has the p ⁺ -type second polycrystalline silicon film between the tungsten silicide film 6 and the silicon oxide film 8, the upper surface of the tungsten silicide film 6 and the silicon oxide film 8 The main feature is that they are not in direct contact with. FIG. 16 shows a boron concentration distribution in a multilayer structure including a silicon oxide film, a polycrystalline silicon film, a tungsten silicide film, and a silicon oxide film. In other words, the boron concentration distribution in a normal two-layer polycide structure sandwiched by a silicon oxide film and a polycide structure composed of a polycrystalline silicon film and a tungsten silicide film on the polycrystalline silicon film is shown. Have been. As shown in FIG. 16, the boron concentration distribution has a peak at the interface between the silicon oxide film and the tungsten silicide film. This indicates that boron is aggregated at the interface. Aggregation of boron causes a decrease in the boron concentration in the tungsten silicide film and the polycrystalline silicon film. That is, the interface between the tungsten silicide film and the polycrystalline silicon film functions as a sink for "absorbing" boron for the boron in the polycide wiring.

On the other hand, no boron aggregation occurs at the interface between the tungsten silicide film and the polycrystalline silicon film. This is because when the crystal grains of the tungsten silicide film grow by the heat treatment, a mismatch occurs between the tungsten silicide film and the silicon oxide film.
It is considered that such a mismatch hardly occurs between the tungsten silicide film and the polycrystalline silicon film.

The concentration distribution shown in FIG. 16 indicates that the sample having the above structure has a secondary ion mass spectrometry (S
IMS). The sample is
It was fabricated as follows. First, after a silicon oxide film and a polycrystalline silicon film were sequentially formed on a silicon substrate, boron ions were implanted into the polycrystalline silicon film. After a tungsten silicide film and a silicon oxide film were sequentially formed on the polycrystalline silicon film, a heat treatment was performed at 900 ° C. for 30 minutes.
By this heat treatment, boron in the polycrystalline silicon film becomes
It diffuses to the interface between the tungsten silicide film and the silicon oxide film.

According to the embodiment of the present invention shown in FIG.
The area of the interface between the tungsten silicide film 6 and the silicon oxide film 9 (the area of the side surface of the tungsten silicide film 6) is compared with the area of the interface between the tungsten silicide film 6 and the silicon oxide film 8 in the conventional semiconductor device. And so small that it is virtually negligible. In this embodiment, since the area of the interface where boron easily aggregates (the interface between the silicide and the insulating film) is significantly reduced, the p ⁺ type first
Aggregation of boron in the polycrystalline silicon film 7 and the tungsten silicide film 8 at the interface is prevented. Therefore, a decrease in the boron concentration in the wiring due to the aggregation of boron is prevented.

As another preferred embodiment, not only the upper surface of the tungsten silicide film 6 but also its side surface may be covered with the p-type second polycrystalline silicon film 6. In such an embodiment, since the tungsten silicide film 6 is completely covered with the polycrystalline silicon film, there is no interface between the tungsten silicide and the silicon oxide film. As a result, boron aggregation due to such an interface does not occur, and a decrease in the boron concentration inside the wiring due to the aggregation is prevented.

With reference to FIGS. 2A to 2C, a method of manufacturing the semiconductor device will be described below. First, an element isolation film 2 is formed in an element isolation region on the surface of a silicon substrate 1 by a known local oxidation (LOCOS) method. LOCO
The element isolation film may be formed by a method other than the S method. A region where the element isolation film 2 is not formed is an element region. By oxidizing the surface of each element region of the silicon substrate 1, a gate oxide film 4 is formed on each element region.

After a polycrystalline silicon film is deposited so as to cover the gate oxide film 4 by a low pressure chemical vapor deposition (LPCVD) method, as shown in FIG. And ions of boron as a p-type impurity are accelerated at an energy of 20 keV and a dose of 6 × 10 ¹⁵ cm.
^{At -2} , inject. Thus, the p ⁺ -type first polycrystalline silicon film 5 is formed.

Next, as shown in FIG. 2 (b), p ⁺
Tungsten silicide film 6 on type polycrystalline silicon film 5
Is deposited, another polycrystalline silicon film is deposited. Boron ions are implanted into the polycrystalline silicon film at an acceleration energy of 20 keV and a dose of 6 × 10 ¹⁵ cm ⁻² . Thus, the p ⁺ -type second polycrystalline silicon film 7 is formed on the tungsten silicide film 6.

Next, a silicon oxide film 8 is deposited on the p ⁺ -type second polycrystalline silicon film 7. A multilayer film including the first polycrystalline silicon film 5, the tungsten silicide film 6, the second polycrystalline silicon film 7, and the silicon oxide film 8 is patterned into a desired wiring shape using a known lithography and etching technique. Thus, as shown in FIG. 2C, a polycide wiring (gate electrode 60) composed of three layers of the first polysilicon film 5, the tungsten silicide film 6, and the second polysilicon film 7 is obtained.

Then, using the element isolation film 2 and the gate electrode 60 as a mask, boron is implanted into the element region of the silicon substrate 1 at an acceleration energy of 10 keV and a dose of 6 × 10 ¹⁵ cm ⁻² . The region into which boron is implanted becomes the source and drain regions 3 of the MOS transistor by a subsequent annealing process. Since a region serving as a channel of the MOS transistor is covered with the gate electrode 60, boron is not implanted into that region. Thus, the channel region and the source and drain regions 3 are
It is formed in a self-aligned manner. The silicon oxide film 8 is
Although it can function as an etching mask when etching the second polycrystalline silicon film 7 and the like, it is not an essential element for the present invention.

Note that a sidewall spacer may be formed on the side surface of the gate electrode 60 before performing the ion implantation for forming the source and drain regions 3. Before forming the sidewall spacer, ion implantation for forming the LDD region may be performed. By forming the LDD region, the short channel effect can be suppressed, so that the size of the MOS transistor can be further reduced. The reduction in the size of the MOS transistor is useful for increasing the operation speed of the transistor and improving the integration of a semiconductor device including a large number of such transistors.

Next, after depositing a silicon oxide film 9 so as to cover the transistor, a BPS
A G film 10 is deposited. In order to flatten the surface of the BPSG film 10 and simultaneously activate the impurities, annealing at 900 ° C. is performed in a nitrogen atmosphere for 30 minutes. This annealing condition can be set arbitrarily as appropriate. After a contact hole (not shown) is formed at a predetermined position of the BPSG film 10, a wiring connected to the polycide wiring and the source and drain regions 3 is formed on the BPSG film 10.

According to this embodiment, since the boron concentration in the polycide wiring (gate electrode 60) due to the heat treatment is prevented from decreasing, the threshold value of the MOS transistor does not change. The MOS transistor in this embodiment can be used as a switching transistor in a memory cell included in a semiconductor storage device such as a DRAM. In other words, the above 3
A polycide wiring having a layer structure can be used as a word line of a DRAM.

(Embodiment 2) FIG. 3 shows a partial cross section of another embodiment of the present invention. In the semiconductor device shown in FIG. 1, a polycide wiring having a three-layer structure is used as a gate electrode of a MOS transistor and a wiring for connecting them. A polycide wiring having a layer structure is used as a wiring that contacts a p-type impurity diffusion region in a semiconductor substrate. The polycide wiring shown in FIG. 3 can be used, for example, as a bit line of a DRAM.

The present semiconductor device comprises a silicon substrate (in which n-type impurities are diffused) 1, an element isolation film 2 formed in an element isolation region on the surface of the silicon substrate 1, and a plurality of elements on the surface of the silicon substrate 1. A p-type impurity diffusion region 33a formed in each of the element regions; an interlayer insulating film 11 formed on the silicon substrate 1; a contact hole 12 formed in the interlayer insulating film 11; And a polycide interconnection 61 which is formed and contacts the p-type impurity diffusion region 33a via the contact hole 12.

In this embodiment, the polycide wiring 61 is formed of a p ⁺ -type first polycrystalline silicon film (thickness: 100 nm) 13
A tungsten silicide film (thickness: 200 nm) 14 formed on the ⁺ type polycrystalline silicon film 13 and a p ⁺ type second polycrystalline silicon film (thickness: 200 nm) 15 formed on the tungsten silicide film 14. have.

The semiconductor device further includes a silicon oxide film 16 formed on the interlayer insulating film 11 so as to cover the polycide wiring 61, and a silicon oxide film 16 formed on the silicon oxide film 16
And a PSG film 17.

According to the present embodiment, the polycide wiring 61
Are the tungsten silicide film 14 and the silicon oxide film 1
6, the boron concentration in the polycide wiring 61 does not decrease even after the heat treatment. As a result, diffusion of boron from the p-type impurity diffusion region 33a in the silicon substrate 1 to the polycide wiring 61 is suppressed. Thus, a decrease in the boron concentration in the p-type impurity diffusion region 33a in the silicide substrate 1 and the polycrystalline silicon film 13 is prevented. As described above, since the boron concentration in the p-type impurity diffusion region 33a and the polycrystalline silicon film 13 does not decrease, the contact resistance between the polycide wiring and the p-type impurity diffusion region 33a is kept low.

Hereinafter, a method for manufacturing the semiconductor device will be described. First, an element isolation film 2 is formed in an element isolation region on the surface of a silicon substrate 1. A region where the element isolation film 2 is not formed is an element region. Thereafter, using the element isolation film 2 as a mask, boron is implanted into the element region of the silicon substrate 1 at an acceleration energy of 10 keV and a dose of 6 × 10 ¹⁵ cm ⁻² . The region into which boron is implanted becomes a p-type impurity diffusion region 33a by a later annealing step.

Next, an interlayer insulating film 1 is formed so as to cover the element region.
1 is deposited, and a contact hole 12 is formed in the interlayer insulating film 11 by using a usual lithography and etching technique.
To form After removing the natural oxide film present on the bottom surface of the contact hole 12 by dip etching using an aqueous solution containing hydrofluoric acid, the polycide wiring 6 is formed in the same manner as the method of forming the polycide wiring of the semiconductor device of FIG.
Form one.

After depositing the silicon oxide film 16 and the BPSG film 17, annealing at 900 ° C. is performed in a nitrogen atmosphere for 30 minutes in order to flatten the BPSG film 17 and activate impurities. Next, the BPSG film 17 and the silicon oxide film 16
After forming a contact hole (not shown) reaching the polycide wiring 61 therein, a wiring (not shown) connected to the polycide wiring 61 through this contact hole is formed by BPS.
It is formed on the G film 17.

Before forming the interlayer insulating film 11, M shown in FIG.
An OS transistor may be formed in an element region. In this case, one of the source and drain regions 3 of the MOS transistor in FIG. 1 corresponds to the p-type impurity diffusion region 33a shown in FIG. When a semiconductor device having the MOS transistor of FIG. 1 and the polycide wiring of FIG. 3 is applied to a DRAM, both word lines and bit lines of the DRAM may be formed by a three-layer polycide wiring. As another application example, a DRAM in which the word line is a word line having a conventional structure and only the bit line is the polycide wiring 61 shown in FIG.
There is.

(Embodiment 3) FIG. 4 shows a partial cross section of another embodiment of the present invention. In the semiconductor device of this embodiment, the polycide wiring 61 having a three-layer structure
It is used as a wiring contacting the p-type impurity diffusion region 33a and the n-type impurity diffusion region 33b therein. A polycide wiring that contacts both the p-type impurity diffusion region 33a and the n-type impurity diffusion region 33b in the silicon substrate 1 is called a dual polycide wiring. The dual polycide wiring shown in FIG.
It can be used as a wiring of a semiconductor device.

The semiconductor device according to the present embodiment includes a silicon substrate 1
An n-type well 100 and a p-type well 200 formed in the silicon substrate 1; an element isolation film 2 formed in an element isolation region on the surface of the silicon substrate 1;
A p-type impurity diffusion region 33a formed in the inside, an n-type impurity diffusion region 33b formed in the p-type well 200,
An interlayer insulating film 11 formed on the silicon substrate 1, a contact hole 12 formed in the interlayer insulating film 11, and a p-type impurity diffusion region 33a formed on the interlayer insulating film 11 through the contact hole 12; a polycide interconnection 61 that contacts the n-type impurity diffusion region 33b.

In this embodiment, the polycide wiring 61 is formed of a p ⁺ -type first polycrystalline silicon film (thickness: 100 nm) 13
A tungsten silicide film (thickness: 200 nm) 14 formed on the ⁺ type polycrystalline silicon film 13 and a p ⁺ type second polycrystalline silicon film (thickness: 200 nm) 15 formed on the tungsten silicide film 14. have.

FIG. 4 is a cross-sectional view parallel to the plane along the running direction of the polycide wiring 61.
Although reference numeral 1 indicates that the entire surface of the interlayer insulating film 11 is completely covered, in practice, a wiring-shaped polycide wiring 61 is present on a predetermined region of the interlayer insulating film 11. The semiconductor device further includes another interlayer insulating film 20 formed on the interlayer insulating film 11 so as to cover the polycide wiring 61. This interlayer insulating film 20 may be a laminated film including a BPSG film or the like.

A method for manufacturing the above-described semiconductor device will be described below with reference to FIGS. First, LOC is added to the element isolation region on the surface of the semiconductor substrate 1 where the p-type well 200 and the n-type well 100 are formed by a known method.
The element isolation film 2 is formed by the OS method. As shown in FIG. 5A, in order to form a pn junction in each of the wells 100 and 200, arsenic ions (n-type impurities) are added to the p-type well 200 and BF _{2 is} added to the n-type well 100. Ions (p-type impurities) are selectively implanted, respectively. Arsenic ions and BF ₂ ions are implanted at an acceleration energy of 40 keV and a dose of 6 × 10 ¹⁵ cm ⁻³ , respectively. The region into which arsenic ions are implanted is the n-type impurity diffusion region 33.
b, and the region into which the BF ₂ ions have been implanted becomes the p-type impurity diffusion region 33a.

Next, as shown in FIG.
An interlayer insulating film (thickness: 300 nm) 11 made of a silicon oxide film is deposited on the semiconductor substrate 1 using a CVD method. A contact hole 12 reaching the n-type impurity diffusion region 33b and the p-type impurity diffusion region 33a formed in each of the wells 100 and 200 is formed in the interlayer insulating film 11 using a normal lithography process and an etching process. The contact hole 12 has, for example, a diameter of 600 nm.
It has the size of

Next, a first polycrystalline silicon film (thickness: 50)
nm) 13 is deposited on the interlayer insulating film 11 by the LPCVD method. Thereafter, boron ions are selectively implanted into a part of the first polycrystalline silicon film 13. Boron ions have an acceleration energy of ¹⁵ keV and a dose of 6 × 10 ¹⁵
Injected at cm- ² . Also, the first polycrystalline silicon film 1
The arsenic ions are selectively implanted into the other portions of FIG. Arsenic ions are implanted at an acceleration energy of 80 keV and a dose of 1 × 10 ¹⁵ cm ⁻² . The order of boron ion implantation and arsenic ion implantation may be the reverse of the order performed in this embodiment. The portion of the first polycrystalline silicon film 13 into which boron ions have been implanted corresponds to the n-type well 10.
In addition, the portion in contact with the p-type impurity diffusion region 33a in
In contact with the n-type impurity diffusion region 33b.

Next, as shown in FIG. 5C, a tungsten silicide film (thickness: 100 nm) 14 is
After being deposited on the polycrystalline silicon film 13 by a sputtering method, a second polycrystalline silicon film (thickness: 50 nm) 15 is deposited on the tungsten silicide film 14 by an LPCVD method. Thereafter, the acceleration energy is 30 keV and the dose is 6
At 10 ¹⁵ cm ^-2 , boron ions are implanted into the entire surface of the second polycrystalline silicon film 15.

As shown in FIG. 5D, a three-layer film including the second polycrystalline silicon film 15, the tungsten silicide film 14, and the first polycrystalline silicon film 13 is formed by a normal lithography process and an etching process. By patterning into a wiring shape, a three-layer dual polycide wiring 61 is formed. Using an atmospheric pressure chemical vapor deposition (APCVD) method, an interlayer insulating film 20 made of a silicon oxide film is deposited on the interlayer insulating film 11 so as to cover the dual polycide wiring 61. Thereafter, annealing at 900 ° C. is performed for 10 to 90 minutes in a nitrogen atmosphere. Thus, the semiconductor device shown in FIG. 4 is obtained.

FIG. 6 shows a first polycrystalline silicon (Poly-silicon).
FIG. 6 shows a depth direction distribution of boron concentration (cm ^-3 ) in a sandwich type three-layer polycide structure including a Si) film, a tungsten silicide (WSi ₂ ) film, and a second polycrystalline silicon (Poly-Si) film. ing. This polycide structure is formed on a silicon substrate (Si-sub) and covered with a silicon oxide film (SiO ₂ ).
The impurity concentration distribution shown in FIG.
This is obtained by S). For comparison, the depth direction distribution of the impurity concentration in a normal two-layer polycide structure including a polycrystalline silicon film and a tungsten silicide film is also shown. The cross-sectional configuration of each of the polycide structures is schematically shown in the graph of FIG. An acceleration energy of 15 keV and a dose of 6 × 1 are applied to the polycrystalline silicon located at the lowermost layer of each polycide structure.
After implanting boron ions at 0 ¹⁵ cm ^-2 , annealing (9
(00 ° C., 60 minutes). In FIG. 6, the boron concentration distribution before the annealing step (immediately after the implantation) is 2%.
This is indicated by the dotted line.

As can be seen from FIG. 6, the boron concentration in the first polycrystalline silicon film in the sandwich-type three-layer polycide structure is lower than the boron concentration in the polycrystalline silicon film in the ordinary polycide structure. It has an order of magnitude higher value.
This is because, since the sandwich type three-layer polycide structure has substantially no interface between the tungsten silicide film and the silicon oxide film, boron does not aggregate at such an interface, and the interface is formed at such an interface. This is because boron is "not sucked".

On the other hand, in the conventional two-layer polycide structure, there is an interface between the polycrystalline silicon film and the silicon oxide film. The boron concentration at this interface exceeds 10 × 10 ²¹ cm ⁻³ . This indicates that boron is aggregated at the interface. Such agglomeration of boron causes a decrease in the boron concentration in the two-layer polycide structure.

FIG. 17 schematically shows such a conventional dual polycide wiring having a two-layer structure. This dual polycide wiring is composed of a polycrystalline silicon film 13 and a tungsten silicide film 14. The polycide wiring is formed on interlayer insulating film 11 covering silicon substrate 1, and is in contact with n ⁺ impurity diffusion region and p ⁺ impurity diffusion region of silicon substrate 1 via a contact hole formed in interlayer insulating film 11. doing. The polycide wiring is covered with a silicon oxide film 20.

In such a polycide wiring, boron cohesion occurs between the silicon oxide film 20 and the tungsten silicide film 14. Further, the contact resistance between the polycide wiring and the impurity diffusion region may increase or fluctuate due to the lateral diffusion of boron and arsenic.

FIG. 7 shows the contact resistance between the p ⁺ -type polycide wiring and the p-type impurity diffusion region in the semiconductor substrate. The contact resistance of a normal polycide wiring (conventional example) is indicated by a black square, and the contact resistance of a sandwich type three-layer polycide wiring (example) is indicated by a white square. No boron is implanted in the second polycrystalline silicon of the sandwich type three-layer polycide wiring. The contact resistance of the sandwich type three-layer polycide wiring in which boron is implanted over the entire surface of the second polycrystalline silicon film (other examples) is shown by black diamonds.

As can be seen from FIG. 7, the contact resistance of the sandwich type three-layer polycide wiring according to the present invention is reduced to less than half as compared with the contact resistance of the conventional polycide wiring. Generally, the contact resistance between the p ⁺ -type polycide wiring and the p ⁺ -type impurity diffusion region in the semiconductor substrate depends on the impurity concentration in the lowermost polycrystalline silicon film in the polycide wiring and the p ⁺ -type impurity diffusion region. Heavily dependent on In the polycide wiring according to the present invention, a decrease in boron concentration due to the aggregation of boron is prevented, so that a low contact resistance can be achieved as shown in FIG. In particular, the sandwich type three-layer polycide wiring in which boron is implanted over the entire surface of the second polycrystalline silicon film has an advantage that the contact resistance does not depend on the annealing time. This advantage suppresses variations in contact resistance due to variations in process conditions.

The characteristics of the sandwich-type three-layer polycide wiring according to the present invention are as follows. First, impurity migration (diffusion) across the interface existing in the polycide wiring, that is, impurity in the vertical direction (depth direction). Regarding redistribution.
In order to evaluate the characteristics of the dual polycide wiring, it is necessary to observe the impurity movement (diffusion) in the direction along the interface in the polycide wiring, that is, the impurity redistribution in the lateral direction. FIG. 8 shows a planar layout of a sample for evaluating impurity redistribution in the lateral direction. This sample includes a sandwich-type three-layer polycide wiring 65 having a first portion 65b doped with arsenic and a second portion 65a doped with boron. The second portion 65a of the polycide wiring 65 is in contact with the p ⁺ -type impurity diffusion region 30 in the semiconductor substrate via the contact hole 12. The first portion 65b has a sufficiently large volume as compared with the second portion 65a. Second part 6
The distance between 5b and the contact portion is defined as a distance D. As samples, a plurality of samples having various intervals D were produced, and each sample was annealed at 900 ° C. for 90 minutes. After annealing, the contact resistance of each sample was measured.

FIG. 9 shows the relationship between the contact resistance and the interval D. For samples other than the sample having the sandwich-type three-layer polycide wiring in which boron is injected over the entire surface of the second polycrystalline silicon film, the smaller the distance D, the higher the contact resistance. On the other hand, the contact resistance of the sample including the sandwich type three-layer polycide wiring in which boron is implanted on the entire surface of the second polycrystalline silicon film is low without depending on the sample interval D. This indicates that in the sandwich type three-layer polycide wiring in which boron is implanted over the entire surface of the second polycrystalline silicon film, the lateral diffusion of boron from the contact portion to the second portion 65b is suppressed. . FIG. 10 shows 1 × 1
Boron by annealing at 900 ° C. for 30 minutes in a sandwich type polycide structure in which arsenic of each dose of 0 ¹⁵ , 3 × 10 ¹⁵ , and 6 × 10 ¹⁵ cm ⁻² is implanted into the second polycrystalline silicon film. Shows how is redistributed. FIG. 11 shows 1 × 10 ¹⁵ , 3 × 10 ¹⁵ , 6 × 10 ¹⁵ c
In a sandwich type polycide structure in which arsenic of each dose of m ⁻² is implanted into the first polycrystalline silicon film, 90
It shows how arsenic is redistributed by annealing at 0 ° C. for 30 minutes.

As can be seen from FIGS. 10 and 11, boron is more present in the tungsten silicide film than in the second polycrystalline silicon film. On the other hand, arsenic is present more in the first polycrystalline silicon film than in the tungsten silicide film.
From this, the following can be said.

(1) In the n-type polycide region of the dual polycide wiring, boron implanted in the second polycrystalline silicon film tends to stay in the second polycrystalline silicon film.
It is difficult to move into the tungsten silicide film.

(2) Therefore, boron implanted in the second polycrystalline silicon film does not adversely affect the contact characteristics between the n-type polycide portion and the n-type impurity region.

(1) Since boron is implanted into the entire surface of the second polycrystalline silicon film, boron in the second polycrystalline silicon film and boron diffused from the second polycrystalline silicon film into the tungsten silicide film are laterally diffused. Distributed substantially uniformly in the direction. Therefore, the lateral diffusion of boron in the second polycrystalline silicon film and the tungsten silicide film is suppressed.

(2) Boron at the contact portion between the p-type polycide region and the p-type impurity diffusion region flows out of the p-type polycide region of the second polycrystalline silicon film to the n-type polycide region via the tungsten silicide film. Is suppressed.

Also, (1) n of the dual polycide wiring
In the type polycide region, arsenic in the first polycrystalline silicon film hardly moves into the tungsten silicide film.

(2) Arsenic in the first polysilicon film is less likely to diffuse in the lateral direction than arsenic in the tungsten silicide film.

(3) Therefore, arsenic is prevented from flowing out of the contact portion between the n-type polycide region and the n-type impurity region due to vertical and horizontal diffusion. Therefore, a decrease in the arsenic concentration is prevented at the contact portion between the n-type polycide region and the n-type impurity region. As described above, the contact resistance between the n-type polycide region and the n-type impurity region hardly deteriorates.

Boron has a characteristic that arsenic is hardly diffused into the impurity diffusion region where the concentration is high. FIG. 13 shows the concentration distribution in the depth direction of boron and arsenic in the sandwich type three-layer polycide wiring. More specifically, the polycide wiring in which arsenic is implanted into the first polycrystalline silicon film and boron is implanted into the second polycrystalline silicon film has an impurity concentration after being subjected to annealing at 900 ° C. for 30 minutes. Minutes are shown. As can be seen from FIG. 13, boron hardly diffuses into the silicon substrate.
The arsenic concentration in the polycrystalline silicon film is kept high.

In order to show that boron implanted in the second polycrystalline silicon film does not adversely affect the contact resistance between the n-type polycide portion and the n-type impurity region,
The n-type contact resistance between the sandwich type three-layer polycide wiring and the n-type impurity diffusion region was measured. FIG.
Is a graph showing how the implantation of boron into the second polysilicon film affects the annealing time dependency of the n-type contact resistance. As apparent from FIG. 12, boron implantation into the second polycrystalline silicon film hardly increases the n-type contact resistance. The annealing temperature is 900 ° C.

(Embodiment 4) Referring to FIG.
A CMOS device provided with the polycide wiring will be described. FIGS. 14A and 14B show an embodiment of the present invention using a dual polycide wiring and a conventional example not using a dual polycide wiring, respectively. FIG.
14A and 14B are cross-sectional views of FIGS. 14A and 14B, respectively.

The CMOS semiconductor device of this embodiment has two n-channel MOS transistors and two p-channel MOS transistors.
This is a two-stage CMOS inverter having an S transistor. The two transistors located on the upper side of FIG. 14A are both p-channel MOS transistors, and the transistors located on the lower side are both n-channel MOS transistors.
It is an S transistor. As shown in FIG. 15A, each source of the p-channel MOS transistor is connected to a power supply line (not shown) via a metal line 69a. Each source of the n-channel MOS transistor
It is connected to a ground wiring (not shown) via a metal wiring 69b. As shown in FIGS. 14A and 15A, a polycide interconnection 63a or 63 is provided between the source of the p-channel MOS transistor and the metal interconnection 69a.
b is interposed. Similarly, a polycide interconnection 63c or 63d is interposed between the source of the n-channel MOS transistor and the metal interconnection 69b.

The p-channel M closer to the input terminal (IN)
The drain of the OS transistor is interconnected to the drain of the corresponding n-channel MOS transistor (the n-channel MOS transistor closer to the input terminal) via the dual polycide interconnection 62. Output terminal (OU
The drain of the p-channel MOS transistor closer to T) is connected via a dual polycide wiring 63 to the corresponding n-channel MOS transistor (n closer to the output terminal).
(Channel MOS transistor). The dual polycide wiring 63 is also an output terminal (OUT). The gates of the p-channel and n-channel MOS transistors closer to the input terminal (IN)
The gate electrode 16a is connected to an input terminal (IN) made of a polycide wiring. The gates of the p-channel and n-channel MOS transistors closer to the output terminal are connected to an output terminal (OUT) formed of a polycide wiring 63 via a gate electrode 16b.

During the process of manufacturing the CMOS semiconductor device of this embodiment, aggregation of impurities in the polycide wiring is prevented, and lateral diffusion is suppressed. As a result, an increase in contact resistance is prevented.

As shown in FIGS. 14 (b) and 15 (b), in the conventional example, the drain of the p-channel MOS transistor and the drain of the n-channel MOS transistor are not formed by the dual polycide wiring but by the metal wiring 72. And 73 are interconnected. Further, the input terminal is constituted by a metal wiring 71.
The interconnection between the source of each MOS transistor and the power supply wiring and the ground wiring is also made by the metal wiring 70.

As shown in FIGS. 14A and 14B, the occupied area of the CMOS semiconductor device of this embodiment is smaller than that of the conventional example. Therefore, a small-sized CMOS semiconductor device in which the contact characteristics are hardly deteriorated is realized. Further, a CMOS semiconductor device integrated at high density is provided. For simplicity, the embodiment of the present invention has been described for a two-stage CMOS inverter, but the present invention is also applicable to other CMOS semiconductor devices.

[0080]

According to the semiconductor device of the present invention, the boron concentration in the polycide wiring is prevented, so that the boron concentration in the polycide wiring does not decrease by the heat treatment. As a result, the threshold value of a MOS transistor having such a polycide wiring as a gate electrode is less likely to fluctuate. In addition, stable contact characteristics can be obtained in which the contact resistance between the polycide wiring and the p-type impurity diffusion region does not increase due to the heat treatment.

According to the present invention, there is provided a CMOS semiconductor device in which deterioration of contact characteristics is suppressed by preventing lateral diffusion of impurities in a dual polycide wiring.

[Brief description of the drawings]

FIG. 1 is a sectional view of a semiconductor device showing an embodiment of the present invention.

FIG. 2 is a process sectional view for explaining a method of manufacturing the embodiment shown in FIG. 1;

FIG. 3 is a cross-sectional view of a semiconductor device showing another embodiment of the present invention.

FIG. 4 is a sectional view of a semiconductor device showing still another embodiment of the present invention.

FIG. 5 is a process sectional view for explaining a method of manufacturing the embodiment shown in FIG. 4;

FIG. 6 is a characteristic diagram showing a boron concentration distribution in a polycide wiring contacting a semiconductor substrate;

FIG. 7 is a characteristic diagram showing annealing temperature dependence of p-type contact resistance.

FIG. 8 is a plan view showing a sample for evaluating lateral diffusion.

9 is a characteristic diagram showing a relationship between a distance D between the samples of FIG. 8 and a p-type contact resistance.

FIG. 10 is a characteristic diagram showing a boron concentration distribution in a polycide wiring;

FIG. 11 is a characteristic diagram showing an arsenic concentration distribution in a polycide wiring;

FIG. 12 is a characteristic diagram showing annealing temperature dependence of n-type contact resistance.

FIG. 13 is a characteristic diagram showing an impurity concentration distribution in a three-layer polycide wiring;

14A is a layout diagram of a two-stage CMOS inverter using metal wiring and dual polycide wiring, and FIG. 14B is a layout diagram of a two-stage CMOS inverter using metal wiring.

15A is a cross-sectional view of the two-stage CMOS inverter of FIG. 14A, and FIG. 15B is a cross-sectional view of the two-stage CMOS inverter of FIG.

FIG. 16 is a characteristic diagram showing a boron concentration distribution in a conventional two-layer polycide wiring;

FIG. 17 is a diagram schematically showing impurity diffusion and aggregation in a conventional two-layer polycide wiring.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Silicon substrate 2 Element isolation film 3 Source and drain 4 Gate oxide film 5, 13 First polycrystalline silicon film 6, 14 Tungsten silicide film 7, 15 Second polycrystalline silicon film 8, 9 Silicon oxide film 60 Gate electrode 61, 65 polycide wiring

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. ⁶ , DB name) H01L 21/3205 H01L 21/768 H01L 21/28-21/288 H01L 21/8238 H01L 27/092

Claims (6)

(57) [Claims] 1. A semiconductor device having a polycide wiring on a semiconductor substrate.
In a semiconductor device, the polycide wiring has both a p-type impurity diffusion portion and an n-type impurity diffusion portion.
A first polycrystalline silicon film, and the first polycrystalline silicon film
A refractory metal silicide film formed on the
Only p-type impurities formed on metal silicide film diffuse
And the second polycrystalline silicon film
Wherein a and. 2. The semiconductor substrate according to claim 1, wherein said semiconductor substrate has a p-type impurity diffusion region.
Region is formed, and the p-type impurity diffusion portion of the first polysilicon film is
being connected to a p-type impurity diffusion region.
The semiconductor device according to claim 1 . 3. A p-channel formed on said semiconductor substrate.
A p- type MOS transistor, wherein the p-type impurity diffusion region is
That it is either the source or the drain of the transistor
3. The semiconductor device according to claim 2, wherein: 4. An n-channel MOS transistor on a semiconductor substrate.
Transistor and p-channel MOS transistor
A semiconductor device, comprising: an n-type impurity diffusion region formed in the semiconductor substrate;
Said n-channel having an n-type source and an n-type drain
A MOS transistor and a p-type impurity diffusion region formed in the semiconductor substrate.
Said p-channel having a p-type source and a p-type drain
MOS transistor, a first polycrystalline silicon film, and the first polycrystalline silicon film.
A refractory metal silicide film formed on a capacitor film;
Second polycrystalline silicide formed on refractory metal silicide film
And a polycide wiring composed of a silicon film and the first polycrystalline silicon film.
an n-type impurity diffusion portion connected to the n-type drain;
Connected to the p-type source or the p-type drain
the second polycrystalline silicon having a p-type impurity diffusion portion.
The film is characterized in that only p-type impurities are diffused.
That the semiconductor device. 5. A semiconductor device having a polycide wiring on a semiconductor substrate.
In a method of manufacturing a semiconductor device, the step of forming the polycide wiring includes forming a first polycrystalline silicon film on the semiconductor substrate.
And a p-type impurity diffusion portion and an n-type impurity in the first polycrystalline silicon film.
Selectively forming an impurity diffusion portion; and forming a refractory metal silicide film on the first polycrystalline silicon film.
Forming a second polycrystalline silicon film on the refractory metal silicide film
Forming a p-type impurity over the entire surface of the second polycrystalline silicon film.
Manufacturing a semiconductor device, comprising the steps of:
Construction method. 6. A p-type impurity in said first polycrystalline silicon film.
A p-type impurity in which a diffusion portion is formed in the semiconductor substrate;
N of the first polycrystalline silicon film
Type impurity diffusion portion is formed in the semiconductor substrate
Claims: Connected to an n-type impurity diffusion region
Item 6. The method for manufacturing a semiconductor device according to Item 5.