JPH0690702B2 - Data transfer control circuit - Google Patents

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data transfer control circuit between a channel device controlled by a central processing unit (hereinafter referred to as CPU) and an input / output control device, and particularly to data transfer. The present invention relates to a data transfer control circuit suitable for accurately performing the above.

[Conventional technology]

Conventionally, there are an interlock method and a non-interlock method as a data transfer method of a channel device and an input / output control device. The interlock system, as shown in FIG. 2, outputs the next data request signal unless the input / output control device receives the data response signal from the channel device corresponding to the data request signal from the input / output control device. Not referred to. The non-interlock system is a system in which the input / output control device can output a data request signal without waiting for a data response signal from the channel device, as shown in FIG. For each method, the data bus may have a 2-byte width as a 1-byte width.

FIG. 4 is a diagram showing a specific example in the case of performing data transfer between a channel device and an input / output control circuit using two data buses. As shown in FIG. 4, the channel device 1 and the input / output control device 2 include a data request signal line 100, a data response signal line 200, mark-in signal lines 500a and 500b, and a mark-out in addition to the data buses 300 and 400. Signal lines 600a, 600b,
Connected by. Where the mark-in signal line 50
0a and the mark-out signal line 600a correspond to the data bus 300, and the mark-in signal line 500b and the mark-out signal line 600b correspond to the data bus 400. That is, when one data request signal is output to the data request signal line 100, the data buses 300 and 400 can be simultaneously used to transfer data. In this case, the mark-in signal line 500a is the data bus
The mark-in signal indicating the validity of the data request to 300 is transferred, and the mark-in signal line 500b outputs the mark-in signal indicating the validity of the data request to the data bus 400. Further, the markout signal line 600a transfers a markout signal indicating the validity of the data transferred via the data bus 300, and the markout signal line 600b transmits the markout signal line 600b.
A markout signal indicating the validity of the data transferred via.

For example, when data is transferred from the input / output control device 2 to the channel device 1 (hereinafter referred to as a read operation), if data is transferred using both of the data buses 300 and 400, the data is sent to the data 300 and 400 at the same time. A mark-in signal with a logical value "1" is sent to the mark-in signal lines 500a and 500b, and a logical value "1" is sent to the data request signal line 100.
The data request signal of is transmitted. On the other hand, the channel device 1 sends out the data response signal of the logical value "1" to the data response signal line 200, and at this time, the fact that both the data of the data buses 300, 400 are received is marked out by the markout signal lines 600a, 6a.
It responds by outputting a markout signal of logical value "1" to 00b. The input / output control device 2 confirms by the markout signal that the channel device 1 has correctly received the data.

Further, when data is transferred from the channel device 1 to the input / output control device 2 (hereinafter referred to as a write operation), the operation is as follows. When performing data transfer to both the data buses 300 and 400, the input / output control device 2 sets the data request signal line 10
The data request signal having the logical value "1" is output to 0, and the mark-in signal having the logical value "1" is output to both the mark-in signal lines 500a and 500b. On the other hand, the channel device 1
Indicates that the data has been sent to both of the data buses 300 and 400, so that the data response signal of the logical value “1” is output to the data response signal line 200 and the markout signal line 600
A markout signal with logical value "1" is output to both a and 600b.

As described above, a method of performing data transfer using two data buses is disclosed in, for example, Japanese Patent Laid-Open No. 60-74066.

In this way, when data transfer is performed using two data buses, one data request signal is a maximum of 2 bytes (1 byte is composed of 8-bit data and 1-bit validity here. Information) can be transferred. If only one byte of data needs to be requested by one data request signal, set the mark-in signal line or mark-out signal line corresponding to the data bus that does not require data transfer to the logical value "1". Thus, 1 byte of data can be transferred. That is, whether the input / output control device requests the 2-byte data or the 1-byte data depends on whether the mark-in signal line or the mark-out signal line has the logical value "1" in synchronization with the transmission of the data request signal. "It is done by. Further, it is known that in the channel device, when the remaining data to be transferred becomes 1 byte, only 1 byte of data is transferred even if the input / output control device requests 2 bytes. Here, it is possible that the number of mark-in signals transmitted in synchronization with the data request signal does not necessarily match the number of mark-out signals transmitted in synchronization with the data response signal output in response to the data request signal. Are known. The above situation is the same when data is transferred from the input / output control device to the channel device.

Incidentally, as one related to the above-mentioned prior art, Japanese Patent Laid-Open No.
There are inventions disclosed in JP-A-74066 and JP-A-60-74072.

[Problems to be solved by the invention]

In the above-mentioned prior art, when the non-interlock system is used and data is transferred using a plurality of data buses, as described above, the number of mark-in signals transmitted in synchronization with the data request signal. And the number of signals sent to the mark-out line in synchronization with the data response signal do not always match, and in the non-interlock system, the data request signal and the data response signal are not in the shake hand format. Therefore, in the conventional technique, when the data response signal is transmitted, the mark-in signal does not exist, and whether the data on the plurality of data buses transmitted in synchronization with the data response signal is the requested data. There was a problem that it was not possible to judge whether or not.

The present invention has been made in view of the above-mentioned problems of the prior art. When a data transfer is performed by a non-interlock method using a plurality of data buses, a data transfer control circuit capable of reliably transmitting and receiving data. The purpose is to provide.

[Means for solving problems]

A data transfer control circuit of the present invention stores a mark-in signal corresponding to a data bus transmitted per unit time at a predetermined address, and a data bus inputted per unit time from a channel device corresponding to the mark-in signal. Storage means for outputting a mark-in signal stored at the predetermined address by a corresponding mark-out signal, and comparison means for comparing the mark-in signal output from the storage means with the input mark-out signal are provided. The comparison means validates only the data on the data bus in which the mark-in signal and the mark-out signal corresponding to the data bus match.

[Work]

According to the present invention, the comparing means compares the mark-in signal corresponding to the data bus transmitted per unit time with the mark-out signal corresponding to the data bus transmitted corresponding to the mark-in signal. As a result, at the time of writing, among the data transferred from the channel device to the input / output control device via the plurality of data buses, only the data on the data bus designated by the mark-in signal can be determined to be valid. It will be possible. That is, the data on the data bus in which the mark-in signal corresponding to the data bus and the mark-out signal corresponding to the data bus match are determined to be valid. Also,
At the time of reading, of the data transferred from the input / output control device to the channel device via the plurality of data buses, it is possible to mark whether the data on the data bus designated by the mark-in signal is correctly received by the channel device. It becomes possible to confirm by the out signal. That is, the mark-in signal corresponding to the data bus and the mark-out signal corresponding to the data bus match, and it is confirmed that the data on the data bus is correctly received by the channel device.

〔Example〕

The present invention will be described in more detail with reference to the examples shown in the attached screens.

FIG. 1 is a block diagram showing an embodiment of the data transfer circuit of the present invention, and FIG. 5 is a time chart showing an example of the write operation. This data transfer circuit is provided in the input / output control circuit.

In FIG. 1, an input / output control device (not shown) sends a data request signal to the data request signal line 100, and in synchronization with this, a mark-in signal sent to the mark-in signal lines 500a and 500b by the input address circuit 11. Specified memory circuit
It is stored in the addresses of 10a and 10b. Input address circuit 11
Is updated by a signal obtained by delaying the data request signal on the data request signal line 100 by the delay circuit 13. The delay time of the delay circuit 13 is stored in the mark-in signal by the data request signal.
Sufficient time is set to input to 10a and 10b.

The validity of the data transmitted via the data bus (not shown) in synchronization with the data response signal transmitted via the data response signal line 200 is determined by the data valid signals 53 and 54. That is, the data on the data bus when the data valid signals 53, 54 have the logical value "1" is set as valid data, and the data is stored in the data latch circuits 17a, 17b in synchronization with the data response signal. Explaining the operation at this time in detail, the data valid signals 53, 54 are the output signals 51, 52 of the memory circuits 10a, 10b storing the mark-in signal,
The mark-out signal output to the mark-out signal lines 600a and 600b in synchronization with the data response signal transmitted via the data response signal line 200, and the AND circuit 15a, respectively.
It is input to 15b and obtained as outputs of AND circuits 15a and 15b. At this time, the mark-in signals 51, 52 output from the storage circuits 10a, 10b are stored at the address designated by the output address circuit 12. The update of the output address circuit 12 is performed by delaying the data response signal transmitted via the data response signal line 200 by the delay circuit 14. The delay time of the delay circuit 14 depends on the data response signal line.
The data of the data buses 300 and 400, whose validity has been confirmed by the data valid signals 53 and 54 synchronized with the data response signal transmitted via the data latch circuit 17a, 1
Set enough time to be set to 7b.

In FIG. 5, the channel device outputs data response signals 200-1 to 200-5 in response to data request signals 100-1 to 100-5 from the input / output control device (not shown). As shown in FIG. 5, the mark-in signal 5 is synchronized with the data request signal 100-2.
The mark-in signals output to 00a and 500b are "1" at 500a and "0" at 500b. Also, the data request signal 10
The mark-in signals output to the mark-in signals 500a and 500b in synchronization with 0-3 are "0" at 500a and "1" at 500b.
Therefore, the data request signal 100-2 requests data only to the data bus 300, and the data request signal 100-3 requests data only to the bus 400. On the other hand, the channel device outputs the data 2 and 3 in response to the data request signals 100-2 and 100-3, and the markout signal lines 600a and 600b.
"1" is output for each of the. Further, in response to the data request signal 100-5, since the data to be transmitted from the channel device is only the data 6, the data 6 is transmitted only to the bus 300, and the markout signal line 600a is marked with "1" and marked out. Output "0" to the signal line 600b.

As described above, the data response signal 200-1 from the channel device
When ~ 200-5 is sent, these data response signals 2
The mark-out signals sent to the mark-out signal lines 600a and 600b in synchronization with 00-1 to 200-5 and the mark-in signals 51 and 52 output from the storage circuits 10a and 10b are the AND circuits 15a and 1b.
Data valid signals 53 and 54 are formed by inputting to 5b. Here, the data on the data buses 300 and 400 at the time when the data valid signals 53 and 54 become the logical value "1" are set in the data latch circuits 17a and 17b. That is, the data buses 300, 400 transmitted in synchronization with the data response signal 200-1
Since the data valid signals 53 and 54 are both “1”, the data 0 and 1 of the data latch circuit 17 are valid data.
Set to a, 17b. Of the data 2 and 3 transmitted in synchronization with the data response signal 200-2, only the data valid signal 53 is "1", so only the data 2 of the data bus 300 is set in the data latch circuit 17a. At this time, the data 3 of the data bus 400 becomes invalid data. This is because the mark-in signal output to the mark-in signal line 500b in synchronization with the data request signal 100-2 is "0" and the data bus 400 has not requested the data. At the same time, for the data 2 and 3 that are sent in synchronization with the data response signal 200-3, only the data valid signal 54 is “1”.
Only data 3 of 400 is set in the data latch circuit 17b. At this time, the data 3 of the data bus 300 becomes invalid data. Further, since only the data valid signal 53 of the data 6 and 5 transmitted in synchronization with the data response signal 200-5 is "1", only the data 6 of the data bus 300 is set in the data latch circuit 17a. This is because even though the data request signal 100-5 requests the data to be sent to both the buses 300 and 400, the data sent by the channel device has only 1 byte remaining, so that only the data 6 can be sent to the data bus 300. Due to sending

In the above embodiment, the case where the data transfer is performed by the non-interlock method has been described, but the present invention is not limited to this, and can be applied to the case where the data transfer is performed by the interlock method. It is possible.

Further, in the above embodiments, the write operation has been described as an example, but the present invention is not limited to this.
It can also be applied to the read operation. In the read operation, by matching the number of mark-in signals output from the input / output control device with the input mark-out signal, it can be confirmed that the data output from the input / output control device has been received by the channel device. You can check. In this case, the AND circuits 16a and 16b in FIG.
The output can be used to confirm the above.

〔The invention's effect〕

As is apparent from the above description, according to the present invention, in the case of data transfer in the interlock system or the non-interlock system using a plurality of data buses, the input / output control device sends out together with the data request signal during the write operation. Even if the number of mark-in signals to be transmitted and the number of mark-out signals sent from the channel device together with the data response signal do not match, it is possible to reliably judge whether the data on the data bus is valid or invalid, and also the read operation. Sometimes it becomes possible to accurately confirm the reception of data sent by the I / O controller at the channel device.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention, FIG. 2 is an explanatory diagram showing data transfer of an interlock system, FIG. 3 is an explanatory diagram showing data transfer of a non-interlock system,
FIG. 4 is a block diagram showing a concrete example in the case of performing data transfer using two data buses according to the conventional technique, and FIG. 5 is a chart showing the operation of the embodiment shown in FIG. 1 ... Channel device, 2 ... Input / output control device, 10a, 10
b ... memory circuit, 11 ... input address circuit, 12 ... output address circuit, 13,14 ... delay circuit, 15a, 15b, 16a, 16b ...
… And circuit, 17a, 17b …… Data latch circuit, 100 ……
Data request signal line, 200 ... Data response signal line, 300,400
...... Data bus, 500a, 500b …… Mark-in signal line, 600
a, 600b …… Markout signal line.

Claims (1)

[Claims] 1. A plurality of mark-in signals corresponding to a plurality of data buses sent from an input / output control device to a channel device and a mark-out signal corresponding to a data bus sent from a channel device to an input / output control device. In a system in which data is transferred between an input / output control device and a channel device via the data bus of, a mark-in signal corresponding to the data bus sent per unit time is stored in a predetermined address in the input / output control device. Storage means for outputting the mark-in signal stored at the predetermined address in response to the mark-out signal corresponding to the data bus input from the channel device per unit time in response to the mark-in signal, and the storage means for outputting the mark-in signal. A comparison means for comparing the mark-in signal and the input mark-out signal is provided, and the comparison means inputs Data that is characterized by determining that the data on multiple data buses is the requested data by validating only the data on the data bus whose match-in signal and the mark-out signal corresponding to the data bus match. Transfer control circuit.