JPS5892023A - Channel device - Google Patents

Abstract

PURPOSE:To improve the processing efficiency and to simplify the constitution of a control system, by producing an ON-state signal and an OFF-state signal rejecting noises from an inputted TAGIN signal and reading out both signals through address designation suitably. CONSTITUTION:ON and OFF-state signals as to each TAGIN signal produced are respectively logged on selection circuits 21, 22 on a channel device 1 separately. When a control section 23 waits for the TAGIN signal on a control sequence transferred to ON, a microprogram generates an address designating an On selection circuit 21, i.e., an ON-readout selection signal to check whether or not the objective specific TAGIN signal is ON-state. When the TAGIN signal to be ON-stage is detected, the signal level of ''1'' of corresponding TAGOUT issuing circuits 9-11 is controlled to be set on.

Description

DETAILED DESCRIPTION OF THE INVENTION (1) Technical Field of the Invention The present invention relates to a channel device, and more particularly to a control signal detector IS that is less likely to malfunction, based on an interlock system at its I10 interface.

(2) Background of the Technology Conventionally, an interlock method has been used as one of the methods used to control interface connections between channel devices and I10 devices. In the interface, TAG signals are provided for each type of control item. If an interlock system is applied to these TAG signals, the TAGIN signal issued by the I10 device and the TAG signal issued by the channel device CHU
The ONSOFF state with the AGOUT signal is communicated with a constant tracking progression.

FIG. 1 shows the basic sequence of the control rules for the interlock system.

In FIG. 1, the I10 device issues a TAGIN signal to the channel device CHU for one control item. Channel device CHU has TAG IN signal ON
When detecting the status from the received (TAG IN) signal, turn on the corresponding TAG OUT signal.
Make it. On the other hand, the I10 device receives (TAG 0
UT) detects the ON state of the signal and selects the TAG IN
Turn the signal OFF. The TAG IN signal must not be turned OFF until the sequence is completed. After detecting the OFF state of the TAG IN signal, the channel device turns the TAG OUT signal OFF.

Channel device CHU The ON or OFF state of the received (TAG IN) signal is checked by a microprogram, and the TAG OUT is processed according to the predetermined conditions.
Performs control to switch signals.

However, the channel unit CHU received (TAG I
N) In the process of being transmitted from the I10 device, the signal is affected by noise, causing a false rise to an ON state or a fall to an OFF state due to a glitch waveform, which is detected by the channel device CHU. This could lead to malfunctions.

In addition, when a large number of TAG signals are provided, the processing for checking the ON state or OFF state of each of them is performed using a microprogram. It is an object of the present invention to provide a TAG signal detection means capable of detecting a signal state with less noise-induced movement and facilitating signal selection even when handling multiple TAG numbers.

(4) Structure of the Invention The present invention has a structure in which the I10 interface of the channel device is controlled by an ink lock method.
means for receiving a plurality of TAG IN signals from an I10 device; detecting an ON state and an OFF state for each of the received TAG IN signals; logic means for outputting status signals about it and all T
AG IN signal ON state signal and OFF state II! It is characterized by comprising two sets of signal means in which the A signals are separately aggregated, and a selection means for reading out the two sets of signal means as necessary.

(5) Examples of the invention The present invention will be explained in detail below based on examples.

2.1 is a configuration diagram of the embodiment device, and 3 sets of TAG
The control circuits for the IN signal and the '1'' AG OUT signal are not included. In 1 cij ta, 1 is the channel device CHU, 2 is the I10 installed f, 3 to 5 are the TAG IN issuing circuits of Ilo, and 6 to 8 are the CHU TAGI
N receiving circuits, 9 to 11 are CHU TAG OUT issuing circuits, 12 to 14 are Ilo TAG OU1 receiving circuits, 15 to 17 are ON logic circuits that detect the ON state of the TAG IN signal, and 18 to + are the same. TAG
OFF logic circuit for detecting OFF state of IN signal, 21
ON selection circuit for reading FiON status number, 22 is OFF
OFF selection circuit that outputs a status signal; 23 is a control unit; 24
is an address line for selecting the ON selection circuit 21 and the OFF selection circuit 22; 25 is a read output line for ON state signals and OFF state signals; 26 is a TAGOUT signal issue control line;
are shown respectively.

! Figure 3 shows the TAG including noise in this example.
In order to explain the logic for detecting the ON state and OFF state from the IN signal, for example, TAG IN issue 1' 1 path 3 et al.' TA G I N signal h for G information to T of t'j2; issued tl, Tamoto Yaro. This signal originally has a clean waveform as shown as the 1st < r ζ TAG IN signal. Although I have
When input to the CHUDTAG IN receiving circuit 6, it becomes a modified waveform including glitches (A) or B (see FIG. 3(a)). 2. Glitch A may be mistakenly recognized as a change in the TAG TN signal to the ON state. Similarly, glitch B may be mistakenly recognized as a change in the TAG IN signal to the OFF state.

Therefore, the CHU receives the TAG IN input signal (cL) from the TAG IN input signal (cL) in FIG.
It is necessary to create an OUT signal 1, the condition is that after a certain period of time has elapsed from the ON position of the signal (α), TAG O
The UT signal is in the ON state, and the OFF state of the signal (α) is recognized, and the TAG OUT signal is turned OFF.Then, the ON position of the signal (α) and the OFF state are recognized.
What should be noted about the F position is that it is not the absolute time position that matters, but the relative time magnitude. Therefore, no problem occurs even if the signal (α) is delayed as a whole.

FIGS. 3(b) to 3(f) show signal manipulation performed in this embodiment to eliminate the influence of this glitch.

The waveform (b) in Figure 3 is the signal (α) synchronized with a clock signal, the waveform (C) in Figure 3 is delayed by one clock, and the waveform in (d) is further synchronized with the clock signal. is delayed by one clock. Here, waveform (e) and waveform (d
), the waveform shown in (e) of the same figure is obtained.

The logical product of waveforms (c) and (d) has the effect of removing glitches. Next, waveform (f) is obtained by logically ORing waveform (c) and waveform (d). Glitch B has been removed from waveform (f).

In this way, by taking the AND or OR of signals shifted by one clock, the influence of the glitch can be removed as long as the width of the glitch is narrower than one clock. The signal period in waveform (e) has a width P, but if the TAGOUT signal is issued for a period of y, malfunctions can be avoided. Similarly, the waveform (f) has a signal period Q, but in the period Q' after the end of this period, the TAG
Malfunctions can be avoided by turning off the OUT signal.

In FIG. 2, TAG IN receiving circuits 6 to 8 are
This circuit synchronizes the TAG IN input signal with a clock and generates two signal waveforms that are shifted by l clocks. The ON logic circuits 15 to 17 operate according to the waveform (e
) consists of an AND circuit to create a signal corresponding to .

The ON selection circuit 21 has a function of simultaneously reading the outputs of the ON logic circuits 15 to 17.

FIG. 4 shows an example of a specific circuit for detecting the ON state from the TAG IN signal. In the figure, 6 to 8 are three-stage delay circuits or shift registers corresponding to the TAG IN receiving circuit in FIG. Numerals n to 3 are three-man power AND gates, which combine the functions of the 0NIiil logic circuits 15 to I7 and the ON selection circuit 21 in Figure 1g2.

OFF logic circuit 18 to OFF selection circuit 2 in FIG.
2 also has a similar configuration. Fifth
The figure shows an example of the specific circuit. In the same figure, 6 to 8
is the TAG IN receiving circuit in FIG. 2, and (9) to 32 are two-man power output circuits corresponding to the OFF logic circuits 18 to 32 in FIG.
The R gate is a two-man power AND gate corresponding to the OFF selection circuit 22 in FIG. 2.

Referring again to FIG. ON state signal and OFF state signal for each TAG IN signal generated as described above
The status signals are separately collected in III selection circuits 21 and 22, respectively.

When the control section 23 is in a state of waiting for the TAG IN signal to turn ON in the control sequence, the microprogram 23 generates an address specifying the ON selection circuit 21, that is, an ON read selection signal, and selects the target. Check whether a specific TAG-IN signal has become ON. If it is detected that the TAG IN signal is in the ON state, control is performed to turn the signal level 1 of the corresponding TAG OUT issuing circuits 9 to 11 ON. This applies similarly to the case of OFF state detection.

In this case, when the OFF state of the TAG IN signal is detected, control is performed to turn OFF the level of the TAG OUT signal corresponding to the TAG IN signal.

Note that although the selection circuits 21 and 22 were configured with gate circuits,
This can also be combined with a latch or register. Extracting a signal related to a particular TAGIN signal from among a plurality of aggregated ON state signals or OFF state signals is within the scope of ordinary techniques.

(6) Effects of the Invention According to the present invention, separate signals such as an ON state signal and an OFF state signal are generated by eliminating noise from the input TAG IN signal, and the ON state signal and the OFF state 11 signal are appropriately generated. Since it can be read by addressing, the processing efficiency of the channel device can be improved and the configuration of the control system can be simplified.

[Brief explanation of drawings]

Figure 1 shows 7 of the TAG signal using the conventional interlock system.
- Figure 2 is a configuration diagram of the embodiment of the present invention, Figure 3 is an explanatory diagram of the
4 is a detailed diagram of the ON logic circuit in the embodiment, and FIG. 5 is a detailed diagram of the OFF logic circuit in the embodiment. In the figure, 1 is a channel device, 2 is an I10 device, 3 to 5 are TAG IN issuing circuits, 6 to 8 are TAG IN receiving circuits, 9 to 11 are TAG OUT signal issuing circuits,
12 to 14 are TAG OUT signal receiving circuits, 15 to 17 are ON logic circuits, 18 to 20 are OFF logic circuits, 21 is an ON selection circuit, 22 (work OFF selection circuit, 23
indicates the control unit, respectively. Patent applicant Fujitsu Ltd. Representative Patent Attorney Fumihiro Hase (1 other person) 1, 3, 2 WI

Claims (1)

[Claims] Multiple TAG IN signals and TAGs where the I10 interface of the channel device is controlled in an interlocking manner
In the device having an OUT signal, means for receiving a plurality of TAG, IN signals from the I10 device, and an ON state and an O state for each of the received TAG IN signals.
logic means for detecting the FF status and outputting a status signal for each, and for all TAG IN signals.
NN letter signal and OFF state signal are collected separately 2
1. A channel device comprising: a pair of signal means; and a selection means for reading out the two sets of signal means as necessary.