JPS5892023A - Channel device - Google Patents

Channel device

Info

Publication number
JPS5892023A
JPS5892023A JP19021381A JP19021381A JPS5892023A JP S5892023 A JPS5892023 A JP S5892023A JP 19021381 A JP19021381 A JP 19021381A JP 19021381 A JP19021381 A JP 19021381A JP S5892023 A JPS5892023 A JP S5892023A
Authority
JP
Japan
Prior art keywords
signal
tag
state
signals
tagin
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP19021381A
Other languages
Japanese (ja)
Other versions
JPS617662B2 (en
Inventor
Seiichi Shimizu
誠一 清水
Masao Koyabu
小薮 正夫
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP19021381A priority Critical patent/JPS5892023A/en
Publication of JPS5892023A publication Critical patent/JPS5892023A/en
Publication of JPS617662B2 publication Critical patent/JPS617662B2/ja
Granted legal-status Critical Current

Links

Classifications

    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38Information transfer, e.g. on bus
    • G06F13/42Bus transfer protocol, e.g. handshake; Synchronisation
    • G06F13/4204Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus
    • G06F13/4221Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being an input/output bus, e.g. ISA bus, EISA bus, PCI bus, SCSI bus
    • G06F13/4226Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being an input/output bus, e.g. ISA bus, EISA bus, PCI bus, SCSI bus with asynchronous protocol

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Information Transfer Systems (AREA)

Abstract

PURPOSE:To improve the processing efficiency and to simplify the constitution of a control system, by producing an ON-state signal and an OFF-state signal rejecting noises from an inputted TAGIN signal and reading out both signals through address designation suitably. CONSTITUTION:ON and OFF-state signals as to each TAGIN signal produced are respectively logged on selection circuits 21, 22 on a channel device 1 separately. When a control section 23 waits for the TAGIN signal on a control sequence transferred to ON, a microprogram generates an address designating an On selection circuit 21, i.e., an ON-readout selection signal to check whether or not the objective specific TAGIN signal is ON-state. When the TAGIN signal to be ON-stage is detected, the signal level of ''1'' of corresponding TAGOUT issuing circuits 9-11 is controlled to be set on.

Description

【発明の詳細な説明】 (1)発明の技術分野 本発明は、チャネル装置に関し、特にそのI10インタ
フェースにおけるインタロック方式に基づく制御信号の
、誤動作の少い検出機isに関する。
DETAILED DESCRIPTION OF THE INVENTION (1) Technical Field of the Invention The present invention relates to a channel device, and more particularly to a control signal detector IS that is less likely to malfunction, based on an interlock system at its I10 interface.

(2)技術の背景 従来、チャネル装置およびI10装置間のインターフェ
ース接続制御に使用される方式の1つとして、インタロ
ック方式がある。インタフェースでは、各種の制御項目
毎にTAG信号が設けられている。これらTAG信号に
インタロック方式が適用された場合、I10装置が発行
するTAGIN信号とチャネル装置CHUが発行するT
AGOUT信号との0NSOFF状態は、一定の追従的
進行をともなって交信される。
(2) Background of the Technology Conventionally, an interlock method has been used as one of the methods used to control interface connections between channel devices and I10 devices. In the interface, TAG signals are provided for each type of control item. If an interlock system is applied to these TAG signals, the TAGIN signal issued by the I10 device and the TAG signal issued by the channel device CHU
The ONSOFF state with the AGOUT signal is communicated with a constant tracking progression.

第1図は、そのインタロック方式の制御規約の基本シー
ケンスを示[7たものである。
FIG. 1 shows the basic sequence of the control rules for the interlock system.

第1図において、I10装置は、ある1つの制御項目に
ついて、チャネル装置CHUにTAGIN信号を発行す
る。チャネル装置CHUは、TAG  IN信号がON
状態になったことを受信した(TAG  IN)信号か
ら検出したとき、対応するTAG  OUT信号をON
にする。他方、I10装置は、受信した(TAG  0
UT)信号のON状態を検出して、そのTAG  IN
信号をOFFに−iる。TAG  IN信号は、そのシ
ーケンスが終了するまでは、OFFにされてはならない
。チャネル装置は、TAG  IN佃号のOFF状態を
検出してから、TAG  OUT信号をOFFにする。
In FIG. 1, the I10 device issues a TAGIN signal to the channel device CHU for one control item. Channel device CHU has TAG IN signal ON
When detecting the status from the received (TAG IN) signal, turn on the corresponding TAG OUT signal.
Make it. On the other hand, the I10 device receives (TAG 0
UT) detects the ON state of the signal and selects the TAG IN
Turn the signal OFF. The TAG IN signal must not be turned OFF until the sequence is completed. After detecting the OFF state of the TAG IN signal, the channel device turns the TAG OUT signal OFF.

チャネル装置CHU 畝受信した(TAG  IN)信
号のONあるいはOFF状態をマイクロプログラムによ
り調べ、定められた条件処したがってTAG  OUT
信号を切替える制御を行なう。
Channel device CHU The ON or OFF state of the received (TAG IN) signal is checked by a microprogram, and the TAG OUT is processed according to the predetermined conditions.
Performs control to switch signals.

しかし、チャネル装置CHUが受信した(TAG  I
N)信号は、I10装置から伝送される過程で、雑音の
影蕃を受け、グリッチ(Glitch)波形による偽の
ON状態への立上りあるいはOFF状態の立下りを生じ
、チャネル装置CHUがこれを検出して、誤動作を行な
うことがあった。
However, the channel unit CHU received (TAG I
N) In the process of being transmitted from the I10 device, the signal is affected by noise, causing a false rise to an ON state or a fall to an OFF state due to a glitch waveform, which is detected by the channel device CHU. This could lead to malfunctions.

また、TAG信号が多数設けられている場合には、その
個々についてON状1IiToるいはOFF状態を調べ
るための処理は、マイクロプログラム制(3)発明の目
的 本発明は、チイえル装置において、雑音による一動作の
少ない信号状態検出が可能で、かつ多側のTAG伯号を
取扱う場合にも、信号選択が容易な、TAG信号検出手
段を提供することを目的にする。
In addition, when a large number of TAG signals are provided, the processing for checking the ON state or OFF state of each of them is performed using a microprogram. It is an object of the present invention to provide a TAG signal detection means capable of detecting a signal state with less noise-induced movement and facilitating signal selection even when handling multiple TAG numbers.

(4)発明の構成 本発明は、その構成として、チャネル装置のI10イン
タフェースがインクロック方式で制御される複数のTA
G  IN信号およびTAG  OUT信号を有するも
のに2いて、I10装置からの複数のTAG  IN信
号を受信する手段と、該受信したTAG  IN信号の
各々についてON状態とOFF状態とを検出し7、そね
それについて状態信号を出力する論理手段と、全てのT
AG  IN信号についてON状態信号およびOFF状
II!A信号を別々に集合化した2組の信号手段と、該
2組の信号手段を必要に応じて読出すための選択手段と
、をそなえていることを特徴としている。
(4) Structure of the Invention The present invention has a structure in which the I10 interface of the channel device is controlled by an ink lock method.
means for receiving a plurality of TAG IN signals from an I10 device; detecting an ON state and an OFF state for each of the received TAG IN signals; logic means for outputting status signals about it and all T
AG IN signal ON state signal and OFF state II! It is characterized by comprising two sets of signal means in which the A signals are separately aggregated, and a selection means for reading out the two sets of signal means as necessary.

(5)発明の実施例 以下に、本発明を実施例にしたがって詳述する。(5) Examples of the invention The present invention will be explained in detail below based on examples.

第2【る1は実施例装置の構成図であり、3組のTAG
  IN信号、’1”AG  OUT信号についての制
御回路を不ず。1cij taにおいて、1はチャネル
装置CHU、2はI10装せf、 3乃至5はIloの
TAG  IN発行回路、6乃至8はCHUのTAGI
N受信回路、9乃至11はCHUのTAG  OUT発
行回路、12乃至14はIloのTAG  OU1゛受
信回路、15乃至17はTAG  IN信号のON状態
を検出するON論理l路、18乃至加は同じTAG  
IN信号のOFF状態を検出するOFF論理回路、21
FiON状態伯号を読出すON選択回路、22はOFF
状態信号を胱出すOFF選択回路、23は制御部、24
はON選択回路21とOFF選択回路22とを選択する
アドレス線、25はON状態信号とOFF状態信号との
読出し出力線、26はTAGOUT信号の発行制御線、
をそれぞれ示す。
2.1 is a configuration diagram of the embodiment device, and 3 sets of TAG
The control circuits for the IN signal and the '1'' AG OUT signal are not included. In 1 cij ta, 1 is the channel device CHU, 2 is the I10 installed f, 3 to 5 are the TAG IN issuing circuits of Ilo, and 6 to 8 are the CHU TAGI
N receiving circuits, 9 to 11 are CHU TAG OUT issuing circuits, 12 to 14 are Ilo TAG OU1 receiving circuits, 15 to 17 are ON logic circuits that detect the ON state of the TAG IN signal, and 18 to + are the same. TAG
OFF logic circuit for detecting OFF state of IN signal, 21
ON selection circuit for reading FiON status number, 22 is OFF
OFF selection circuit that outputs a status signal; 23 is a control unit; 24
is an address line for selecting the ON selection circuit 21 and the OFF selection circuit 22; 25 is a read output line for ON state signals and OFF state signals; 26 is a TAGOUT signal issue control line;
are shown respectively.

!だ第3図は、本実施例において雑音を含むTAG  
IN信号から、ON状態およびOFF状態”を検出する
論理を説明するた、・うの、信号波形図である 動作jてむいて、IloのたとえばTAG  IN発行
1′1路3つ・ら、’t′j2のTへG情報についての
TA G  I N信号h;発行さtl、たもつと・ヤ
ろ。この信号は、本来、第1<r・ζTAG  IN信
号として示したような、きれいな波形をもっているが、
CHUDTAG  IN受信回路6に入力されるときに
は、第3図(α)に示すLつな、グリッチ雑−)Aある
いシまBを含む変形された波形となって1^る。2、グ
リッチAは、TAG  TN信号のON状態への変化と
誤って認識させるおそれがあり また、同様にグリッチ
Bは、TAG  IN信号のOFF状態への変化と誤っ
て認識させるおそれがある。
! Figure 3 shows the TAG including noise in this example.
In order to explain the logic for detecting the ON state and OFF state from the IN signal, for example, TAG IN issue 1' 1 path 3 et al.' TA G I N signal h for G information to T of t'j2; issued tl, Tamoto Yaro. This signal originally has a clean waveform as shown as the 1st < r ζ TAG IN signal. Although I have
When input to the CHUDTAG IN receiving circuit 6, it becomes a modified waveform including glitches (A) or B (see FIG. 3(a)). 2. Glitch A may be mistakenly recognized as a change in the TAG TN signal to the ON state. Similarly, glitch B may be mistakenly recognized as a change in the TAG IN signal to the OFF state.

そのため、CHUは、第3図のTAG  IN入力信号
(cL)から、正[7いインタロック動作によりTAG
  OUT信号をつくる必要がある1、その条件は、信
号(α)のON位置から一定時間経過後にTAG  O
UT信号をON状態(でし、また信号(α)のOFF状
態を認識し7てTAG  OUT、信号をOFF状態に
することである。そして、信号(α)のON位置とOF
F位置とについて注意すべきことは、その絶対的時間位
置が問題なのではなく、相対的時間の大きさが重要なこ
とである。したがって、信号(α)が全体として遅延さ
れても支障は生じない。
Therefore, the CHU receives the TAG IN input signal (cL) from the TAG IN input signal (cL) in FIG.
It is necessary to create an OUT signal 1, the condition is that after a certain period of time has elapsed from the ON position of the signal (α), TAG O
The UT signal is in the ON state, and the OFF state of the signal (α) is recognized, and the TAG OUT signal is turned OFF.Then, the ON position of the signal (α) and the OFF state are recognized.
What should be noted about the F position is that it is not the absolute time position that matters, but the relative time magnitude. Therefore, no problem occurs even if the signal (α) is delayed as a whole.

第3図(b)乃至(f)は、このグリッチによる影響を
除去するために本実施例で行なわれる信号操作を示す。
FIGS. 3(b) to 3(f) show signal manipulation performed in this embodiment to eliminate the influence of this glitch.

第3図の波形(b)は、信号(α)をクロック信号で同
期化したもの、同図(C)の波形はそれをlクロック分
遅らせたもの、同図(d)の波形は更にそれを1クロッ
ク分遅らせたものを示す。ここで波形(e)と波形(d
)の論理積をとれば、同図(e)の波形が得られる。
The waveform (b) in Figure 3 is the signal (α) synchronized with a clock signal, the waveform (C) in Figure 3 is delayed by one clock, and the waveform in (d) is further synchronized with the clock signal. is delayed by one clock. Here, waveform (e) and waveform (d
), the waveform shown in (e) of the same figure is obtained.

波形(c)と(d)との論理積は、グリッチ人を除去す
る作用をもつ。次に、波形(c)と波形(d)との論理
和をとれば波形(f)が得られる。波形(f)からはグ
リッチBが除去されている。
The logical product of waveforms (c) and (d) has the effect of removing glitches. Next, waveform (f) is obtained by logically ORing waveform (c) and waveform (d). Glitch B has been removed from waveform (f).

このように、1クロックずらせた信号同士の論理積ある
いは論理和をとることにより、グリッチの幅が1クロッ
クよりも狭いものである限り、その影響を除くことがで
きる。そして波形(e)における信号期間は幅Pをもつ
が、yの期間的でTAGOUT信号を発行すれば、誤動
作を避けることができる。また同様に、波形(f)は信
号期間Qをもつが、この期間終了後の期間Q′にTAG
  OUT信号をOFFにする動作を行なうことにより
、誤動作を避けることができる。
In this way, by taking the AND or OR of signals shifted by one clock, the influence of the glitch can be removed as long as the width of the glitch is narrower than one clock. The signal period in waveform (e) has a width P, but if the TAGOUT signal is issued for a period of y, malfunctions can be avoided. Similarly, the waveform (f) has a signal period Q, but in the period Q' after the end of this period, the TAG
Malfunctions can be avoided by turning off the OUT signal.

第2図において、TAG  IN受信回路6乃至8は、
TAG  IN入力信号をクロックで同期化し、lクロ
ックだけずれた2つの信号波形を生成するための回路で
ある。ON論理回路15乃至17は、第3図の波形(e
)に相当する信号をつくるための論理積回路からなる。
In FIG. 2, TAG IN receiving circuits 6 to 8 are
This circuit synchronizes the TAG IN input signal with a clock and generates two signal waveforms that are shifted by l clocks. The ON logic circuits 15 to 17 operate according to the waveform (e
) consists of an AND circuit to create a signal corresponding to .

ON選択回路21はON駿理回路15乃至17の出力を
同時に読出す機能をもつ。
The ON selection circuit 21 has a function of simultaneously reading the outputs of the ON logic circuits 15 to 17.

第4図は、TAG  IN信号からON状態を検出する
ための具体回路例を示す。同図において、6乃至8は第
2図のTAG  IN受信回路に相当する3ステージの
遅延回路またはシフトレジスタである。n乃至器は3人
力ANDゲートであり、1g2図の0NIiil理回路
15乃至I7とON選択回路21との機能を併せたもの
である。
FIG. 4 shows an example of a specific circuit for detecting the ON state from the TAG IN signal. In the figure, 6 to 8 are three-stage delay circuits or shift registers corresponding to the TAG IN receiving circuit in FIG. Numerals n to 3 are three-man power AND gates, which combine the functions of the 0NIiil logic circuits 15 to I7 and the ON selection circuit 21 in Figure 1g2.

第2図のOFF論理回路18乃至加とOFF選択回路2
2とについても、はぼ同様な構成がとられている。第5
図は、その具体回路例を示す。同図において、6乃至8
は第2図のTAG  IN受り回路、(9)乃至32は
第2図のOFF論理回路18乃至加に相当する2人力O
Rゲート、簡乃至35社第2図のOFF選択回路22に
相当する2人力ANDゲートである。
OFF logic circuit 18 to OFF selection circuit 2 in FIG.
2 also has a similar configuration. Fifth
The figure shows an example of the specific circuit. In the same figure, 6 to 8
is the TAG IN receiving circuit in FIG. 2, and (9) to 32 are two-man power output circuits corresponding to the OFF logic circuits 18 to 32 in FIG.
The R gate is a two-man power AND gate corresponding to the OFF selection circuit 22 in FIG. 2.

再び第2図を参照する。上述したようにして生成された
各TAG  IN信号についてのON状態信号とOFF
状態信号とは、それぞれIII選択回路21と22とに
別々に集合化される。
Referring again to FIG. ON state signal and OFF state signal for each TAG IN signal generated as described above
The status signals are separately collected in III selection circuits 21 and 22, respectively.

制御部23は、制御シーケンス上、TAG  IN信号
がONに転換するのを待つ状態にあるときは、マイクロ
プログ2ムによりON選択回路21を指定するアドレス
すなわちON読出し選択信号を発生し、目的とする特定
のTAG−IN信号がON状態になったか否かを調べる
。もし該TAG  IN信号がON状態になったことが
検出されたときには、対応するTAG  OUT発行回
路9乃至11の1の信号レベルをONとする制御を行な
う。これは、OFF状態検出の場合も同様に適用される
When the control section 23 is in a state of waiting for the TAG IN signal to turn ON in the control sequence, the microprogram 23 generates an address specifying the ON selection circuit 21, that is, an ON read selection signal, and selects the target. Check whether a specific TAG-IN signal has become ON. If it is detected that the TAG IN signal is in the ON state, control is performed to turn the signal level 1 of the corresponding TAG OUT issuing circuits 9 to 11 ON. This applies similarly to the case of OFF state detection.

九だし、この場合には、TAG  IN信号のOFF状
態と検出したとき、当該TAG  IN信号に対応する
TAG  OUT信号のレベルをOFFとする制御を行
なう。
In this case, when the OFF state of the TAG IN signal is detected, control is performed to turn OFF the level of the TAG OUT signal corresponding to the TAG IN signal.

なお、選択回路21.22はゲート回路で構成したが、
これにラッチあるいはレジスタを組合わせることもでき
る。集合化された複数のON状態信号あるいはOFF状
態信号の中から、特定のTAGIN信号に関するものを
取り出すことは、通常の慣用技術の範囲内で行なわれる
Note that although the selection circuits 21 and 22 were configured with gate circuits,
This can also be combined with a latch or register. Extracting a signal related to a particular TAGIN signal from among a plurality of aggregated ON state signals or OFF state signals is within the scope of ordinary techniques.

(6)発明の効果 本発明によれば、入力されたTAG  IN信号から雑
音を排除したON状態信号とOFF状態信号という別個
の信号を生成し、かつON状態信号とOFF状11信号
とを適宜アドレス指定により読み出すことができるため
、チャネル装置の処理効率を向上させることができると
ともに、制御システムの構成を単純化できる効果がある
(6) Effects of the Invention According to the present invention, separate signals such as an ON state signal and an OFF state signal are generated by eliminating noise from the input TAG IN signal, and the ON state signal and the OFF state 11 signal are appropriately generated. Since it can be read by addressing, the processing efficiency of the channel device can be improved and the configuration of the control system can be simplified.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は従来のインタロック方式によるTAG信号の7
−ケンス説明図、第2図は本発明実施例の構成図、第3
図は実施例の動作を説明する信号タイミング図、第4図
は実施例中のON論理回路の詳細図、第5図は実施例中
のOFF論理回路の詳細図である。 図中、1はチャネル装置、2はI10装置、3乃至5は
TAG  IN発行回路、6乃至8はTAG  IN受
信回路、9乃至11はTAG  OUT信号発行回路、
12乃至14はTAG  OUT信号受信回路、15乃
至17はON論理回路、18乃至20はOFF論理回路
、21はON選択回路、22(工OFF選択回路、23
は制御部をそれぞれ示す。 特許出願人 富士通株式会社 代理人弁理士 長谷用 文廣 (外1名) 才1図 才3図 才2WI
Figure 1 shows 7 of the TAG signal using the conventional interlock system.
- Figure 2 is a configuration diagram of the embodiment of the present invention, Figure 3 is an explanatory diagram of the
4 is a detailed diagram of the ON logic circuit in the embodiment, and FIG. 5 is a detailed diagram of the OFF logic circuit in the embodiment. In the figure, 1 is a channel device, 2 is an I10 device, 3 to 5 are TAG IN issuing circuits, 6 to 8 are TAG IN receiving circuits, 9 to 11 are TAG OUT signal issuing circuits,
12 to 14 are TAG OUT signal receiving circuits, 15 to 17 are ON logic circuits, 18 to 20 are OFF logic circuits, 21 is an ON selection circuit, 22 (work OFF selection circuit, 23
indicates the control unit, respectively. Patent applicant Fujitsu Ltd. Representative Patent Attorney Fumihiro Hase (1 other person) 1, 3, 2 WI

Claims (1)

【特許請求の範囲】[Claims] チャネル装置のI10インタフェースがインタロック方
式で制御される複数のTAG  IN信号およびTAG
  OUT信号を有するものにおいて、I10装置から
の複数のTAG  、IN信号を受信する手段と、咳受
信したTAG  IN信号の各々についてON状態とO
FF状態とを検出し、それぞれについて状態信号を出力
する論理手段と、全てのTAG  IN信号についてO
NN書簡信号よびOFF状態信号を別々に集合化した2
組の信号手段と、該2組の信号手段を必要に応じて読出
すための選択手段と、をそなえていることを特徴とする
チャネル装置。
Multiple TAG IN signals and TAGs where the I10 interface of the channel device is controlled in an interlocking manner
In the device having an OUT signal, means for receiving a plurality of TAG, IN signals from the I10 device, and an ON state and an O state for each of the received TAG IN signals.
logic means for detecting the FF status and outputting a status signal for each, and for all TAG IN signals.
NN letter signal and OFF state signal are collected separately 2
1. A channel device comprising: a pair of signal means; and a selection means for reading out the two sets of signal means as necessary.
JP19021381A 1981-11-27 1981-11-27 Channel device Granted JPS5892023A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP19021381A JPS5892023A (en) 1981-11-27 1981-11-27 Channel device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP19021381A JPS5892023A (en) 1981-11-27 1981-11-27 Channel device

Publications (2)

Publication Number Publication Date
JPS5892023A true JPS5892023A (en) 1983-06-01
JPS617662B2 JPS617662B2 (en) 1986-03-07

Family

ID=16254344

Family Applications (1)

Application Number Title Priority Date Filing Date
JP19021381A Granted JPS5892023A (en) 1981-11-27 1981-11-27 Channel device

Country Status (1)

Country Link
JP (1) JPS5892023A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63304359A (en) * 1987-06-05 1988-12-12 Hitachi Ltd Data transfer control circuit

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63304359A (en) * 1987-06-05 1988-12-12 Hitachi Ltd Data transfer control circuit

Also Published As

Publication number Publication date
JPS617662B2 (en) 1986-03-07

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