JPH0690472A - Access arbitration system - Google Patents

Abstract

PURPOSE:To enable the elimination of the control line and signal line related to a contention control as hardwares and to eliminate the necessity of the propagation time of a contention control signal by providing with N request generation sources, M resources, a matrix switch means and a control circuit. CONSTITUTION:In this system, eight request generation sources R (1) to R (8) generating access requests, eight resources S (1) to S (8) shared by the request generation sources R (1) to R (8), a matrix switch 3 having 8X8 capacity where the request generation sources R (1) to R (8) are connected with input terminals 11 to 18 and the resources S (1) to S (8) are connected with output terminals 21 to 28, and a control circuit 4 controlling the connection and disconnection of the intersection point of the matrix switch 3 are provided. The access requests for all the resources S (1) to S (8) from all the request generation sources R (1) to R (8) can be coped with not performing the contention control between the request generation sources R (1) to R (8).

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention is used in an information processing apparatus, a communication exchange, particularly an ATM exchange, and other systems having a plurality of resources commonly connected by a bus.
Here, the resource means a memory device, an output device, a display device, an input device, a printing device, a functional unit, and other equipment accompanied by hardware for operating the system.

The present invention relates to arbitration of a plurality of access requests generated from within a system with respect to a plurality of shared resources arranged in one system.

[0003]

2. Description of the Related Art Arbitration of an access request according to the prior art will be described with reference to a model shown in FIG. 6, which is based on a ring arbiter control method. In this model, there are eight access request sources R (1) to R (8) and eight resources S (1) to S (8) that accept the access requests.
These are respectively connected to the input terminal group and the output terminal group of the matrix switch means. The matrix switch means may be provided with hardware of a matrix structure as shown in the drawing, or may be virtual one composed of a logic circuit having the illustrated matrix function capable of transmitting an access request. The number of access request sources and the number of resources are not necessarily equal.

The access request sources R (1) to R (8) generate access requests one after another. Since access requests are generated according to the circumstances of the source, a plurality of access requests may compete for one resource at the same time. The contention is arbitrated by the matrix switch means, and one access request generation source transmits the access request to one resource of a request destination. At this time, the ring arbiter RA
Each of (1) to RA (8) sweeps an access request as shown by an arrow in FIG. 6, and when the corresponding access request is reached, the access request is cleared through the intersection C (n, m). Only one is transmitted to the resource side, and the resource accepts the access request.

When one access request is accepted,
Information indicating that the request has been accepted is transmitted to the request source that has transmitted the access request. By accepting one access request, another access request sent to the ring arbiter is made to wait, and the other access request is detected at the next timing or at the next timing. After the access request is accepted, processing such as transfer of necessary data via this matrix switch means or via another bus signal line is executed.

[0006]

In such contention arbitration of access requests, the ring arbiters RA (1) to RA (8) for performing contention arbitration select one access request so that each pin is assigned to each terminal. A control line is needed to read the content of the access request being sent. Further, when one access request is selected, a signal line for transmitting the selection of the request from the control circuit to the corresponding access request generation sources R (1) to R (8) is required. Furthermore, the propagation time of the control signal propagating on the control line and the propagation time of transmitting information to the signal line transmitting the selection are required.

According to the present invention, the control line and the signal line as described above can be omitted as hardware, it is not necessary to provide the above-mentioned propagation time, and moreover, the throughput is impaired as compared with the prior art. The purpose is to provide a non-access request arbitration method. A further object of the present invention is to provide an access request arbitration method with a small hardware scale that can be implemented by adding software without providing special hardware. That is, an object of the present invention is to provide an access request arbitration method that has simple hardware and can operate at high speed.

[0008]

According to the present invention, N request generation sources (N is an integer of 2 or more) for generating access requests,
M resources (M is an integer of 2 or more) shared by the access request sources, the N request generation sources are connected to input terminals, and the M resources are connected to output terminals N × It is embodied in a device provided with a matrix switch means having a capacity of M and a control circuit for controlling connection / disconnection of intersection points of the matrix switch means.

Each of the access request sources is a resource in a broad sense, and may be one of the M resources depending on the device configuration. The matrix switch means may be a matrix switch in which switches composed of hardware are arranged at intersections of a matrix,
Further, it may be a virtual matrix switch in which a program control circuit realizes a circuit that substantially connects or disconnects an access request at the intersection.

The features of the present invention are as follows. The control circuit for controlling the disconnection of the intersections of the matrix switch means is prepared in advance with P disconnection patterns (P is an integer of 2 or more) for the disconnection of the intersections of the matrix switch means and stored in the memory. ing. Then, for each time slot that is synchronized with the timing signal sent from another timing generating means, the P connecting / disconnecting patterns are adopted so as to make one cycle in P timeslots, and the connecting / disconnecting of the matrix switch means is performed. And means for controlling the.

The resource is constructed so as to be able to receive an access request from one request generation source once in each time slot in synchronization with the time slot.

The request generation source includes a wait register for holding the number of the generated access request destination resource,
A counter that holds information relating to the request generation source corresponding to the P disconnection patterns, displays the number of the resource connected in the time slot in synchronization with the time slot, and holds in the wait register And a comparison execution unit that identifies the match between the displayed number and the number displayed on the counter and executes the access request.

The P connection patterns can all be connection patterns that connect one request generation source to one resource, and the wait register corresponds to a plurality of access requests. It is also possible to use a shift register that holds the number of each resource to be used as a queue.

In the case of holding the number of each resource as a queue, the comparison execution means, when a plurality of the numbers in the queue are identified as coincident, the access request having the highest priority in the queue is made. Select only one.

Further, another priority register for holding the priority is provided corresponding to the wait register, and the comparison execution means is provided when the coincidence is identified in a plurality of numbers in the queue. The access request having the highest priority in the corresponding priority register can be selected in preference to the priority of the queue.

Further, the P connection patterns may include at least a connection pattern that connects one request generation source to a plurality of resources. In this case, the wait register is a shift register that holds, as a queue, the number of each resource corresponding to a plurality of access requests, and the comparison execution means identifies the match with a plurality of numbers in the queue. In this case, the queue includes a means for selecting the earliest access request.

The request execution means may identify a match for all of the queue from the beginning to the end, but only from the beginning to the middle of the queue (D is an integer of 2 or more, search depth). It can be configured to identify the match.

[0018]

In the system of the present invention, the control circuit for controlling the matrix switch means adopts the preset P disconnection patterns for each time slot according to the lapse of time in the order in which they are set in advance. Then, the matrix switch means is disconnected. At the access request source, this time slot is always recognized, and at least information about itself regarding the P disconnection patterns is stored in advance, and which resource the own system is connected to at each time slot. We are aware of whether or not.
The number of this uniquely recognized resource is displayed on the counter.

On the other hand, on the access request source side, when an access request is generated, the resource number of the request destination is stored in the register and stands by. When the number stored in this register matches the number displayed on the counter, it means that only the own system is issuing an access request to the resource of that number, so the resource side or the matrix switch means is controlled. You do not have to receive any information from the side. That is, since it is not necessary to receive the control information or the information that can accept the access request, the hardware for that is not necessary, and the time for transmitting such information is also unnecessary. Therefore, the hardware can be simplified and the control can be speeded up.

Conveniently, the registers are queue registers. That is, when the number of the destination resource of the access request generated in the own system is stored in this register as a queue, the access requests that match the number displayed in the counter are executed in the order of the queue. .

In addition to the queue, another register for designating the priority can be provided and the access request in the queue can be associated with the priority. Whether or not the priority specification conflicts with the queue priority can be set by applying logic.

The method of the present invention does not lower the throughput as compared with the conventional method. Most of the method of the present invention can be realized by preparing the software of the program control circuit. The access request source side register, counter, comparison and identification means, etc. can be realized by modifying the software of the access request program control circuit without substantially providing hardware.

[0023]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The configuration of the first embodiment of the present invention will be described with reference to FIGS. FIG. 1 is an overall configuration diagram of the first embodiment of the present invention. FIG. 2 is a block diagram of a request generation source in the first embodiment of the present invention.

According to the present invention, eight request generation sources R (1) to R (8) for generating access requests and eight request generation sources R (1) to R (8) for this access are shared. Resource S (1) ~
S (8) and eight request generation sources R (1) to R (8) are connected to the input terminals ₁₁ to ₁₈ to provide eight resources S (1) to S (8).
Are connected to the output terminals 2 _{1 to} 2 ₈ and have a capacity of 8 × 8, and the matrix switch 3
Is an access arbitration method including a control circuit 4 for controlling the disconnection of the intersection points of

Here, the feature of the present invention is that the control circuit 4 includes only one request generation source R (1) to R (R).
(8) and one resource S (1) to S (8) are connected in advance, and there are P disconnection patterns (P is an integer of 2 or more) that are connection patterns.
It includes means for controlling the disconnection of the matrix switch 3 by adopting the same disconnection pattern as one cycle in P timeslots, and the resources S (1) to S (8) are synchronized with the timeslot. Means for accepting access requests from one request generation source R (1) to R (8) once for each time slot, and the request generation sources R (1) to R (8) include , The shift register 6 which is a waiting register for holding the numbers of the generated access request destination resources S (1) to S (8)
And information relating to the request generation sources R (1) to R (8) corresponding to the P disconnection patterns, and the resource S (connected to the time slot in synchronization with the time slot). 1) Counter 5 that displays the numbers S to S (8),
The comparison execution unit 9 identifies a match between the number held in the shift register 6 and the number displayed in the counter 5 and executes the access request. The comparison execution unit 9 selects the access request with the highest priority in the queue when the plurality of numbers in the shift register 6 are identified.

Next, the operation of the first embodiment of the present invention will be described. In FIG. 1, the connection state between the request generation sources R (1) to R (8) and the resources S (1) to S (8) is indicated by a black circle at the intersection of the grid wiring. According to FIG. 1, R (1) ⇔ S (1) [intersection point Xp
(1, 1)], R (2) ⇔ S (2) [Intersection point Xp (2,
2)], R (3) ⇔ S (3) [Intersection Xp (3, 3)], R
(4) ⇔ S (4) [Intersection Xp (4, 4)], R (5) ⇔ S (5)
[Intersection Xp (5, 5)], R (6) ⇔ S (6) [Intersection Xp
(6, 6)], R (7) ⇔ S (7) [Intersection Xp (7,
7)], R (8) ⇔ S (8) [intersection point Xp (8, 8)] are set as accessible combinations at this timing. Therefore, in the example of FIG. 1, it is possible to generate any request source by circulating other seven types of combinations of the resources S (1) to S (8) for the other request sources R (1) to R (8). R (1) to R (8) can access any resource S (1) to S (8). In the control circuit 4, the time slot synchronizing signal is input and the pattern is sequentially changed in synchronization with the timing.

In FIG. 2, SR (d) [d = 1, ...,
D] is a constituent element of the shift register 6 and includes a comparator CP.
(d) [d = 1, ..., D] is the value Q and SR (d) of the counter 5
Compare with the value of.

The comparison execution unit 9 includes a comparator CP (d) [d =
The value of d in 1, ..., D] is set, and the search range, that is, the search depth is set. In the range not included in the search depth, the value of SR (d) is sequentially stored and shifted.

The request generator 7 outputs the access request and the resource numbers of the resources S (1) to S (8) for which the access is requested, and transfers the resource numbers to the shift register 6. The shift register 6 sequentially stores the resource numbers from SR (D) to SR (1). Comparator CP
The value Q commonly given to (d) is the resources S (1) to S (S) that can be accessed and are determined in advance at the current timing.
It is the number of (8).

The resource number held by SR (d) and the value Q
If they match, CP (d) outputs a match flag F (d). The position number of SR (d) with which the resource number matches d =
d1, d2, d3, d4, d5 ... (d1 <d2 <d3 <
If d4 <d5 ...), the permission is given to the access request having the smallest d among the coincidence flags F (d) of the comparator CP (d).

Therefore, access permission is given to the access request corresponding to SR (d1), the data of SR (d1) is deleted, the data of SR (d1 + 1) is transferred to SR (d1), and the subsequent data is transferred. Pack one by one. In FIG. 2, d1 = 2, d
2 = 3, permission is given to the access request corresponding to SR (2), and data after SR (3) is shifted.

By performing such processing cyclically for the combinations shown in FIG. 1, all request generation sources can be executed without performing competition control between the request generation sources R (1) to R (8). R (1)
It is possible to respond to access requests for all resources S (1) to S (8) from .about.R (8).

The combination of the next timings in the matrix switch 3 is R (1) ⇔S (2) [intersection Xp (1,
2)], R (2) ⇔ S (3) [Intersection Xp (2, 3)], R
(3) ⇔ S (4) [Intersection Xp (3, 4)], R (4) ⇔ S (5)
[Intersection Xp (4,5)], R (5) ⇔ S (6) [Intersection Xp
(5,6)], R (6) ⇔ S (7) [Intersection Xp (6,
7)], R (7) ⇔ S (8) [Intersection Xp (7, 8)], R
(8) ⇔ S (1) [intersection point Xp (8, 1)]. By sequentially shifting in this way, all combinations can be realized.

In the first embodiment of the present invention, the request source R (1)
.About.R (8) and resources S (1) .about.S (8) are each eight, but can be configured regardless of the numbers. Also,
Although only one access was allowed at a time, multiple accesses can be allowed at once. For example, if the number of permits is 4,
It is also possible to give access permission to SR (d1), SR (d2), SR (d3), and SR (d4), and perform access in this order. Further, request sources R (1) to R (8) and resources S (1) to S (8)
It is also possible to adopt a configuration in which the combination cyclic order and cyclic cycle are arbitrarily set.

Next, a second embodiment of the present invention will be described with reference to FIGS. FIG. 3 is an overall configuration diagram of the second embodiment of the present invention. FIG. 4 is a block diagram of a request generation source in the second embodiment of the present invention. In the second embodiment of the present invention, one request generation source R (1) to R (4) can access two resources S (1) to S (8) at the same time. In FIG. 3, R (1) ⇔ S (1), S (2) [intersection Xp (1,
1), Xp (1, 2)], R (2) ⇔ S (3), S (4) [Intersection points Xp (2, 3), Xp (2, 4)], R (3) ⇔ S (5 )
, S (6) [intersection points Xp (3, 5), Xp (3, 6)],
R (4) ⇔ S (7), S (8) [Intersection point Xp (4, 7), Xp
(4, 8)] is an accessible combination. Here, the combination of the two resources S (1) to S (8) with respect to one request generation source R (1) to R (4) is arbitrary. Therefore,
As shown in FIG. 3, the combination of resources S (1) to S (8) is fixed, and any other request generation source R (1) is selected by the other three combinations.
.About.R (4) can access any resource S (1) .about.S (8).

In FIG. 4, the request generator 7 outputs the access request and the resource number for which the access is requested, and transfers this to the shift register 6. The shift register 6 sequentially stores resource numbers from SR (D) to SR (1). The values Q1 and Q2 commonly given to the comparator CP (d) are the resource numbers m1 and m2 of the resource S (m) [m = 1, 2, ..., 8] set at the current timing in advance. .

Resource number and value Q1 held by SR (d)
If they match, the comparator CP (d) determines that the match flag F1
When (d) is output and the value Q2 matches, the match flag F
Output 2 (d).

The position number of the SR (d) whose resource number matches m1 is d = d1, d2, d3, d4, d5 ... (d1
<D2 <d3 <d4 <d5 ...), and S that matches m2
The position number of R (d) is d = d1 ', d2', d3 ', d
4 ', d5' ... (d1 '<d2'<d3'<d4'<d
5 '...). One comparator CP (d) does not output two coincidence flags F1 (d) and F2 (d) at the same time. Of the coincidence flags F1 (d) and F2 (d) of the comparator CP (d), permission is given to the access request with the smallest d. Therefore, m corresponding to SR (d1) and SR (d1 ')
Give access permission to access request to 1 and m2,
The data of SR (d1) and SR (d1 ′) are deleted, and SR
The data of (d1 + 1), SR (d1 '+ 1) is converted into SR (d1), S
Transfer to R (d1 ') and enclose subsequent data one by one.

In FIG. 4, d1 = 2, d2 = 5, d
1 '= 1, d2' = 3, and SR for S (m1)
In (2), permission is given to S (m2) for the access request corresponding to SR (1). Next, after deleting SR (1) and SR (2), the data after SR (3) is shifted to prepare for the next access. By performing this process cyclically for the combinations shown in FIG. 3, all the resources S (1) to S (S) from all the request generation sources R (1) to R (4) are performed without performing the competition control. Can respond to access requests for (8). In FIG. 3, the next timing combination is R (1) ⇔
S (3), S (4) [Intersection points Xp (1, 3), Xp (1,
4)], R (2) ⇔ S (5), S (6) [Intersection Xp (2,
5), Xp (2,6)], R (3) ⇔ S (7), S (8) [Intersection point Xp (3, 7), Xp (3, 8)], R (4) ⇔ S (1 )
, S (2) [intersection points Xp (4, 1), Xp (4, 2)],
Becomes

In the second embodiment of the present invention, the demand source R (1)
Although the number of R (4) is four and the number of resources S (1) to S (8) is eight, they can be configured regardless of the number. Further, the number of resources S (1) to S (8) permitted to output to one request generation source R (1) to R (4) can be two or more. Further, although only one access is permitted to one resource S (1) to S (8) at a time, it is also possible to permit a plurality of arbitrary accesses at a time. If the number of permits for S (m1) is 4 and the number of permits for S (m2) is 3, then SR (d1), S
R (d2), SR (d3), SR (d4) and SR (d1 '), SR
(d2 ') and SR (d3') can be granted access and access can be performed in this order. Furthermore, the request source R
The combination cyclic order of (1) to R (4) and the resources S (1) to S (8) and the cyclic period can be arbitrarily configured.

Next, a third embodiment of the present invention will be described with reference to FIG. FIG. 5 is a block diagram of a request generation source in the third embodiment of the present invention. The third embodiment of the present invention is another example of the access priority control in the first embodiment of the present invention. Here, an access request is generated from the outside and the priority order of the access request is added to the access requests generated in time series. Here, d ′ is in descending order of priority.
The ranking is [d '= 1, ..., D].

In FIG. 5, the priority shift register 1
0 is synchronized with the shift register 6, and the comparator CP '
(d) compares the values of both the priority shift register 10 and the shift register 6 with the value Q of the counter 5 for three types of numerical values. NC (d) is SR (d) of the shift register 6
Is a component of the priority shift register 10 corresponding to.

The request generator 7 outputs the access request and the resource number for which the access is requested, and transfers this to the shift register 6. At the same time, a priority number (NO) is arbitrarily added to the access request from the outside and transferred to the priority shift register 10. The shift register 6 sequentially stores the resource numbers from SR (D) to SR (1) and the priority shift register 10 stores from NC (D) to NC (1). There is a one-to-one correspondence between SR (d) and NC (d). That is, by the position d, the comparator CP ′ (d) can simultaneously refer to the request resource position of the d-th generated access request and the priority d ′ of the request.

The value Q commonly given to CP '(d) is
Resource S (1) that has been determined in advance at that timing
This is the resource number of S (8). When the resource number held by CP '(d) matches the value Q and the priority order held by NC (d) is d'≤d "[d" = 1, ..., D], the match flag F Output ′ (d). Among the matching flags F '(d) of CP' (d), the access request with the smallest value of NC (d) (the highest priority) is granted.
Therefore, in FIG. 5, the access request to the resource number S (m) is given, and the access permission is given to the access request corresponding to SR (3) of the priority order d '= 2. Thus
The data (m) of SR (3) is deleted, and the data after SR (4) is shifted to SR (3) one by one to prepare for the next access.

In the third embodiment of the present invention, only one access is permitted at one time, but it is also possible to permit a plurality of accesses at one time. If the number of permits is three, SR (3), SR (2), SR
You can give access permission to (D) and access in this order.

[0046]

As described above, according to the present invention, the control line and the signal line related to the competition control can be omitted as hardware, and it is not necessary to provide the propagation time of the competition control signal. It does not impair the throughput as compared with the prior art. Furthermore, since the present invention can be implemented by adding software without providing special hardware, the hardware scale can be reduced. That is, the present invention can realize an access request arbitration method that has simple hardware and can operate at high speed.

[Brief description of drawings]

FIG. 1 is an overall configuration diagram of a first embodiment of the present invention.

FIG. 2 is a block diagram of a request generation source according to the first embodiment of the present invention.

FIG. 3 is an overall configuration diagram of a second embodiment of the present invention.

FIG. 4 is a block diagram of a request generation source according to a second embodiment of the present invention.

FIG. 5 is a block diagram of a request generation source according to a third embodiment of the present invention.

FIG. 6 is a configuration diagram of a conventional example.

[Explanation of symbols]

1 ₁ to ₁₈ Input terminal 2 ₁ to 2 ₈ Output terminal 3 Matrix switch 4 Control circuit 5 Counter 6 Shift register 7 Request generation unit 9 Comparison execution unit 10 Priority shift register CP Comparator R (1) to R (8) Request source S (1) to S (8) Resource Xp Intersection

Claims (6)

[Claims] 1. N request generation sources (N is an integer of 2 or more) that generate access requests, M resources (M is an integer of 2 or more) shared by the access request sources, and the N Matrix switch means having N × M capacitors connected to the input terminals and the M resources connected to the output terminals, and a control circuit for controlling connection / disconnection of intersections of the matrix switch means. In the access arbitration system including the above, the control circuit is prepared in advance with P (where P is an integer of 2 or more) disconnection patterns, and the P disconnection patterns are sequentially provided P times for each time slot. And a means for controlling connection / disconnection of the matrix switch means, wherein the resources are synchronized with the time slots and are provided once for each time slot. Means for accepting an access request from a request generation source, wherein the request generation source holds a waiting register for holding the number of an access request destination resource that has occurred, and the request generation corresponding to the P disconnection patterns. A counter that holds information related to the source and displays the number of the resource connected in the time slot in synchronization with the time slot; and the number held in the wait register and the number displayed in the counter. An access arbitration method comprising: a comparison execution unit that identifies a match and executes the access request. 2. The access arbitration method according to claim 1, wherein all the P connection patterns are connection patterns that connect one request generation source and one resource. 3. The wait register is a shift register that holds a number of each resource corresponding to a plurality of access requests as a queue, and the comparison execution means identifies the coincidence with a plurality of numbers in the queue. 3. The access arbitration method according to claim 2, further comprising means for selecting an access request having the earliest priority in the queue. 4. A priority register holding a priority corresponding to the wait register is provided, and the comparison execution means corresponds to a plurality of numbers in the queue when the match is identified. 4. The access arbitration method according to claim 3, further comprising means for selecting an access request having the highest priority of the priority register in priority to the priority of the queue. 5. The P disconnection patterns include a disconnection pattern that connects at least a part of one request generation source to a plurality of resources, and the wait register corresponds to a plurality of access requests. A shift register that holds a resource number as a queue, wherein the comparison execution means selects an access request with the highest priority in the queue when the matches are identified with a plurality of numbers in the queue. The access arbitration method according to claim 1, further comprising means. 6. The access arbitration according to claim 3, wherein the request execution means includes means for identifying the match only from the head of the queue to the D-th (D is an integer of 2 or more). method.