JPH0690233A - Access arbitration system - Google Patents

Abstract

PURPOSE:To improve the throughput of an access request by performing one time of arbitration control for the access request generated from each request generation source at every time slot, and controlling the connection/disconnection of a large number of intersections of a matrix switch simultaneously at every time slot according to a result of arbitration control. CONSTITUTION:This system is equipped with a shift register that is a standby register which holds the source number of the request destination of the access request generated at each of the request generation sources R(1)-R(8) as a queue, respectively. A control circuit 4 is provided with an arbitration part 10 including a means which retrieves whether or not the numbers of resources S(1)-S(8) exist up to the depth of the shift register set respectively in accordance with the resources S(1)-S(8), and a means which performs the arbitration control on the request generation sources R(1)-R(8) in which the presence of the numbers of the resources S(1)-S(8) is identified by the retrieval means at every resource number. The connection/disconnection of the intersection >= one of a matrix switch circuit 3 can be controlled at every slot according to the result of such arbitration control.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention is used in an information processing apparatus, a communication exchange, particularly an ATM exchange, and other systems having a plurality of resources commonly connected by a bus.
Here, the resource means a memory device, an output device, a display device, an input device, a printing device, a functional unit, and other equipment accompanied by hardware for operating the system.

The present invention relates to arbitration of a plurality of access requests generated from within a system with respect to a plurality of shared resources arranged in one system.

[0003]

2. Description of the Related Art The arbitration of access requests according to the prior art will be described with reference to a model shown in FIG. 5, which is based on a ring arbiter control method. In this model, there are eight access request sources R (1) to R (8) and eight resources S (1) to S (8) that accept the access requests.
These are respectively connected to the input terminal group and the output terminal group of the matrix switch means. The matrix switch means may be provided with hardware of a matrix structure as shown in the drawing, or may be virtual one composed of a logic circuit having the illustrated matrix function capable of transmitting an access request. The number of access request sources and the number of resources are not necessarily equal.

The access request sources R (1) to R (8) generate access requests one after another. Since access requests are generated according to the circumstances of the source, a plurality of access requests may compete for one resource at the same time. The contention is arbitrated by the matrix switch means, and one access request generation source transmits the access request to one resource of a request destination. At this time, the ring arbiter RA
Each of (1) to RA (8) sweeps the access request as shown by an arrow in FIG. 5, and when the corresponding access request is reached, the access request is cleared through the intersection C (n, m). Only one is transmitted to the resource side, and the resource accepts the access request.

When one access request is accepted,
Information indicating that the request has been accepted is transmitted to the request source that has transmitted the access request. By accepting one access request, another access request sent to the ring arbiter is made to wait, and the other access request is detected at the next timing or at the next timing. After the access request is accepted, processing such as transfer of necessary data via this matrix switch means or via another bus signal line is executed.

FIG. 6 is a conceptual diagram for explaining the operation of this ring arbiter. The number of the resource of the request destination is displayed as an access request from each of the request generation sources R (1) to R (8). Arbitration control is performed by resource S (1)
It is executed every S (8). Now, the m-th resource S in FIG.
Arbitration control is being executed for (m). The access request from each of the request generation sources R (1) to R (8) is searched, and it is searched whether or not there is any requesting access to the resource S (m). In this example, the second request generation source R (2) issues an access request to the mth resource. In arbitration control, when this is found, the request generation source R (2) is connected to the resource S (m). When one is connected, another request source R (1), R (3) -R
(8) is not connected.

If there is one request generation source R (1) to R (8) that is currently issuing an access request to the m-th resource S (m), the request will be accepted immediately. If there is any conflict between them, arbitration is performed, one is selected, and the request is accepted. The arbitration logic can be set in various ways. Here, it is assumed that the request generation sources R (1), R (2), ..., R (n) are cyclically executed. This logic can be set equally for each request source, prioritize the request sources, or any other logic.

[0008]

In such access request arbitration control, the ring arbiters RA (1) to RA (8) for performing arbitration in the case of contention each request in one time slot. Only one access request from the source can be accepted. Even if a plurality of access requests have already been generated for each request generation source and are waiting by forming a queue as shown in the left end of FIG. 6, only the access request indicated by the diagonal line at the head is subject to contention arbitration. Therefore, the access request after the second queue must wait at least the next time slot.

If, at one request source, the access request at the head of the queue is the second resource S (2) and the second access request in the queue is the resource S (3), this Resource S (2) in time slot
Is in a race condition with another request source and is not accepted, and if the resource S (3) has no access request from another request source, the access request to the resource S (3) is accepted. It should have been nice. That is, the intersection of this request generation source of the matrix switch means and the resource S (3) is not used in this time slot. This means that the matrix switch means is not used for the convenience of arbitration control although there is still a margin, and the throughput of access requests is substantially suppressed.

An object of the present invention is to improve this, and to provide an access arbitration method for improving the throughput of access requests.

[0011]

According to the present invention, N request generation sources (N is an integer of 2 or more) for generating access requests,
M resources (M is an integer of 2 or more) shared by the access request sources, the N request generation sources are connected to input terminals, and the M resources are connected to output terminals N × It is embodied in a device provided with a matrix switch means having a capacity of M and a control circuit for controlling connection / disconnection of intersection points of the matrix switch means. This control circuit, for access requests generated from the N request generation sources,
Arbitration control is performed once for each time slot, and connection / disconnection of a large number (strictly 1 or more) of intersections of the matrix switch means is controlled simultaneously for each time slot according to the result of the arbitration control.

Each of the access request sources is a resource in a broad sense, and may be one of the M resources depending on the device configuration. The matrix switch means may be a matrix switch in which switches composed of hardware are arranged at intersections of a matrix,
Further, it may be a virtual matrix switch in which a program control circuit realizes a circuit that substantially connects or disconnects an access request at the intersection.

Here, the feature of the present invention resides in that it is provided with a register for holding, as a queue, resource numbers of request destinations of access requests generated corresponding to respective request generation sources. Then, the control circuit has a means for searching whether or not there is a number of the resource up to the depth set in the wait register corresponding to the resource, and the searching means has identified that there is the number of the resource. An arbitration control is performed for each resource number of the request generation source.

A priority order register for holding a priority order is provided corresponding to each stage of the waiting register, and when the searching means identifies a plurality of resource numbers, the corresponding priority order register is designated. The arbitration control can be performed according to the held priority.

[0015]

According to the method of the present invention, the control circuit for controlling the matrix switch means executes the arbitration control when the access requests from the plurality of request generation sources compete for each time slot with the passage of time. Based on the result of the arbitration control, the access request is accepted only once in each time slot by setting the intersection of the matrix switch means to the connected state. That is, within one time slot period, the arbitration control is first executed, and then the connection state is created only once at one intersection. Therefore, one request source can make an access request only once in one time slot. One resource can accept an access request only once in one time slot.

According to the method of the present invention, the register provided corresponding to each request generation source holds the resource number of the request destination of the access request generated from the request generation source as a queue. Then, a search is performed from the head of the queue to a preset depth in order for an access request to the resource number. Therefore, as compared with the conventional method in which only one access request can be displayed for each request generation source, a search can be executed in one time slot for a plurality of access requests held in the waiting register. The possibility that an access request will be accepted increases, and the throughput improves.

The arbitration control can be sequentially executed for n resources S (1) to S (n) connected to one matrix switch means, or can be executed in parallel in time. it can.

[0018]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The configuration of the first embodiment of the present invention will be described with reference to FIGS. FIG. 1 is a block diagram of the first embodiment of the present invention. FIG. 2 is a block diagram of a request generation source according to the first embodiment of the present invention.

According to the present invention, eight request generation sources R (1) to R (8) for generating access requests and eight request generation sources R (1) to R (8) for this access are shared. Resource S (1) ~
S (8) and eight request generation sources R (1) to R (8) are connected to the input terminals ₁₁ to ₁₈ to provide eight resources S (1) to S (8).
A matrix switch 3 but having a capacitance of the output terminal 2 ₁ to 2 ₈ is connected to the 8 × 8, 8 pieces of request generation source R (1) ~
A matrix that controls the arbitration control once for each time slot for the access request generated from R (8) and controls the disconnection of one or more intersection points of the matrix switch 3 for each time slot according to the result of the arbitration control. This is an access arbitration system including a control circuit 4 including a switch connection / disconnection section 11.

Here, a feature of the present invention is a wait register that holds, as a queue, resource numbers of request destinations of access requests generated for each of the request generation sources R (1) to R (8). The shift register 6 is provided, and the control circuit 4 corresponds to the resources S (1) to S (8).
Of the resources S (1) to S
(8) means for searching for the numbers, and the request generating sources R (1) -R (8) for identifying the resources S (1) -S (8) by the searching means. ), An arbitration unit 10 including means for performing arbitration control for each resource number.
Is equipped with.

Next, the operation of the first embodiment of the present invention will be described. In FIG. 2, SR (1) to SR (D) represent constituent elements of the shift register 6. In the access request generator 7,
The position numbers of the resources S (1) to S (8) for which access is requested are output and transferred to the shift register 6. here,
This position number is stored in the shift register 6 in the order of SR (1), ..., SR (D).

Resource S performed by the arbitration unit 10 of the control circuit 4
The search order of the access request from the request generation source R (n) for (m) is SR (1), ..., SR (8). This SR
The search range is from (1) to SR (d), and d is called the number of searches, that is, the search depth.

In FIG. 2, the search depth of the request generation source R (n-1) is d ', the search depth of the request generation source R (n) is d, and the search depth of the request generation source R (n + 1) is. d ″.

First, the SR (1) (●) of the request generation source R (n−1)
The search is started from (), and SR (d ') is searched in this order. If the shift register 6 in the request generation source R (n-1) has no access request to the resource S (m), the access right is transferred to the next request generation source R (n).

Next, in the request generation source R (n), SR
The search starts from (1), and SR (d) is searched in this order. Here, an access request to the resource S (m) exists in SR (4), and the output permission flag F is output from SR (4) to the arbitration unit 10 of the control circuit 4. At the request generation source R (n), the data of SR (4) is deleted and the data of SR (5) and thereafter are filled.

Upon receiving the output permission flag F from SR (4), the arbitration unit 10 of the control circuit 4 controls the matrix switch connection / disconnection unit 11 to execute the access relating to SR (4).

Next, SR (1) of the request generation source R (n + 1)
The search starts from (○). This time the permissions are
It is given to SR (3) of the request source R (n + 1).

Next, a second embodiment of the present invention will be described with reference to FIG. FIG. 3 is a block diagram of the second embodiment of the present invention. The feature of the second embodiment of the present invention is that S in the first embodiment of the present invention is
The priority number NO is given to the position numbers of the resources S (1) to S (8) stored in R (d).

A second shift register 9 is provided in parallel with the shift register 6, and in synchronization with the access request transferred from the access request generator 7 to the shift register 6, the priority number NO is externally assigned to the second shift register. Transfer to 9.

NC (1) to NC (D) are constituent elements of the second shift register 9 and have a one-to-one correspondence with SR (1) to SR (D) which are constituent elements of the shift register 6. . That is, the value k (k = 1, ..., D,) of NC (d) is the search order of access requests in the request generation source R (n) for the resource S (m) in this order. The range in which SR (d) corresponding to NC (d) = 1, ..., K is searched, and k is the number of searches, that is, the search depth. The search depth of the request source R (n-1) is k ',
The search depth of the request source R (n) is k, and the request source R (n + 1)
The search depth of is k ″.

First, in the request generation source R (n-1), the search is started from SR (2) corresponding to NC (2) whose priority number NO is "1", and the priority number NO is "k". ’” N
SR (d ') corresponding to C (d') is searched in ascending order of priority number NO. That is, in the request generation source R (n−1), SR (2) (marked with ●), SR (1), SR (4), S
Search in the order of R (5), ..., SR (d ′). Request source R
When there is no access request to the resource S (m) in the shift register 6 in (n-1), the access right is transferred to the next request generation source R (n).

Subsequently, in the request generation source R (n), the search is started from SR (3) whose priority number NO is "1", and the search is continued up to SR (d) where NC (d) = k or less. Search in order. There is an access request for the resource S (m) in SR (5) whose priority number is "2", and SR (5) outputs the output permission flag F to the control circuit 4. At the request generation source R (n), the data of SR (5) is deleted and the data of SR (6) and subsequent ones are filled. Further, subtract each "1" from the NC (d) having the data of the priority number NO "2" or later,
After raising the priority number NO, the data after NC (6) is filled.

Upon receiving the output permission flag F from SR (5), the arbitration unit 10 of the control circuit 4 controls the matrix switch connection / disconnection unit 11 to execute an access regarding SR (5).

Subsequently, in the request generation source R (n + 1),
The search is started from SR (5) whose priority number is "1", and SR (d ") whose NC (d") = k "or less are searched in this order. The priority number is" 2 ". SR (3) has an access request for resource S (m), and SR (3)
Outputs an output permission flag F ′ to the control circuit 4.
At the request source R (n + 1), the data of SR (3) is deleted and S
Fill in the data after R (4). Furthermore, the priority number N
N "1" is subtracted from each NC (d ") that has data of" 2 "or later, and the priority number NO is advanced to N.
Fill in the data after C (4).

Upon receiving the output permission flag F'from SR (3), the arbitration unit 10 of the control circuit 4 controls the matrix switch connection / disconnection unit 11 to execute the access relating to SR (3).

Next, a third embodiment of the present invention will be described with reference to FIG. FIG. 4 is a block diagram of the essential parts of a third embodiment of the present invention. The third embodiment of the present invention is characterized in that the control circuit 4 in the first and second embodiments of the present invention includes a priority order setting unit PR (1).
It is in the place where the PR (8) is provided. This priority setting section P
R (1) to PR (8) are SRT (1) to SRT which are shift registers 6 provided in the request generation sources R (1) to R (8), respectively.
The access request amount stored in RT (8) is monitored, and the priority order of starting the search from the request generation sources R (1) to R (8) having a large amount is added.

In FIG. 4, request sources R (5), R
(8), R (2), R (6), R (3), R (7), R (1), R
The search is performed in the order of (4). Each request source R
The search method in (1) to R (8) is the same as in the first or second embodiment of the present invention. The advantage of the third embodiment of the present invention is that the priorities are set in the order of the largest access request amount, so that the access request amounts held by the respective request generation sources R (1) to R (8) are kept uniform. There is a place where you can do it.

In the first to third embodiments of the present invention, the request generation sources R (1) to R (8) and the resources S (1) to S (8).
Although the description has been made with the number of eight, it can be arbitrarily configured. Further, the request generation sources R (1) to R (8) and the resource S
The numbers of (1) to S (8) may not be equal.

In the first and second embodiments of the present invention, when output permission is given to one SR (d) of the request generation source R (n), the access right is transferred to the next request generation source R (n + 1). However, the search may be restarted from the SR (d + 1) next to the SR (d) to which the output permission of the request generation source R (n) is given. It is also possible to allow a plurality of accesses at once.

In the third embodiment of the present invention, the reference for setting the priority is the accumulated amount of access requests, but it may be arbitrarily given from the outside.

[0041]

As described above, according to the present invention, since the number of access request searches is plural, the probability of being granted access is greatly improved. Therefore, the throughput of access requests can be improved.

[Brief description of drawings]

FIG. 1 is a configuration diagram of a first embodiment of the present invention.

FIG. 2 is a configuration diagram of a request generation source according to the first embodiment of the present invention.

FIG. 3 is a configuration diagram of a second embodiment of the present invention.

FIG. 4 is a configuration diagram of main parts of a third embodiment of the present invention.

FIG. 5 is a configuration diagram of a conventional example.

FIG. 6 is a diagram showing competitive arbitration by a ring arbiter.

[Explanation of symbols]

1 ₁ to 1 ₈ input terminal 2 ₁ to 2 ₈ output terminal 3 matrix switch 4 control circuit 6 shift register 7 access request generation unit 9 second shift register 10 arbitration unit 11 matrix switch disconnection unit NO priority number PR (1 ) ~ PR (8) Priority setting section R (1) ~ R (8) Request source RA (1) ~ RA (8) Ring arbiter S (1) ~ S (8) resource

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁵ Identification code Internal reference number FI Technical display location H04L 12/44 12/48 H04Q 3/52 A 9076-5K 8732-5K H04L 11/20 Z

Claims (2)

[Claims] 1. N request generation sources (N is an integer of 2 or more) that generate access requests, M resources (M is an integer of 2 or more) shared by the access request sources, and the N Number of request generation sources are connected to input terminals and the M number of resources are connected to output terminals, and matrix switch means having a capacity of N × M, and access requests generated from the N number of request generation sources, In an access arbitration system including a control circuit for performing arbitration control once for each time slot and controlling the connection / disconnection of one or more intersections of the matrix switch means for each time slot according to the result of the arbitration control, The control circuit is provided with a wait register that holds a resource number of a request destination of an access request generated for each request generation source, as a queue, Means for searching for the number of the resource up to the set depth of the storage register, and arbitration control for each resource number of the request generation source identified by the searching means as having the number of the resource And an access arbitration method. 2. A priority order register for holding a priority order is provided corresponding to each stage of the waiting register, and the control circuit has identified that the resource number is plural by the searching means. The access arbitration method according to claim 1, further comprising means for performing arbitration control according to the priority held in the corresponding priority register.