JP3107122B2 - Access arbitration method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention is applied to an information processing apparatus, a communication exchange, in particular, an ATM exchange, and other systems having a plurality of resources commonly connected by a bus.
Here, the resource refers to a memory device, an output device, a display device, an input device, a printing device, a functional unit, and other facilities including hardware for operating the system.

[0002] The present invention relates to arbitration of a plurality of access requests generated within a system with respect to a plurality of shared resources arranged in one system.

[0003]

2. Description of the Related Art The arbitration of access requests according to the prior art will be described with reference to a model shown in FIG. 7, which is based on a control method of a ring arbiter. This model includes eight access request sources R (0) to R (7) and eight resources S (1) to S (S) for receiving the access request.
(7). These are connected to the input terminal group and the output terminal group of the matrix switch means, respectively. The matrix switch means may be provided with hardware having a matrix configuration as shown in the figure, or may be a virtual one constituted by a logic circuit having a matrix function as shown and capable of transmitting an access request. The number of access request sources and the number of resources do not necessarily have to be equal.

Access request sources R (0) to R (7)
Generates access requests one after another. Since an access request is generated according to the circumstances of the source, a plurality of access requests may simultaneously compete for one resource S (m). The contention is arbitrated by a control circuit that controls the matrix switch means, and one access request source R (n) is transmitted to one request destination resource S (m). At this time, ring arbiter RA
Each of (1) to RA (8) sweeps an access request as indicated by an arrow in FIG. 7 and, when the corresponding access request is reached, the access request is reduced via the intersection C (n, m). Only one resource S (m) is transmitted to the resource S (m).
(M) receives the access request.

When one access request is accepted,
Information indicating that the request has been accepted is sent to the request source that sent the access request. By receiving one access request, another access request sent to the ring arbiter is waited, and the other access request is detected at the next timing or at the next timing. After the access request is accepted, processing such as transfer of necessary data via the matrix switch means or another bus signal line is executed.

[0006]

In such contention arbitration of access requests, it is good when the number of access request sources and the number of resources are small, but as the number increases, the number of contention arbitrations increases. N is N + ΔN, M is M
By increasing to + ΔM, the scale of the matrix switch is N × M, but becomes (N + ΔN) × (M + ΔM) = NM + ΔNM + NΔM + ΔNΔM. The increase in the size of the matrix switch directly leads to an increase in the contention arbitration operation by the ring arbiter. That is, in FIG. 7, the request source R (0) and the resource S
In order to establish the connection with (7), the ring arbiter must perform contention arbitration at eight intersections. Furthermore, as the size of the matrix switch increases,
The number of intersections that the ring arbiter has to go around increases. In addition, it is necessary to transmit and receive connection availability information for each access request. That is, the operation time becomes long, and expensive elements that can execute high-speed operation must be used.

The present invention is an improvement of the present invention, in which the logic of contention arbitration is changed to reduce the number of request sources or resources of apparent accesses to reduce the number of contention arbitrations to be executed. Aim. SUMMARY OF THE INVENTION It is an object of the present invention to provide a method capable of shortening the contention arbitration time for access request arbitration and performing the contention arbitration with a low-speed and low-power-consumption element.

[0008]

According to the present invention, there are provided N (N is an integer of 2 or more) request sources for generating access requests;
M resources (M is an integer of 2 or more) shared by the access request sources and the N request sources are connected to the input terminal, and the M resources are connected to the output terminal. Matrix switch means having a capacity of N × M, arbitration means for executing arbitration when an access request is issued from a plurality of access request sources for one of the resources, and a result of the arbitration An access arbitration system including a control circuit including a disconnection unit that controls disconnection of an intersection of the matrix switch unit.

Here, a feature of the present invention is characterized in that the arbitration means of the control circuit divides the access request generation source into a plurality of groups smaller than the number (N), and divides the resource into the plurality of groups. Means for dividing into a plurality of groups smaller than the number (M), and a group of intersections connecting each combination of the divided resource group and the group of the access request source, and focused on the group. The present invention includes means for executing the arbitration within the group of intersections, and means for circulating the group of intersections of interest over time with respect to all of the groups of intersections connecting the combinations.

[0010] The arbitration means of the control circuit may be configured to divide the intersection into a group of intersections connecting each combination of the divided resource group and the access request source group. Means for notifying the combination of the group of the access request source and the group of the resource to the group of intersections divided by the dividing means at each access request generation timing,
Means for executing the arbitration within the group of divided intersections for the access request corresponding to the notified combination, output of the group of intersections arbitrated by the means for executing the arbitration, and And a selector switch for connecting all the combinations of the output and the resource in a circulating manner over time. Preferably, the selector switch includes a matrix switch.

The arbitration means of the control circuit may further comprise: means for dividing the intersection into a group of intersections connecting each combination of the divided resource group and the access request source group. Means for informing the intersection group divided by the dividing means of the combination of the group of the access request source and the group of the resources, and the division of the access request corresponding to the notified combination. Means for performing the arbitration within the group of intersections, and a filter circuit for connecting the output of the group of intersections arbitrated by the means for performing the arbitration to the resource and identifying a header of a signal provided to the resource And a configuration including: The filter circuit preferably includes means for selecting an output line of the resource according to an address of a header of the output.

The arbitration means of the control circuit may further comprise: means for dividing the intersection into a group of intersections connecting each combination of the divided resource group and the access request source group. Means for informing the group of access request sources of the combination of the group of access request sources and the group of resources; and the access request for the group of request sources not notified from the notification means. Means for prohibiting the occurrence of the arbitration, means for executing the arbitration within the group of the divided intersections for the access request corresponding to the notified combination, and means for executing the arbitration by the means for executing the arbitration. A selector switch for connecting the output of the group and the resource, wherein the selector switch Cycled over time for all combinations of the serial resource may be configured to include a means for connecting.

[0013]

In order to construct an N × M large-scale one-stage matrix switch, N request sources are divided into d1 groups, and M resources are divided into d2 groups. (N /
d1) × (M / d2) small-scale switches using d1
The small-scale switch is associated with the request source division group, and the small-scale switch performs outgoing contention control and data transfer by associating an arbitrary resource with the small-scale switch. The connection relation with the small-scale switch is circulated so as to take a combination.

This eliminates the need to pass all adjacent intersections in a two-dimensional array during data transfer.

[0015]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The configuration of a first embodiment of the present invention will be described with reference to FIG. FIG. 1 is a configuration diagram of the first embodiment of the present invention.

According to the present invention, eight request sources R (0) to R (7) for generating access requests and eight request sources R (0) to R (7) shared by the access request sources are provided. Resources S (1) to S (7) and eight request sources R (0) to R (R)
(7) is connected to the input terminal ₁ 1 to 1 _8, matrix switch 3 having a capacity of eight resource S (1) to S (7) is connected to the output terminal 2 ₁ to 2 ₈ have been 8 × 8 And arbitration means for executing arbitration when access requests are generated from a plurality of access request sources R (0) to R (7) for one of resources S (1) to S (7). An access arbitration system including an arbitration unit 5 and a control circuit CTL including a matrix switch disconnection unit 6 as disconnection means for controlling disconnection of an intersection of the matrix switch means based on the arbitration result.

Here, a feature of the present invention is that the arbitration means of the arbitration unit 5 includes access request generation sources R (0) to R (0).
Means for dividing R (7) into four groups, means for dividing resources S (1) to S (7) into four groups, and means for dividing the resources S (1) to S (7) And resource request groups IG (0) to IG (3), which are groups of the resource groups OG (0) to OG (3) and the access request sources R (0) to R (7). Means for focusing on switch groups SW (0) to SW (3), which are groups of intersections connecting the combinations one by one, and executing the arbitration in the focused switch groups SW (0) to SW (3); Switch groups SW (0) to SW connecting this group of intersections of interest to the combination
Means for circulating all of (3) over time.

Next, the operation of the first embodiment of the present invention will be described. The request sources R (0) to R (7) are divided into four, and the divided groups are divided into request source groups IG (0) to IG (0), respectively.
IG (3), the resources S (1) to S (7) are divided into four, and the divided groups are each assigned to a resource group OG.
(0) to OG (3).

A small switch having a 2 × 2 intersection and performing competitive control of two inputs and two outputs is referred to as a switch group S.
W (0) to SW (3). In FIG. 1, a switch group indicated by a broken line is a portion including a virtual intersection that does not actually exist, and therefore, no hardware exists. Data lines IL (0) to IL (7) for receiving data and control data from each request source R (0) to R (7) and returning a control result, and a switch group SW
(0) to the input line of SW (3). Data lines OL (0) to OL (7) of resources S (1) to S (7)
Are connected to output lines of arbitrary switch groups SW (0) to SW (3) based on the procedure described below.

In the first embodiment of the present invention, outgoing line contention control and data transfer are performed by an arbitrary request source group IG (0).
IG (3) and arbitrary resource groups OG (0) to OG
(3) Performed only during the period. The types are IG (0) ⇔OG (0), IG (1) ⇔OG (1),
IG (2) ⇔OG (2), IG (3) ⇔OG (3) IG (0) ⇔OG (1), IG (1) ⇔OG (2),
IG (2) ⇔OG (3), IG (3) ⇔OG (0) IG (0) ⇔OG (2), IG (1) ⇔OG (3),
IG (2) ⇔OG (0), IG (3) ⇔OG (1) IG (0) ⇔OG (3), IG (1) ⇔OG (0),
IG (2) ⇔OG (1) and IG (3) ⇔OG (2). Here, the request source group IG (0)
-IG (3) and resource group OG (0) -OG
The combination of (3) is the resource group OG
(0) to OG (3) and switch group SW (0) to S
It is equivalent to a combination with W (3). In the case of the first embodiment of the present invention, by cyclically selecting ~, all of the request source groups IG (0) to IG (3) and all of the resource groups OG (0) to OG (3) are connected. Take a combination. This means that all request source groups R (0)
R (7) issues an output request to all resources S (1) to S (7), and indicates that data can be output by permitting output. This indicates that an 8 × 8 switch (64 intersections) can be constituted by four 2 × 2 small switches (16 intersections) virtually. The tour here is nothing but moving the switch groups SW (0) to SW (3) to the apparent intersection shown by hatching in FIG. 1 as indicated by arrows. The arrow in FIG. 1 shows a case where a transition from the combination to the combination is made.

In the case of the first embodiment of the present invention, the request source R
The number of (0) to R (7) is 8, and the resources S (1) to S (S)
(7) is 8, the number of request sources R (0) to R (7) is 4 and the number of divided request sources is 2;
Although the number of divisions of (1) to S (7) is four and the number of divided resources is two, these numbers are not limited and can be set arbitrarily and independently. For example, the number of divisions of the request sources R (0) to R (7) and the resources S (1) to S (7) need not be equal, and the size of each switch group SW (0) to SW (3) is Optional. There is no restriction on the order of the tour, as long as all the combinations are covered.

Next, a second embodiment of the present invention will be described with reference to FIG. FIG. 2 is a configuration diagram of the second embodiment of the present invention. In the second embodiment of the present invention, the request generation sources R (0) to R (0) to R
(7) is divided into four, the divided groups are referred to as request source groups IG (0) to IG (3), and resources S (1) to
S (7) is divided into four, and the divided groups are referred to as resource groups OG (0) to OG (3). Small-scale switches having 2 × 2 intersections and performing competitive control on two inputs and two outputs are referred to as switch groups SW (0) to SW (3). Selectors SEL (0) and SEL (1) are connected to data line IL.
(0) to IL (7) and data lines OL (1) to OL (7)
Are four-input, four-output selectors that are connected in a one-to-one manner, or are non-block switches that are connected in a fixed cyclic manner in each cell cycle. The control circuit CTL includes the request source group IG
(0) to IG (3) and resource groups OG (0) to O
G (3) is selected and each switch group SW
(0) to SW (3) and selectors SEL (0) and SE
This is a circuit that notifies and controls the combination to L (1). Request generation sources R (0) to R (7) and switch group SW (0)
To SW (3) are data lines IL (0) to IL, respectively.
(7). The data lines IL (0) to IL (7) are data lines that receive data and control data from the request generation sources R (0) to R (7) and return a control result. The data lines OL (1) to OL (7) are
(0), OL (2), OL (4) and OL (6) are connected to the selector SEL (0), and the data lines OL (1) and OL (1) are connected.
(3), OL (5), OL (7) are selectors SEL
Connected to (1). Output lines O (0) to O (7) are output lines O (0), O (2), O (4), and O (6) that output data from selector SEL (0) to resources S (0), S
(2), output to S (4) and S (6), and output line O
(1), O (3), O (5), O (7) are selectors SE
The data output of L (1) is represented by resources S (1), S (3),
Output to S (5) and S (7). Control line CL (0), C
L (1) and the control lines ctl (0) to ctl (3) are connected to the selectors SEL (0) and SEL (1) and the switch groups SW (0) to SW (3), respectively.
(0) to IG (3) and resource groups OG (0) to O
This is a control line for notifying the combination of G (3). In the case of the second embodiment of the present invention, the combinations that can be selected by the control circuit CTL are IG (0) ⇔OG (0), IG (1) ⇔OG (1),
IG (2) ⇔OG (2), IG (3) ⇔OG (3) IG (0) ⇔OG (1), IG (1) ⇔OG (2),
IG (2) ⇔OG (3), IG (3) ⇔OG (0) IG (0) ⇔OG (2), IG (1) ⇔OG (3),
IG (2) ⇔OG (0), IG (3) ⇔OG (1) IG (0) ⇔OG (3), IG (1) ⇔OG (0),
IG (2) ⇔OG (1) and IG (3) ⇔OG (2). By cyclically selecting from, a combination of all request source groups IG (0) to IG (3) and resource groups OG (0) to OG (3) is obtained. This indicates that all request sources R (0) to R (7) can issue output requests to resources S (1) to S (7) and can output data by permitting output.

Now, assuming the present combination, (1) the request sources R (2a) and R (2a + 1) of the request source group IG (a) ｛a = 0, 1, 2,.
3｝ issues an output request to switch group SW (a),
(2) In the switch group SW (a), the resource group OG whose request is notified by ctl (a)
Resource S (2a) and resource S (2a + 1) in (a)
If the request is received, the switch group SW (a) performs outgoing contention control in response to the request. (3) As a result, permission is given to the output request from R (2a) or R (2a + 1). If obtained, the data is transferred to the data line IL (2
a) or through IL (2a + 1) to the switch group SW (a). Switch group SW (a)
Are output to the resource S (2a) based on the control result, and the output to the resource S (2a) passes through the data line OL (2a).
(0), the output to the resource S (2a + 1) passes through the data line OL (2a + 1) and the selector SEL (1)
Selector SE based on the combination of (4)
L (0) connects data line OL (2a) and output line O (2a), and selector SEL (1) connects data line OL (2a + 1) and output line O (2a + 1) to transfer data.
(5) As a result, R (2a) and R (2a) for which output permission has been obtained
+1) is the resource S (2a) and the resource S (2
a + 1), take the combination of
By repeating the procedures (1) to (5), all the request sources R (0) to R (7)
Data output can be performed for (1) to S (7) through outgoing line competition control. This is a virtual 2 × 2 small switch (16 intersections) and an 8 × 8 switch (64
(Intersection) can be constructed.

FIG. 3 is a diagram showing the operating principle of the selectors SEL (0) and SEL (1) used in the second embodiment of the present invention. The data lines OL (0) to OL (6)
The request source includes a switch that outputs line data. Output lines O (0) to O (6) indicate four resource groups. The selector SEL is a four-input four-output selector. The intersection of the selector SEL is X (c, d) ｛c
= 0, 1, 2, 3; d = 0, 1, 2, 3}. The control circuit CTL is a control circuit that forcibly connects and disconnects four inputs and four outputs so as to correspond one-to-one.

Here, the selector SEL is connected to the selector SE.
Taking L (0) as an example, connection and operation will be described. The data line OL is connected to four inputs of the selector SEL.
(0), OL (2), OL (4), OL (6) are connected, and output lines O (0), O (2), O (4),
O (6) is connected. The control circuit CTL closes the intersection of the selector SEL based on the control data given to the small switch in the second embodiment of the present invention. The combinations are X (0,0), X (1,1), X (2,2), X
(3,3) X (0,1), X (1,2), X (2,3), X
(3,0) X (0,2), X (1,3), X (2,0), X
(3,1) X (0,3), X (1,0), X (2,1), X
Select (3, 2). FIG. 3 shows X (0,1), X (1,2), X
The case where (2, 3) and X (3, 0) are selected is shown. The intersection indicated by ● is closed, and the data from each small switch is OL
(0) → O (2), OL (2) → O (4), OL (4)
It is transferred to resources S (0), S (2), S (4) and S (6) via → O (6), OL (6) → O (0). In the case of the selector SEL (1), the data lines OL (1), OL (3), OL (5) and OL (7) are connected to four inputs, and the output lines O (1) and O are connected to four outputs. (3), O
(5), O (7) may be connected. In this case, the number of input lines is four and the number of output lines is four, but these numbers are not limited and can be set arbitrarily according to the scale and the number of divisions of the switch. In the case of the second embodiment of the present invention, the request sources R (0) to R
The number 8 of (7), the number 8 of resources S (1) to S (7), the number of divisions of the request source 4 is 2, the number of division request sources is 2, and the number of divisions of resource 4 is 2 However, these numbers are not limited and can be set arbitrarily and independently. For example, request sources R (0) to R (7) and resources S (1) to S (S)
The number of divisions in (7) does not need to be equal, and the size of each switch group SW (i) may be arbitrary. The selectors SEL (0) and SEL (1) may be any circuit as long as the input and output can be combined in a non-block manner.

A third embodiment of the present invention will be described with reference to FIG. FIG. 4 is a configuration diagram of the third embodiment of the present invention. In the third embodiment of the present invention, the number of request generation sources R (0) to R (7) is 8,
It is assumed that the number of resources S (1) to S (7) is 8. In the third embodiment of the present invention, the request sources R (0) to R (7) are divided into four, and the divided groups are divided into the request source groups IG (0).
To IG (3), the resources S (1) to S (7) are divided into four, and the divided group is referred to as a resource group OG (0).
To OG (3). Switch groups SW (0) to which have 2 × 2 intersections and perform conflict control on two inputs and two outputs
SW (3). Filter circuits AF (0) and AF
(1) is a 4-input / 4-output filter circuit that connects an input line and an output line one-to-one. The control circuit CTL includes the request source groups IG (0) to IG (3) and the resource group O
This is a circuit that selects a combination of G (0) to OG (3) and notifies each switch group SW (0) to SW (3) of the combination to control. Request source group R (0) to R (7)
And switch groups SW (0) to SW (3) are connected by data lines IL (0) to IL (7), respectively. The data lines IL (0) to IL (7) are connected to the request sources R (0) to R (R).
This is a data line that receives data and control data from (7) and returns a control result. Data lines OL (1) to OL
(7) indicates data lines OL (0), OL (2), OL
(4), OL (6) is connected to the filter circuit AF (0), and the data lines OL (1), OL (3), OL (5), O
L (7) is connected to filter circuit AF (1). Output lines O (0) to O (7) are output lines O (0), O (2),
O (4) and O (6) output the data output of the filter circuit AF (0) to the resources S (0), S (2), S (4), S
(6), and output lines O (1), O (3), O
(5), O (7) outputs the data output of the filter circuit AF (1) to resources S (1), S (3), S (5), S (7).
Output to The control lines CL (0), CL (1) and the control lines ctl (0) to ctl (3) are each provided with a filter circuit AF.
(0), AF (1) and switch groups SW (0) to S
W (3) includes request source groups IG (0) to IG
This is a control line for notifying a combination of (3) and resource groups OG (0) to OG (3). In the case of the second embodiment of the present invention, the combinations that can be selected by the CTL are IG (0) ⇔OG (0), IG (1) ⇔OG (1),
IG (2) ⇔OG (2), IG (3) ⇔OG (3) IG (0) ⇔OG (1), IG (1) ⇔OG (2),
IG (2) ⇔OG (3), IG (3) ⇔OG (0) IG (0) ⇔OG (2), IG (1) ⇔OG (3),
IG (2) ⇔OG (0), IG (3) ⇔OG (1) IG (0) ⇔OG (3), IG (1) ⇔OG (0),
IG (2) ⇔OG (1) and IG (3) ⇔OG (2). By cyclically selecting from, a combination of all request source groups IG (0) to IG (3) and resource groups OG (0) to OG (3) is obtained. This indicates that all request sources R (0) to R (7) can issue output requests to resources S (1) to S (7) and can output data by permitting output.

Now, assuming the current combination, (1) the request source R of the request source group IG (a)
(2a) and R (2a + 1) {a = 0, 1, 2, 3}
Issues an output request to switch group SW (a),
(2) In the switch group SW (a), when the request is for the resources S (2a) and S (2a + 1) of the resource group OG (a), the control circuit C
Since it is informed that the output can be performed from the TL, the request is accepted and the outgoing line conflict control is performed in the switch group SW (a). (3) As a result, the request source R (2)
a) or if an output request from R (2a + 1) is granted, data is passed through the data line IL (2a) or IL (2a + 1) to the switch group SW (a).
Is forwarded to The switch group SW (a) outputs data to the switch group S (2a) based on the control result, and the filter group AF (2a) passes through the data line OL (2a).
(0) and output to the resource S (2a + 1) pass through the data line OL (2a + 1) and pass through the filter circuit A
F (1) transferred to (4) filter circuit AF (0)
Is the data line OL (2a) {a = 0, 1, 2, 3}
, The header of the target resource is read internally, and the resource S is output via the output line O (2a).
(0), S (2), S (4), and S (6). The filter circuit AF (1) is connected to the data line OL (2a + 1)
{A = 0, 1, 2, 3} are received and internally targeted resources S (1), S (3), S
(5), the header of S (7) is read, and the output line O (2a
+1) through the resources S (1), S (3), S
(5) Transfer to S (7). (5) As a result, request sources R (2a) and R (2a + 1) that have obtained output permission.
Is output to the resources S (2a) and S (2a + 1). By taking the combination of and repeating the procedures of (1) to (5), all request sources R (0)
To R (7) can output data to all the resources S (1) to S (7) through outgoing contention control. This is because 4 small 2 × 2 small switches (1
It shows that an 8 × 8 switch (64 intersections) can be configured with 6 intersections).

The operation principle of the filter used in the third embodiment of the present invention will be described with reference to FIG. FIG. 5 is a diagram for explaining the operation principle of the filter used in the third embodiment of the present invention. The filter circuit AF is a 4-input 4-output filter shown in FIG. The inside of the filter circuit AF is the intersection X (c,
d) A space switch composed of intersections of {c = 0, 1, 2, 3; d = 0, 1, 2, 3}. Filter F
(C, d) reads the input data, reads the address of the output line written at an arbitrary position, and obtains the intersection X (c, d).
A device for opening and closing d). When the address data matches the output line address, the intersection is closed. Here, the connection and operation will be described taking the filter circuit AF (0) as an example.
The data line OL (0),
OL (2), OL (4) and OL (6) are connected, and output lines O (0), O (2), O (4) and O (6) are connected to four outputs.
Is connected. Data lines OL (0), OL (2), OL
(4) In the third embodiment of the present invention, the data input to the OL (6) is already allocated so that the addresses of the resources S (1) to S (7) do not collide.
The input data is output to the output lines O (0) and O without collision.
(2), O (4), and O (6). In FIG. 5, the addresses of the transferred data are OL (0) → O
(2), OL (2) → O (4), OL (4) → O
(6) shows a case where OL (6) → O (0). Filter circuits F (0,1), F (1,2), F (2,
3), F (3,0) detects a match between the corresponding resource and the address, and intersections X (0,1), X (1,2), X
(2,3), X (3,0) is closed. It goes without saying that other filters do not respond. The intersection indicated by ● is closed, and the data from each small switch is OL (0) → O
(2), OL (2) → O (4), OL (4) → O
(6), transferred to the resource via OL (6) → O (0). Filter circuit AF (1) of the third embodiment of the present invention
In the case of, the data lines OL (1), OL (3),
OL (5) and OL (7) are connected, and output line O is connected to 4 outputs.
(1), O (3), O (5) and O (7) may be connected. In the case of the third embodiment of the present invention, the request sources R (0) to R
The number 8 of (7), the number 8 of resources S (1) to S (7), the number of divisions of the request source 4 is 2, the number of division request sources is 2, and the number of divisions of resource 4 is 2 However, these numbers are not limited and can be set arbitrarily and independently. For example, request sources R (0) to R (7) and resources S (1) to S (S)
The number of divisions in (7) does not need to be equal, and the size of each switch group SW (i) may be arbitrary.

Next, a fourth embodiment of the present invention will be described with reference to FIG. FIG. 6 is a configuration diagram of the fourth embodiment of the present invention. In the fourth embodiment of the present invention, the number of request sources R (0) to R (7) is 8, and the number of resources S (1) to S (7) is 8. In the fourth embodiment of the present invention, the request sources R (0) to R (7) are
Divide and divide the divided group into request source group IG
(0) to IG (3), and resources S (1) to S (7)
Is divided into four, and the divided group is assigned to the resource group OG.
(0) to OG (3). Switch group SW having 2 × 2 intersections and performing conflict control on two inputs and two outputs
(0) to SW (3). Selectors SEL (0) and S
EL (1) is a 4-input / 4-output selector for connecting the input line and the output line in a one-to-one manner, or a non-blocking switch for fixedly and cyclically connecting every cell cycle. The switch groups SW (0) to SW (3) are all the switch groups SW (0) to SW (3) which perform output line contention control by determining an output request related to the selector SEL (0) or SEL (1).
(3) has a common function. The control circuit CTL selects a combination of the request source groups IG (0) to IG (3) and the resource groups OG (0) to OG (3) and selects each of the request source groups IG (0) to IG (3). Selector SEL
This is a circuit that notifies and controls the combination of (0) and SEL (1). The request generation sources R (0) to R (7) and the switch groups SW (0) to SW (3) are respectively connected to the data lines IL.
(0) to IL (7). Data line IL (0)
ＩＬIL (7) are data lines that receive data and control data from the request sources R (0) to R (7) and return control results. Data lines OL (1) to OL (7) are data lines OL (0), OL (2), OL (4), OL (6).
Is connected to the selector SEL (0), and the data line OL
(1), OL (3), OL (5), OL (7) are connected to the selector SEL (1). Output lines O (0) to O
(7) indicates output lines O (0), O (2), O (4), O
(6) outputs the data output of the selector SEL (0) to the resources S (0), S (2), S (4), S (6), and the output lines O (1), O (3), O (5), O (7) outputs the data output of selector SEL (1) to resources S (1), S
(3), output to S (5) and S (7). Control line CL
(0), CL (1), and control lines ctl (0) to ctl
(3) respectively correspond to the selectors SEL (0) and SEL (1) and the request source groups IG (0) to IG (3), the request source groups IG (0) to IG (3) and the resource group OG (0). ) To OG (3). In the case of the fourth embodiment of the present invention, the combinations that can be selected by the control circuit CTL are IG (0) ⇔OG (0), IG (1) ⇔OG (1),
IG (2) ⇔OG (2), IG (3) ⇔OG (3) IG (0) ⇔OG (1), IG (1) ⇔OG (2),
IG (2) ⇔OG (3), IG (3) ⇔OG (0) IG (0) ⇔OG (2), IG (1) ⇔OG (3),
IG (2) ⇔OG (0), IG (3) ⇔OG (1) IG (0) ⇔OG (3), IG (1) ⇔OG (0),
IG (2) ⇔OG (1) and IG (3) ⇔OG (2). By cyclically selecting from, a combination of all request source groups IG (0) to IG (3) and resource groups OG (0) to OG (3) is obtained. This indicates that all request sources R (0) to R (7) can issue output requests to resources S (1) to S (7) and can output data by permitting output.

Now, description will be made assuming the current combination. (1) Request source R of request source group IG (a)
(2a) and R (2a + 1) {a = 0, 1, 2, 3}
Is notified that only requests to the resource group OG (a) can be output. Then, switch group SW
(A) Output request is issued. (2) Switch group SW
In (a), the requests are connected to the selector SEL.
(0) or SEL (1) is determined, and outgoing line conflict control is performed. (3) As a result, the request source R (2a)
Or, when permission is obtained for the output request from R (2a + 1), the data is transferred to the data line IL (2a) or IL (2a + 1).
The data is transferred to the switch group SW (a) through (2a + 1). The switch group SW (a) that outputs to the resource S (2a) based on the control result is transferred to the selector SEL (0) through the data line OL (2a) and output to the resource S (2a + 1) Is transferred to the selector SEL (1) through the data line OL (2a + 1). Based on the combination of (4), the selector SEL
(0) is the data line OL (2a) and the output line O (2a)
And the selector SEL (1) is connected to the data line OL (2a
+1) and the output line O (2a + 1) are connected to transfer the data. (5) As a result, the data of the request sources R (2a) and R (2a + 1) for which output permission has been obtained are stored in the resource S
By taking the combination of (2a) and S (2a + 1), and repeating the procedures of (1) to (5), all request sources R (0) to R (7) Data can be output to the resources S (1) to S (7) through outgoing line conflict control. This is virtually 2x
It shows that an 8 × 8 switch (64 intersections) can be constituted by four small switches (16 intersections). At this time, S
EL can be similarly performed using the selector described in the second embodiment of the present invention.

In the case of the fourth embodiment of the present invention, the request source R
(8) of (0) to R (7), resources S (1) to S (7)
, The number of request generation sources is divided into four, and the number of division request generation sources is divided into two, and the number of resource divisions is divided into four, thereby dividing the number of resources into two.
For example, request sources R (0) to R (7) and resource S
The number of divisions of (1) to S (7) does not need to be equal, and the size of each switch group SW (i) may be arbitrary.
The selectors SEL (0) and SEL (1) may be any circuit as long as the input and output can be combined in a non-block manner.
Further, the same can be realized by replacing the selectors SEL (0) and SEL (1) with a filter configuration as in the third embodiment of the present invention. In this case, it goes without saying that the control lines CL (0) and CL (1) are not required.

[0032]

As described above, according to the present invention, the number of contention arbitrations to be executed can be reduced by changing the logic of contention arbitration and apparently reducing the number of access request sources or the number of resources. . According to the present invention, the contention arbitration time for access request arbitration can be shortened, and the contention arbitration can be performed by a low-speed and low-power-consumption element.

[Brief description of the drawings]

FIG. 1 is a configuration diagram of a first embodiment of the present invention.

FIG. 2 is a configuration diagram of a second embodiment of the present invention.

FIG. 3 is a configuration diagram of a selector according to a second embodiment of the present invention.

FIG. 4 is a configuration diagram of a third embodiment of the present invention.

FIG. 5 is a configuration diagram of a filter circuit according to a third embodiment of the present invention.

FIG. 6 is a configuration diagram of a fourth embodiment of the present invention.

FIG. 7 is a configuration diagram of a conventional example.

[Explanation of symbols]

3 Matrix switch 5 Arbitration unit 6 Matrix switch disconnection unit AF filter circuit CL (0), CL (1), ctl (0), ctl
(1), ctl (2), ctl (3) Control line CTL control circuit F filter IG (0) to IG (3) Request generation source group O (0) to O (7) Output line OG (0) to OG (3) Resource group OL (1) to OL (7), IL (0) to IL (7) Data line R (0) to R (7) Request generation source RA (1) to RA (8) Ring arbiter S (1) to S (7) Resource SEL selector SW (0) to SW (3) Switch group X, C intersection

────────────────────────────────────────────────── ─── Continuation of the front page (56) References JP-A-3-154544 (JP, A) JP-A-6-90232 (JP, A) JP-A-6-90233 (JP, A) JP-A-6-90233 90242 (JP, A) JP-A-6-90243 (JP, A) U.S. Pat. No. 3,226,688 (US, A) (58) Fields investigated (Int. Cl. ⁷ , DB name) H04L 12/28

Claims (6)

(57) [Claims] 1. N (N is an integer of 2 or more) request sources that generate access requests, M (M is an integer of 2 or more) resources shared by the request sources of the access, Matrix switch means having an N × M capacity in which the N request sources are connected to an input terminal and the M resources are connected to an output terminal; and the access request source for one of the resources. Arbitration means for executing arbitration when an access request is issued from a plurality of the control means, and a control circuit including disconnection means for controlling disconnection of an intersection of the matrix switch means based on the arbitration result. In the arbitration method, the arbitration means of the control circuit includes: means for dividing the access request source into a plurality of groups smaller than the number (N); and dividing the resources by the number (M). Means for dividing into a plurality of small groups, and focusing on a group of intersections connecting each combination of the divided resource group and the group of the access request source, and within the focused intersection group An access arbitration method comprising: means for executing the arbitration; and means for circulating the group of intersections of interest with respect to all of the groups of intersections connecting the combinations over time. 2. The access arbitration method according to claim 1, wherein the arbitration means of the control circuit is configured to combine each of the resource group divided at the intersection and the access request source group. Means for dividing into groups of intersections to be connected; means for notifying the group of intersections divided by the means for dividing the combination of the group of the source of the access request and the group of the resource for each access request generation timing Means for executing the arbitration within the divided group of intersections for the access request corresponding to the notified combination; output of the group of intersections arbitrated by the means for executing the arbitration; And a selector switch for connecting the output and the resource. An access arbitration system comprising means for circulating and connecting all of the sets over time. 3. The access arbitration system according to claim 2, wherein said selector switch includes a matrix switch. 4. The access arbitration method according to claim 1, wherein the arbitration means of the control circuit combines one of each of the group of the resources divided at the intersection and the group of the access request source. Means for dividing into groups of connecting intersections; means for informing the groups of intersections divided by the dividing means of a combination of the group of the access request source and the group of resources; and the notified combination Means for executing the arbitration within the group of the divided intersections for the access request corresponding to, and connecting the output of the group of the intersections arbitrated by the means for executing the arbitration to the resource, and connecting to the resource An access arbitration system comprising: a filter circuit for identifying a header of a given signal. 5. The access arbitration method according to claim 4, wherein said filter circuit includes means for selecting an output line of said resource according to an address of a header of said output. 6. The access arbitration method according to claim 1, wherein the arbitration unit of the control circuit combines one of each of the resource group divided at the intersection and the access request source group. Means for dividing into groups of intersections to be connected; means for notifying the group of request sources of access to a combination of the group of request source of access and the group of resources; and notification from the means for notifying. Means for prohibiting the generation of the access request for a group of request sources that do not exist, means for executing the arbitration within the group of the divided intersections for the access request corresponding to the notified combination, and executing the arbitration And a selector switch for connecting the resource to the output of the group of intersections arbitrated. The access arbitration system, wherein the selector switch includes means for circulating and connecting all combinations of the output and the resource over time.