JPH0685551U - Timing extraction circuit - Google Patents

Abstract

(57) [Abstract] [Purpose] A pulse signal train having a timing frequency component is generated from a received data signal which is an NRZ code, a stable clock signal is extracted, and integration is possible without using a fixed delay line. (EN) Provided is a timing extraction circuit which can realize an IC. [Composition] In the timing extraction circuit, the phase difference is electrically and automatically controlled by using an integrating circuit and the like, which eliminates the need for adjusting the pulse width while changing the fixed delay line, and the transmission speed of the received data signal. It is possible to generate a stable edge pulse signal irrespective of the transmission speed even if the value changes.

Description

[Detailed description of the device]

[0001]

[Industrial applications]

 The present invention relates to a timing extraction circuit for reproducing a clock signal from a received signal, which circuit is provided in a receiver for digital transmission.

[0002]

[Prior art]

 The prior art is shown in FIG. Since an NRZ code does not have a timing frequency component, in order to generate an edge pulse signal train from a received signal which is an NRZ code, a logical circuit such as an exclusive OR (hereinafter, EX-OR logic circuit) circuit 8 is used. , It is possible to generate an edge pulse signal train having a timing frequency component by creating a phase difference between the two input signals of the EX-OR logic circuit 8.

In the prior art, a method of providing a phase difference between two input signals of the EX-OR logic circuit 8 is to insert a fixed delay line 7 in front of one input of the EX-OR logic circuit 8. There is. By passing the output of the EX-OR logic circuit 8 through the narrow band filter 9, a sine wave having a timing frequency component can be obtained. This sine wave is amplified and shaped by the limit amplification circuit 10 to be a clock signal.

When the phase difference between the two input signals of the EX-OR logic circuit 8 is 90 °, the amplitude value of the sine wave output from the narrow band filter 9 can be maximized.

[0005]

[Problems to be solved by the device]

 In FIG. 3 showing the conventional technique, it is desired to set the phase difference between the two input signals of the EX-OR logic circuit 8 to an optimum value. For that purpose, it is necessary to determine the delay time of the fixed delay line 7 in consideration of the line length to the input terminal of the EX-OR logic circuit 8. The delay time of the fixed delay line 7 is changed, the output amplitude of the narrow band filter 9 is measured, and the fixed value extension line 7 that becomes the delay time when the amplitude reaches the maximum value is determined.

The conventional technique has a drawback in that a troublesome adjusting method of forming a circuit using the fixed delay line 7 determined by the above-described method is applied. Further, if the transmission speed of the received data signal changes, it is necessary to adjust the delay time of the fixed delay line 7 according to the change.

[0007] Furthermore, the fixed delay line 7-wave coil, the capacitor or the like, or the strip line is used, and there is a drawback that it is difficult to form an integrated circuit.

An object of the present invention is to generate a pulse signal train having a timing frequency component from a received data signal which is an NRZ code, extract a stable clock signal, and enable integration without using a fixed delay line. It is to provide a timing extraction circuit that can be integrated into an IC.

[0009]

[Means for Solving the Problems]

 The feature of the present invention is that the timing extraction circuit does not need to adjust the pulse width while changing the fixed delay line by automatically controlling the phase difference electrically by using an integrating circuit. is there. Moreover, even if the transmission rate of the received data signal changes, it is possible to generate a stable edge pulse signal regardless of the transmission rate.

[0010]

[Action]

 By eliminating the need for a fixed delay line that is difficult to integrate with respect to the timing extraction circuit, it is possible to realize the IC of the timing extraction circuit.

[0011]

【Example】

 FIG. 1 shows an embodiment of the present invention. Fig. 2 shows a time chart of the output waveform at each point in Fig. 1.

In FIG. 1, the waveform of the received NRZ code data signal at the point A, which is the output of the integrating circuit 1, is a triangular wave by the integrating circuit 1. The threshold value 6a of the comparison circuit 3a is given by the constant voltage source 2a. The output signal waveform at the point B is obtained by the comparison by the comparison circuit 3a. Further, similarly, the comparison circuit 3b threshold 6b is given by the constant voltage source 2b, and the comparison circuit 3b makes a comparison, and the compared output signal waveform at the point C is obtained.

By performing the above operation, the output signals at the points B and C are input to the logical sum (hereinafter, referred to as OR logic circuit) circuit 4. By taking the logical sum by the OR logic circuit 4, the output signal X becomes an edge pulse signal train having a timing frequency component. The timing frequency component can be extracted by outputting the edge pulse signal train, which is the output signal X of the OR logic circuit 4, to the input terminal 5 of the narrow band filter 9. Further, a clock signal can be obtained by outputting to the limit amplification circuit 10.

(Other Embodiments) In FIG. 1, the OR logic circuit 4 may be replaced with an EX-OR logic circuit 8.

FIG. 4 shows another embodiment of the present invention. FIG. 5 shows a time chart of the output waveform at each point in FIG.

In FIG. 4, the output signal of the integrating circuit 1 is input to the differential output amplifying circuit 11, and the positive phase output and the negative phase output are sent to the two comparing circuits 3a and 3b, respectively. By doing so, the number of constant voltage sources 2 for setting the threshold value 6 of the comparison circuits 3a and 3b can be reduced to one.

[0017]

[Effect of device]

 From the above explanation, to show the effect of the present invention, since the pulse width can be adjusted by changing the threshold value of the comparison circuit, the fixed delay line is adjusted in adjusting the signal input to the logic circuit. Manual replacement eliminates the need for phase adjustment.

Furthermore, since it is possible to generate a stable edge pulse signal regardless of the transmission rate of the received data signal, it is possible to eliminate unnecessary adjustment even if the transmission rate changes.

Since the fixed delay line, which is difficult to be integrated into a circuit, is not required, it becomes easy to realize the timing extraction circuit as an IC.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention.

FIG. 2 is a time chart diagram of output waveforms at respective points in FIG.

FIG. 3 is a diagram showing a conventional technique for extracting a clock signal.

FIG. 4 is a block diagram showing another embodiment of the present invention.

5 is a time chart diagram of output waveforms at respective points in FIG.

[Explanation of symbols]

 1 integrator circuit 2, 2a, 2b constant voltage source 3a, 3b comparison circuit 4 logical sum circuit 5 narrow band filter input terminal 6a, 6b threshold by constant voltage source 7 fixed delay line 8 exclusive OR circuit 9 narrow band filter 10 Limit amplification circuit 11 Differential output amplification circuit

Claims (2)

[Scope of utility model registration request] 1. A timing extraction circuit for extracting a clock signal from a received data signal, the circuit comprising an integration circuit, a constant voltage source, a comparison circuit, and a logic circuit for ORing output signals of two comparison circuits. A timing extraction circuit characterized by the above. 2. The timing extraction circuit according to claim 1, wherein an edge pulse signal train is generated from the received data signal.