JPS643372B2 - - Google Patents

Description

[Detailed description of the invention]

The present invention relates to a timing extraction circuit used in a pulse amplitude modulation (PAM) signal receiver. Generally, when receiving an L-level PAM signal having L discrete amplitude values, it is necessary to sample the received signal at a correct timing to determine the amplitude level at the timing. In this case, a timing signal is required to determine the correct sample position. The timing signal is usually obtained by a self-timing method that is extracted in some way from the received signal itself. One of the conventional self-timing methods is the nonlinear extraction method. this is,
Timing is extracted by utilizing the property that when a received PAM signal is subjected to a nonlinear operation such as a squaring operation, an emission line spectrum is generated at the clock frequency position. Therefore, a nonlinear circuit that performs nonlinear operation is required, and a bandpass filter for passing the bright line spectrum generated at the clock frequency position and an amplitude limiting circuit for eliminating level fluctuations in the bright line spectrum are also required. Therefore, there is a drawback that the circuit is complicated. Further, the above-mentioned nonlinear circuit, amplitude limiting circuit, etc. tend to malfunction in a high frequency region. Therefore, there is a drawback that unnecessary phase noise is likely to be mixed into the extracted timing signal. Another conventional self-timing method is the maximum likelihood detection method. This method differentiates the received PAM signal and controls the timing signal generation circuit so that the timing position is at the zero crossing point of the differentiated waveform. This method does not require the nonlinear circuit described above, and since a voltage-controlled oscillator is usually used in the timing signal generation section, a timing signal with a constant amplitude is always obtained, and the unnecessary It has the characteristic that no phase noise is mixed in. However, since a differential circuit and a sample hold circuit for holding sample values of the differential waveform (or polarity signals of the sample values) are required, there is a drawback that the circuit scale is large and complicated. moreover,
Since the sample value of the differential waveform is sensitive to waveform fluctuations of the received waveform, it is necessary to minimize waveform deterioration in the transmission path. That is, it has the disadvantage of requiring an expensive transmission line. SUMMARY OF THE INVENTION An object of the present invention is to provide a timing extraction circuit which solves the above-mentioned drawbacks of the conventional self-timing method, operates stably even in the face of deterioration of a received waveform, and has a significantly small circuit scale. The timing extraction circuit of the present invention includes a delay difference circuit that outputs a difference between a received signal and a signal delayed by one clock, and a delay difference circuit that outputs a difference between a received signal and a signal delayed by one clock, and a timing extraction circuit in a receiving section of a pulse amplitude modulation signal. a voltage controlled oscillation circuit that generates a timing signal with a controlled frequency; a polarity determination circuit that determines the polarity of a difference between a received signal and a predetermined threshold based on the timing signal output from the voltage controlled oscillation circuit; It has a gate circuit that outputs the output signal of the delay difference circuit as it is or with its polarity inverted according to the output signal of the determination circuit, and a filter that smoothes the output of the gate circuit, and controls the voltage based on the output of the filter. It is characterized by controlling the oscillation frequency of the oscillation circuit. Next, the present invention will be explained in detail with reference to the drawings. FIG. 1 is a block diagram showing one embodiment of the present invention. In other words, the reception input from input terminal 1
The PAM signal y(t) is input to the delay difference circuit 2 and the polarity determination circuit 3. The delay difference circuit 2 is a circuit that calculates the difference between the input signal y(t) and the previous input signal y(t-T) by one clock T and outputs a difference signal. It is composed of circuits. The polarity determination circuit 3 determines the polarity of the difference between the input signal y(t) and a predetermined threshold value based on the timing signal output from the voltage controlled oscillation circuit 6. That is, when the received signal y(t) is greater than the threshold at the sampling time, “+
1", and when the received signal does not meet the threshold value, it outputs "-1". When the output signal of the polarity determination circuit 3 is "+1", the gate circuit 4 outputs the signal of the delay difference circuit 2. The output difference signal is input as is to the loop filter 5, and when the output signal of the polarity determination circuit 3 is "-1", the polarity of the difference signal is inverted and input to the loop filter 5. For example, an amplifier with a gain of 1 The output of the gate circuit 4 may be configured to be switched and connected to the inverting circuit according to the output of the polarity determination circuit 3. Alternatively, the configuration may be configured using a connection similar to that of a ring modulator. The signal is smoothed by the loop filter 5 and supplied as a control voltage to the voltage controlled oscillation circuit 6. The voltage controlled oscillation circuit 6 generates a timing signal whose oscillation frequency is controlled by the control voltage. The polarity determination timing of the polarity determination circuit 3 is obtained by the timing signal.Next, the principle of the present invention will be explained by an example of the operation of this embodiment with reference to FIGS. 1 and 2.Received PAM signal y(t) can be expressed as y(t)= _∞ 〓 ^k=-∞ a _k g(t-kT)...(1) However, g(t) is a unit received waveform, and {a〓 } is generally a multilevel code sequence of 0,
A certain value is taken among L levels of 1, 2, . . . , L-1. For simplicity, if {a} is a binary series of 1 and 0, the received signal y(t) will have a waveform as shown in FIG. 2a. Next, the output of the delay difference circuit 2, that is, the one-clock delay difference signal x(t), is _expressed ^as 〓 _-1 )g(t-kT)...(2) Delayed difference signal x(t) for FIG. 2a
has a waveform as shown in FIG. 2b. Now consider the case where the timing signal output from the voltage controlled oscillator circuit 6 is generated with a deviation of Δt from the correct timing position, as shown in FIG. 2c.
The output signal d(t) of the polarity determining circuit 3 obtained by determining whether the received signal y(t) is positive or negative with respect to the threshold value (L-1)/2 at the above timing is as follows in the range where Δt is small: It can be expressed as d(t)= _∞ 〓 ^k=-∞ b〓u(t-kT-Δt)...(3). However, b〓 is [a〓−(L−
1)/2] is positive, it takes a value of +1, and [a〓
-(L-1)/2] is a binary series that takes a value of -1 when it is negative, and u(t) is a rectangular wave that is 1 when 0≦t≦T and 0 otherwise. Figure 2a
With respect to the received signal shown in FIG. 2, the output signal d(t) whose polarity is determined by the timing signal shown in FIG. 2c becomes as shown in FIG. 2d. Further, as shown in FIG. 2 c', when polarity is determined using a timing signal that is advanced by Δt' from the correct timing position, the determined output signal is as shown in FIG. 2 d'. Next, the output ^signal z(t) _{of the} gate circuit 4 is ^as _follows . (4) For example, the judgment output signal d(t) shown in Fig. 2d
In this case, the output signal z(t) of the gate circuit 4 becomes as shown in FIG. 2 e, and depending on the judgment output signal d' shown in FIG. An output signal like this is obtained. As can be understood from these figures, the average value in the case of Figure 2e is negative, and the average value in the case of Figure 2e is negative.
Since the average value in the case of Figure e' is positive, by controlling the oscillation frequency of the voltage controlled oscillation circuit 6 using the output of the loop filter 5, a timing signal with a small deviation Δt from the correct timing position can be obtained. I can do it. The average value ( ) of the above signal z( _t ) is () = 〓 ⁿ 〓 ^m ( _o − _o-1 ) b _n g (t- nT) u(t-mT-Δt) = 〓 ⁿ 〓 〓 ^m [ _{o o} δ _{on o}・_n (1−δ _o , _n ) − _{o-1 o-1} δ
_o-1,n − _{o-1 n} (1−δ _o-1,n )] ×g(t−nT)u(t−mT−Δt) …(5) Here, δ _o,n is the Kuronetsuka delta (that is, δ _o,n =1 when n=m, δ _o,n =0 otherwise). In equation (5), a _o b _o and _o・_n
do not depend on the subscripts n and m, respectively, so these can be written as
When expressed as ab and, equation (5) can be transformed as follows. ()=(-) 〓 〓 ⁿ g(t-nT)×[u(t-nT-Δt)u(t-nT+T-
Δt)]...(6) D(Δt) using the DC component of z(t) as a function of Δt
Then, D(Δt) is given by equation (6), It is expressed as Here G(ω) and U(ω) are the Fourier transforms of g(t) and u(t), respectively, and U ^* (ω) is the complex conjugate of U(ω). the above
Equation (7) can be further transformed as follows. Here, since g(t) and u(t+T/2) are real functions that are almost even symmetric with respect to t=0, G(ω) and

It is understood that each of the equations is a real function with even symmetry with respect to ω=0. Therefore, the first term of the compound integral function in equation (8), that is, is an odd function with respect to ω, and this integral becomes 0. Therefore, equation (8) can be further simplified as becomes. Furthermore, it is clear from equation (9) that D(Δt)=−D(−Δt), that is, D(Δt) is an odd function with respect to Δt.
Therefore, for example, by controlling the output frequency of the voltage controlled oscillator using the control signal D, increasing the oscillation frequency when Δt is positive, and decreasing the oscillation frequency when Δt is negative, it is possible to always maintain the correct timing position. The timing signal shown can be extracted. Also, the unit waveform g(t) is usually on the high frequency side (ωT is
Because it is susceptible to distortion in the frequency range (close to 2π),
G(ω) deviates from the ideal state accordingly.
However, as can be understood from equation (9), the frequency components near ωT = 2π are suppressed by sinωT/2, so the value of D is less affected by the distortion of g(t). be. In other words, a correct timing signal can be extracted even when the transmission characteristics of the transmission path are poor. As described above, in the present invention, the polarity of the one-clock delay difference signal of the received signal can be changed to positive or
Since the frequency of the timing signal is controlled by smoothing the inverted signal, there is an effect that it is not easily affected by deterioration of the received waveform.
That is, it can be used even when transmission characteristics are poor. It goes without saying that even better results can be obtained by inputting a signal in which the distortion received in the transmission line has been equalized, for example, by an equalizing amplifier. Note that the configuration of the present invention is simple and the circuit scale is small. Further, the delay differential circuit can be easily constructed using a normal differential amplifier, and a commercially available analog multiplexer or the like can be used as the gate circuit. They also have the advantage of being able to operate stably up to high frequencies. For example, it is suitable for PCM repeaters that require low power consumption, and the practical effect is extremely large.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing one embodiment of the present invention, and FIG. 2 is a waveform diagram showing an example of signals in each main part for explaining the operation of the above embodiment. In the figure, 2... delay difference circuit, 3... polarity determination circuit, 4... gate circuit, 5... loop filter, 6... voltage controlled oscillation circuit.

Claims (1)

[Claims] 1 In the timing extraction circuit in the receiving section of the pulse amplitude modulation signal, the received signal and the received signal are
A delay difference circuit outputs the difference between the clock and the clock-delayed signal; a voltage-controlled oscillation circuit generates a timing signal whose oscillation frequency is controlled by a control voltage; and a timing signal output from the voltage-controlled oscillation circuit a polarity determination circuit that determines the polarity of the difference between the signal and a predetermined threshold; and a gate circuit that outputs the output signal of the delay difference circuit as is or with the polarity inverted according to the output signal of the polarity determination circuit; A timing extraction circuit comprising: a filter for smoothing the output of the gate circuit; and controlling the oscillation frequency of the voltage controlled oscillation circuit by the output of the filter.