JPH0685050A - Formation of element isolation insulating film - Google Patents

Abstract

PURPOSE:To prevent the upper end of insulating film buried in the groove of element isolating area from being lower than the silicon substrate of element area. CONSTITUTION:After a thin silicon oxide film 4 is formed on a silicon substrate, a polisilicon 5 and a silicon oxide film 6 are sequentially deposited. Then after etching the silicon oxide film 6 using a resists 7 as a mask, the resist 7 is removed. Then, with the silicon oxide film 6 as a mask, a polisilicon 5, the silicon oxide film 4 and the surface of the silicon substrate 1 are etched through an RIE method so that a groove 9 which is going to be an element isolating area is formed. Further, a silicon oxide film 8 is deposited before etching back, for the surface of polisilicon 5 to be exposed. Then, the polisilicon 5 and the silicon oxide film 4 are etched.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming an element isolation insulating film for a semiconductor integrated circuit.

[0002]

2. Description of the Related Art An element isolation insulating film for an IC (semiconductor integrated circuit) is generally formed by a LOCOS (selective oxidation) method.

A conventional method for forming an element isolation insulating film will be described with reference to the plan view of FIG. 2A and the sectional view taken along the line AB of FIG. 2B.

A thick element isolation oxide film 3 is formed on the P-type silicon substrate 1a via an N-type channel stopper 2 by the LOCOS method. Further, a gate oxide film 4a is formed so as to bridge the element isolation oxide film 3 across the element region, and a gate electrode 5a made of a polysilicon film is formed thereon.
Are formed.

Element isolation by the LOCOS method has the following drawbacks. The element size (width) becomes smaller than the mask size by the amount of the bird's beak 10. When the element width becomes narrow, the effective channel width becomes narrow due to impurity diffusion from the channel stopper 2 (narrow channel effect).

Next, an element isolation method for solving the bird's beak and the narrow channel effect will be described with reference to the sectional views of FIGS. 3 (a) to 3 (c).

First, as shown in FIG. 3A, after the silicon oxide film 4 is formed on the silicon substrate 1, the silicon oxide film 4 in the element isolation region is etched. Next, the silicon substrate 1 is etched using the silicon oxide film 4 as a mask to form a groove 9.

Next, as shown in FIG. 3B, a silicon oxide film 8 is deposited to fill the groove 9.

Next, as shown in FIG. 3C, the silicon oxide 8 and the silicon oxide film 4 are etched back.

[0010]

By embedding the insulating film and then etching back, the bird's beak and the narrow channel effect can be prevented. However, FIG.
As shown in (c), since the silicon oxide film 4 is etched back so as not to remain in the element region, the upper end of the insulating film 8 embedded in the groove becomes lower than the surface of the silicon substrate 1 in the element region. Therefore, a MOSFET with a small channel width
When a voltage is applied to the gate electrode of, the electric field is concentrated at the element region end 11 shown in FIG. 3C, and the threshold voltage of the MOSFET becomes low.

An object of the present invention is to provide a method of filling a groove with an insulating film so as not to be lower than the surface of a silicon substrate.

[0012]

A method of forming an element isolation insulating film according to the present invention comprises a step of sequentially forming a first insulating film, a polysilicon film and a second insulating film on one main surface of a silicon substrate. A step of etching the second insulating film, the polysilicon film, and the first insulating film in a device isolation region, and etching the surface of the silicon substrate using the second insulating film as a mask to form a groove. And a step of depositing a third insulating film on the entire surface to fill the groove, and then etching back until the surface of the polysilicon film is exposed, and etching the polysilicon film and the first insulating film. And the step of performing.

[0013]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described with reference to FIGS.
This will be described with reference to (e).

First, as shown in FIG. 1A, a thin silicon oxide film 4 is formed on a silicon substrate 1. Next, the polysilicon 5 and the silicon oxide film 6 are formed by the CVD method.
After being sequentially deposited, a resist 7 covering the element region is formed.

Next, as shown in FIG. 1 (b), RIE
After the silicon oxide film 6 is etched by the (reactive ion etching) method using the resist 7 as a mask, the resist 7 is removed. Next, the surface of the polysilicon 5, the silicon oxide film 4 and the silicon substrate 1 is etched by the RIE method using the silicon oxide film 6 as a mask to form a groove 9.

Next, as shown in FIG. 1C, a silicon oxide film 8 is deposited by the CVD method.

Next, as shown in FIG. 1D, the silicon oxide film 8 and the silicon oxide film 6 are etched back,
The surface of the polysilicon 5 is exposed. Here, by using the polysilicon 5 as an end point monitor based on the emission spectrum at the time of etching, the silicon oxide film 8 can be left only inside the trench 9.

Next, as shown in FIG. 1E, by etching the polysilicon 5 and the silicon oxide film 4, the upper end of the silicon oxide film 8 embedded in the groove 9 is the surface of the silicon substrate 1 in the element region. It can be prevented from becoming lower.

An insulating film such as a silicon nitride film can be used instead of the silicon oxide film 8 of this embodiment. Further, the silicon oxide films 4, 6 and the polysilicon 5 can be changed to other films having different materials capable of being selectively etched with each other.

[0020]

The upper end of the silicon oxide film embedded in the groove on the surface of the silicon substrate can be suppressed from being lower than the surface of the silicon substrate in the element region. As a result, it has been possible to solve the problem that the threshold voltage is lowered even if a MOSFET having a narrow channel width is formed.

[Brief description of drawings]

FIG. 1 is a sectional view showing an embodiment of the present invention in the order of steps.

FIG. 2A is a plan view showing an element isolation oxide film formed by a LOCOS method. (B) is a sectional view showing an element isolation oxide film by the LOCOS method.

FIG. 3 is a cross-sectional view showing a method of forming an element isolation region using a conventional buried oxide film.

[Explanation of symbols]

 1 Silicon Substrate 1a P-type Silicon Substrate 2 N-type Channel Stopper 3 Element Isolation Oxide Film 4 Thin Silicon Oxide Film 4a Gate Oxide Film 5 Polysilicon 5a Gate Electrode 6 Silicon Oxide Film 7 Resist 8 Silicon Oxide Film 9 Groove 10 Bird's Beak 11 Device Area end

Claims (1)

[Claims] 1. A step of sequentially forming a first insulating film, a polysilicon film, and a second insulating film on one main surface of a silicon substrate, and a step of forming the second insulating film and the polysilicon in a device isolation scheduled region. Etching the film and the first insulating film, etching the surface of the silicon substrate with the second insulating film as a mask to form a groove, and depositing a third insulating film on the entire surface to form the groove. A method for forming an element isolation insulating film, comprising: a step of etching back until the surface of the polysilicon film is exposed after filling the groove; and a step of etching the polysilicon film and the first insulating film.