JPH0684953A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To make characteristics of a MISFET uniform by eliminating irregularities in mutual positional relationship between a gate electrode and source, drain electrodes. CONSTITUTION:A gate pattern 2a, a source pattern 2b and a drain pattern 2c are simultaneously opened in a photoresist film 2 formed on a semiconductor substrate 1. An entire surface is covered with an insulating film 3 to cover the entire patterns 2a, 2b, 2c. The film 3 covering the pattern 2a is removed to form a gate electrode 6, the film 3 covering the patterns 2b, 2c is removed to form a source electrode 7b and a drain electrode 7c.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device. Specifically, the present invention relates to a method for manufacturing a field effect semiconductor device such as MESFET or HEMT.

[0002]

2. Description of the Related Art In a conventional MESFET manufacturing method, the gate electrode (Schottky electrode) and the source / drain electrode (ohmic electrode) have different electrode materials, so that the gate electrode and the source / drain electrode are formed in different steps. It is formed by.

That is, in the step of forming the source / drain electrodes, the source / drain pattern is opened in the photoresist film separately formed by using another photomask for forming the source / drain electrodes, and the ohmic electrode material is formed. Evaporate the source and source in the drain pattern
A drain electrode is formed.

In the step of forming the gate electrode, a photomask for forming the gate electrode is aligned and superposed on the photoresist film formed on the semiconductor substrate, exposed and developed to form a gate pattern on the photoresist film. And a Schottky electrode material is vapor-deposited to form a gate electrode in the gate pattern.

[0005]

However, in the conventional MESFET manufacturing method, since the gate pattern and the source / drain pattern are exposed by using different photomasks, the gate pattern and the source / drain are exposed. There is a problem that the positional relationship between the patterns tends to vary depending on the mask alignment accuracy. Therefore, it is difficult to obtain a MESFET having uniform characteristics. MESF
When the gate length is shortened and the distance between the gate electrode and the source / drain electrodes is shortened in order to improve the ET characteristics, the influence of the mask alignment accuracy becomes larger, so that the characteristics are more likely to vary.

The present invention has been made in view of the drawbacks of the above conventional examples, and an object of the present invention is to eliminate variations in the positional relationship between the gate electrode and the source and drain electrodes, and to eliminate the MESFET. The aim is to make the characteristics uniform.

[0007]

According to a method of manufacturing a semiconductor device of the present invention, a photoresist film is formed on a semiconductor substrate having an operating layer, and a source pattern is formed on the photoresist film.
The method includes a step of simultaneously opening the gate pattern and the drain pattern, and a step of covering the source pattern, the gate pattern, and the drain pattern with an insulating film. Next, after these steps, the step of removing the insulating film covering the gate pattern and forming a gate electrode on the semiconductor substrate exposed from the gate pattern, and the step of removing the insulating film covering the source pattern and the drain pattern are performed. And a step of forming a source electrode and a drain electrode on the semiconductor substrate exposed from the source pattern and the drain pattern.

[0008]

According to the method of manufacturing a semiconductor device of the present invention, 1
After opening the gate pattern, the source pattern, and the drain pattern in the photoresist film at the same time in the lithography process once, and covering the entire pattern once with the insulating film,
The insulating film covering the gate pattern is removed to form a gate electrode, and the insulating film covering the source pattern and the drain pattern is removed to form a source electrode and a drain electrode. Therefore, the positional relationship between the gate pattern, the source pattern and the drain pattern is affected by the alignment accuracy of the mask as in the conventional example in which the gate pattern and the source pattern and the drain pattern are formed by separate lithography processes. And the variation can be reduced. Therefore, with the gate electrode,
It is possible to eliminate variations in the positional relationship between the source electrode and the drain electrode, and to provide a field-effect semiconductor device having uniform characteristics.

[0009]

1 (a) to 1 (f) show a method for manufacturing a MESFET 11 according to an embodiment of the present invention. This MES
In the method of manufacturing the FET 11, as shown in FIG. 1A, a photoresist film 2 is formed on a semiconductor substrate 1 having an operating layer 1a formed on the surface thereof, and a photomask is overlaid thereon for exposure. Then, the photoresist film 2 is developed to open the gate pattern 2a, the source pattern 2b, and the drain pattern 2c. At this time, the width d of the gate pattern 2a
₀ is, for example, 0.5 μm, which is the lower limit that can be accurately formed by the photolithography method.

Then, an insulating film 3 is deposited so as to cover the entire surface of the wafer by, for example, a sputtering method. Since the insulating film 3 is also deposited on the inner wall of each pattern 2a, 2b, 2c, the gate pattern 2a is narrowed by twice the film thickness Δd of the insulating film 3 deposited on the inner wall, and the width d (= d ₀
-2Δd). Since this width d becomes the gate length of the gate electrode 6 described later, the film thickness Δd of the insulating film 3 is set so as to obtain a desired gate length.

Then, as shown in FIG. 1B, a photoresist film 4 is formed on the insulating film 3, and a width D (where D>d>D> d) is provided above the region including the gate pattern 2a by photolithography. ₀ > d) opening 4a,
The gate pattern 2a covered with the insulating film 3 is exposed.
Since the width D of the opening 4a becomes the electrode width D (width of the upper portion) of the gate electrode 6 described later, the width D of the opening 4a is set so that the desired electrode width D can be obtained.

Next, anisotropic etching is performed by, for example, the reactive ion etching (RIE) method, as shown in FIG.
As shown in (c), etching is performed until the photoresist film 2 and the insulating film 3 on both sides of the gate pattern 2a have a predetermined thickness t. As a result, the step portions 5 and 5 of the thickness t formed of the insulating film 3 and the photoresist film 2 are formed on both sides of the gate pattern 2a. Since the thickness t of the step portions 5 and 5 becomes the height of the lower portion of the gate electrode 6 described later, the thickness t of the step portions 5 and 5 is set so as to obtain a desired height. At the same time, the width d in the gate pattern 2a
The insulating film 3 is etched over, and the gate pattern 2a having the width d is opened between the step portions 5 and 5. Next, for example, wet etching is performed to remove the exposed damaged layer of the semiconductor substrate 1 to form the recess region 1b.

Next, a gate metal is vapor-deposited on the entire surface,
When the photoresist film 4 and the gate metal are removed by the lift-off method, as shown in FIG. 1D, from the recess region 1b of the semiconductor substrate 1 to above the step portions 5 and 5,
A mushroom-type gate electrode 6 having a lower width d, a lower height of approximately t, and an upper width D is formed.

After the insulating film 3 is removed by etching to expose the semiconductor substrate 1 from the source pattern 2b and the drain pattern 2c, an ohmic metal 7 is deposited on the entire surface as shown in FIG. 1 (e). At this time, the source electrode 7b is formed on the semiconductor substrate 1 exposed from the source pattern 2b, and the drain electrode 7c is formed on the semiconductor substrate 1 exposed from the drain pattern 2c. The ohmic metal 7 is also stacked on the gate electrode 6. Finally, the photoresist film 2 and the ohmic metal 7 are removed to complete the MESFET 11 [FIG. 1 (f)].

As described above, in this embodiment, the gate pattern 2a, the source pattern 2b and the drain pattern 2c are formed on the photoresist film 2 by one lithography process.
Since the gate pattern 2a and the source pattern 2b and the drain pattern 2c are formed in separate lithography steps, the positional relationship between the patterns is affected by the mask alignment accuracy as in the conventional example. There is no. Therefore, it is possible to eliminate variations in the positional relationship between the gate electrode 6 and the source electrode 7b and the drain electrode 7c, and it is possible to provide the MESFET 11 having uniform characteristics.

The gate length d is the photoresist film 2
It can be made smaller than the width d ₀ of the gate pattern 2a opened at 2 times by twice the film thickness Δd of the insulating films 3 and 3.
Therefore, the lower limit of the width d ₀ of the gate pattern 2a that can be formed with good reproducibility by the photolithography method is 0.0.
When the thickness is 5 μm, the gate electrode 6 having the gate length d smaller than that by twice the film thickness Δd of the insulating films 3 and 3 can be formed with good reproducibility.

Further, since the gate electrode 6 is formed in a mushroom type and the ohmic metal 7 is further laminated, the gate resistance can be reduced.

In the above-mentioned embodiment, the insulating film 3 covering the gate pattern 2a is removed first to form the gate electrode 6 before the source and drain electrodes 7b and 7c, but conversely, the source and drain electrodes 7b and 7c are formed. The source and drain electrodes 7 are formed by first removing the insulating film 3 covering the drain patterns 2b and 2c.
b and 7c may be formed before the gate electrode 6.

The present invention can also be applied to a MESFET having source and drain regions (high concentration ion regions) in a part of a semiconductor substrate by ion implantation or the like. Further, it is not limited to MESFET, and for example, H
It can also be applied to EMT.

[0020]

According to the method of manufacturing a semiconductor device of the present invention, since the gate pattern, the source pattern and the drain pattern are simultaneously opened in the photoresist film in one photolithography process, the mutual positional relationship between the patterns is different. It is determined only by the pattern accuracy of the mask without being affected by the mask alignment accuracy. Therefore, the positional relationship between the gate electrode, the source electrode, and the drain electrode can be accurately obtained, and a semiconductor device having uniform characteristics can be provided.

[Brief description of drawings]

1A, 1B, 1C, 1D, 1E, and 1F are cross-sectional views showing a method for manufacturing a semiconductor device according to an embodiment of the present invention.

[Explanation of symbols]

 1 semiconductor substrate 1a operating layer 2 photoresist film 2a gate pattern 2b source pattern 2c drain pattern 3 insulating film 6 gate electrode 7b source electrode 7c drain electrode

Claims (1)

[Claims] 1. A step of forming a photoresist film on a semiconductor substrate having an operation layer and simultaneously opening a source pattern, a gate pattern and a drain pattern in the photoresist film, and a step of forming the source pattern, the gate pattern and the drain pattern. A step of covering with an insulating film, a step of removing the insulating film covering the gate pattern and forming a gate electrode on the semiconductor substrate exposed from the gate pattern, and a step of removing the insulating film covering the source pattern and the drain pattern. And a step of forming a source electrode and a drain electrode on the semiconductor substrate exposed from the source pattern and the drain pattern.