JPH0684692A - Multilayer ceramic chip capacitor - Google Patents
Multilayer ceramic chip capacitorInfo
- Publication number
- JPH0684692A JPH0684692A JP5085705A JP8570593A JPH0684692A JP H0684692 A JPH0684692 A JP H0684692A JP 5085705 A JP5085705 A JP 5085705A JP 8570593 A JP8570593 A JP 8570593A JP H0684692 A JPH0684692 A JP H0684692A
- Authority
- JP
- Japan
- Prior art keywords
- oxide
- converted
- multilayer ceramic
- chip capacitor
- sio
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000003990 capacitor Substances 0.000 title claims abstract description 63
- 239000000919 ceramic Substances 0.000 title claims abstract description 44
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims abstract description 13
- 229910002113 barium titanate Inorganic materials 0.000 claims abstract description 13
- 239000000203 mixture Substances 0.000 claims abstract description 13
- CPLXHLVBOLITMK-UHFFFAOYSA-N magnesium oxide Inorganic materials [Mg]=O CPLXHLVBOLITMK-UHFFFAOYSA-N 0.000 claims description 44
- QVQLCTNNEUAWMS-UHFFFAOYSA-N barium oxide Chemical compound [Ba]=O QVQLCTNNEUAWMS-UHFFFAOYSA-N 0.000 claims description 40
- 239000000395 magnesium oxide Substances 0.000 claims description 31
- 239000000292 calcium oxide Substances 0.000 claims description 30
- ODINCKMPIJJUCX-UHFFFAOYSA-N calcium oxide Inorganic materials [Ca]=O ODINCKMPIJJUCX-UHFFFAOYSA-N 0.000 claims description 30
- 238000010304 firing Methods 0.000 claims description 28
- 229910004298 SiO 2 Inorganic materials 0.000 claims description 27
- AMWRITDGCCNYAT-UHFFFAOYSA-L hydroxy(oxo)manganese;manganese Chemical compound [Mn].O[Mn]=O.O[Mn]=O AMWRITDGCCNYAT-UHFFFAOYSA-L 0.000 claims description 22
- 239000004020 conductor Substances 0.000 claims description 13
- JRPBQTZRNDNNOP-UHFFFAOYSA-N barium titanate Chemical compound [Ba+2].[Ba+2].[O-][Ti]([O-])([O-])[O-] JRPBQTZRNDNNOP-UHFFFAOYSA-N 0.000 claims description 12
- AXZKOIWUVFPNLO-UHFFFAOYSA-N magnesium;oxygen(2-) Chemical compound [O-2].[Mg+2] AXZKOIWUVFPNLO-UHFFFAOYSA-N 0.000 claims description 12
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims description 11
- 239000011575 calcium Substances 0.000 claims description 11
- 229910052760 oxygen Inorganic materials 0.000 claims description 11
- 239000001301 oxygen Substances 0.000 claims description 11
- 230000036961 partial effect Effects 0.000 claims description 11
- BRPQOXSCLDDYGP-UHFFFAOYSA-N calcium oxide Chemical compound [O-2].[Ca+2] BRPQOXSCLDDYGP-UHFFFAOYSA-N 0.000 claims description 10
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 10
- 229910000990 Ni alloy Inorganic materials 0.000 claims description 8
- SIWVEOZUMHYXCS-UHFFFAOYSA-N oxo(oxoyttriooxy)yttrium Chemical compound O=[Y]O[Y]=O SIWVEOZUMHYXCS-UHFFFAOYSA-N 0.000 claims description 8
- 239000011572 manganese Substances 0.000 claims description 3
- 229910052748 manganese Inorganic materials 0.000 claims description 2
- PWHULOQIROXLJO-UHFFFAOYSA-N Manganese Chemical compound [Mn] PWHULOQIROXLJO-UHFFFAOYSA-N 0.000 claims 1
- 238000009413 insulation Methods 0.000 abstract description 8
- 230000001133 acceleration Effects 0.000 abstract description 3
- 230000032683 aging Effects 0.000 abstract 1
- 229910052681 coesite Inorganic materials 0.000 abstract 1
- 229910052906 cristobalite Inorganic materials 0.000 abstract 1
- 239000000377 silicon dioxide Substances 0.000 abstract 1
- 235000012239 silicon dioxide Nutrition 0.000 abstract 1
- 229910052682 stishovite Inorganic materials 0.000 abstract 1
- 229910052905 tridymite Inorganic materials 0.000 abstract 1
- 239000010410 layer Substances 0.000 description 86
- 238000000034 method Methods 0.000 description 28
- 238000012937 correction Methods 0.000 description 21
- 230000005684 electric field Effects 0.000 description 19
- 239000007789 gas Substances 0.000 description 19
- 239000003989 dielectric material Substances 0.000 description 14
- 238000000137 annealing Methods 0.000 description 13
- 239000011230 binding agent Substances 0.000 description 12
- 239000002245 particle Substances 0.000 description 11
- 239000002003 electrode paste Substances 0.000 description 9
- 239000013078 crystal Substances 0.000 description 8
- TWNQGVIAIRXVLR-UHFFFAOYSA-N oxo(oxoalumanyloxy)alumane Chemical compound O=[Al]O[Al]=O TWNQGVIAIRXVLR-UHFFFAOYSA-N 0.000 description 8
- 238000001816 cooling Methods 0.000 description 7
- 239000010953 base metal Substances 0.000 description 6
- 229910052759 nickel Inorganic materials 0.000 description 6
- 238000005498 polishing Methods 0.000 description 6
- OAYXUHPQHDHDDZ-UHFFFAOYSA-N 2-(2-butoxyethoxy)ethanol Chemical compound CCCCOCCOCCO OAYXUHPQHDHDDZ-UHFFFAOYSA-N 0.000 description 5
- 239000000956 alloy Substances 0.000 description 5
- 229910045601 alloy Inorganic materials 0.000 description 5
- 230000007423 decrease Effects 0.000 description 5
- 238000011282 treatment Methods 0.000 description 5
- CSCPPACGZOOCGX-UHFFFAOYSA-N Acetone Chemical compound CC(C)=O CSCPPACGZOOCGX-UHFFFAOYSA-N 0.000 description 4
- 230000000052 comparative effect Effects 0.000 description 4
- 150000001875 compounds Chemical class 0.000 description 4
- 238000000280 densification Methods 0.000 description 4
- 239000000843 powder Substances 0.000 description 4
- 230000002829 reductive effect Effects 0.000 description 4
- LIVNPJMFVYWSIS-UHFFFAOYSA-N silicon monoxide Chemical compound [Si-]#[O+] LIVNPJMFVYWSIS-UHFFFAOYSA-N 0.000 description 4
- YMWUJEATGCHHMB-UHFFFAOYSA-N Dichloromethane Chemical compound ClCCl YMWUJEATGCHHMB-UHFFFAOYSA-N 0.000 description 3
- 239000001856 Ethyl cellulose Substances 0.000 description 3
- ZZSNKZQZMQGXPY-UHFFFAOYSA-N Ethyl cellulose Chemical compound CCOCC1OC(OC)C(OCC)C(OCC)C1OC1C(O)C(O)C(OC)C(CO)O1 ZZSNKZQZMQGXPY-UHFFFAOYSA-N 0.000 description 3
- MUBZPKHOEPUJKR-UHFFFAOYSA-N Oxalic acid Chemical compound OC(=O)C(O)=O MUBZPKHOEPUJKR-UHFFFAOYSA-N 0.000 description 3
- 229910010413 TiO 2 Inorganic materials 0.000 description 3
- YXFVVABEGXRONW-UHFFFAOYSA-N Toluene Chemical compound CC1=CC=CC=C1 YXFVVABEGXRONW-UHFFFAOYSA-N 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 229920001249 ethyl cellulose Polymers 0.000 description 3
- 235000019325 ethyl cellulose Nutrition 0.000 description 3
- VASIZKWUTCETSD-UHFFFAOYSA-N manganese(II) oxide Inorganic materials [Mn]=O VASIZKWUTCETSD-UHFFFAOYSA-N 0.000 description 3
- 239000000463 material Substances 0.000 description 3
- 239000003960 organic solvent Substances 0.000 description 3
- 230000000630 rising effect Effects 0.000 description 3
- 238000005488 sandblasting Methods 0.000 description 3
- 238000005245 sintering Methods 0.000 description 3
- 229910018072 Al 2 O 3 Inorganic materials 0.000 description 2
- 230000005540 biological transmission Effects 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- 239000002131 composite material Substances 0.000 description 2
- 239000011258 core-shell material Substances 0.000 description 2
- 238000004898 kneading Methods 0.000 description 2
- 229910052751 metal Inorganic materials 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- -1 or various oxides Chemical class 0.000 description 2
- 150000002902 organometallic compounds Chemical class 0.000 description 2
- 230000003647 oxidation Effects 0.000 description 2
- 238000007254 oxidation reaction Methods 0.000 description 2
- 229920000139 polyethylene terephthalate Polymers 0.000 description 2
- 238000012545 processing Methods 0.000 description 2
- 239000011347 resin Substances 0.000 description 2
- 229920005989 resin Polymers 0.000 description 2
- 239000000758 substrate Substances 0.000 description 2
- 238000012360 testing method Methods 0.000 description 2
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 2
- UOCLXMDMGBRAIB-UHFFFAOYSA-N 1,1,1-trichloroethane Chemical compound CC(Cl)(Cl)Cl UOCLXMDMGBRAIB-UHFFFAOYSA-N 0.000 description 1
- 239000004925 Acrylic resin Substances 0.000 description 1
- 229920000178 Acrylic resin Polymers 0.000 description 1
- 229920002799 BoPET Polymers 0.000 description 1
- BVKZGUZCCUSVTD-UHFFFAOYSA-L Carbonate Chemical compound [O-]C([O-])=O BVKZGUZCCUSVTD-UHFFFAOYSA-L 0.000 description 1
- XWROUVVQGRRRMF-UHFFFAOYSA-N F.O[N+]([O-])=O Chemical compound F.O[N+]([O-])=O XWROUVVQGRRRMF-UHFFFAOYSA-N 0.000 description 1
- 101100513612 Microdochium nivale MnCO gene Proteins 0.000 description 1
- 229910018663 Mn O Inorganic materials 0.000 description 1
- 229910002651 NO3 Inorganic materials 0.000 description 1
- NHNBFGGVMKEFGY-UHFFFAOYSA-N Nitrate Chemical compound [O-][N+]([O-])=O NHNBFGGVMKEFGY-UHFFFAOYSA-N 0.000 description 1
- 229910002367 SrTiO Inorganic materials 0.000 description 1
- 238000003917 TEM image Methods 0.000 description 1
- 239000000654 additive Substances 0.000 description 1
- WUOACPNHFRMFPN-UHFFFAOYSA-N alpha-terpineol Chemical compound CC1=CCC(C(C)(C)O)CC1 WUOACPNHFRMFPN-UHFFFAOYSA-N 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- 239000007864 aqueous solution Substances 0.000 description 1
- 229910052788 barium Inorganic materials 0.000 description 1
- 229910052791 calcium Inorganic materials 0.000 description 1
- 239000003985 ceramic capacitor Substances 0.000 description 1
- 229910052804 chromium Inorganic materials 0.000 description 1
- 239000011247 coating layer Substances 0.000 description 1
- 229910000428 cobalt oxide Inorganic materials 0.000 description 1
- IVMYJDGYRUAWML-UHFFFAOYSA-N cobalt(ii) oxide Chemical compound [Co]=O IVMYJDGYRUAWML-UHFFFAOYSA-N 0.000 description 1
- SQIFACVGCPWBQZ-UHFFFAOYSA-N delta-terpineol Natural products CC(C)(O)C1CCC(=C)CC1 SQIFACVGCPWBQZ-UHFFFAOYSA-N 0.000 description 1
- 239000002270 dispersing agent Substances 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- XLYOFNOQVPJJNP-UHFFFAOYSA-M hydroxide Chemical compound [OH-] XLYOFNOQVPJJNP-UHFFFAOYSA-M 0.000 description 1
- 230000002401 inhibitory effect Effects 0.000 description 1
- 229910052500 inorganic mineral Inorganic materials 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 238000010030 laminating Methods 0.000 description 1
- 230000000670 limiting effect Effects 0.000 description 1
- 239000011777 magnesium Substances 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 238000005259 measurement Methods 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 239000011707 mineral Substances 0.000 description 1
- 238000002156 mixing Methods 0.000 description 1
- 229910052758 niobium Inorganic materials 0.000 description 1
- 235000006408 oxalic acid Nutrition 0.000 description 1
- 229910052763 palladium Inorganic materials 0.000 description 1
- 239000004014 plasticizer Substances 0.000 description 1
- 238000007747 plating Methods 0.000 description 1
- 229910052573 porcelain Inorganic materials 0.000 description 1
- 238000002360 preparation method Methods 0.000 description 1
- 229910052761 rare earth metal Inorganic materials 0.000 description 1
- 150000003839 salts Chemical class 0.000 description 1
- 239000004576 sand Substances 0.000 description 1
- 238000001878 scanning electron micrograph Methods 0.000 description 1
- 238000005476 soldering Methods 0.000 description 1
- 239000002904 solvent Substances 0.000 description 1
- 239000007921 spray Substances 0.000 description 1
- 229910052715 tantalum Inorganic materials 0.000 description 1
- 229940116411 terpineol Drugs 0.000 description 1
- 229910052720 vanadium Inorganic materials 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01G—CAPACITORS; CAPACITORS, RECTIFIERS, DETECTORS, SWITCHING DEVICES, LIGHT-SENSITIVE OR TEMPERATURE-SENSITIVE DEVICES OF THE ELECTROLYTIC TYPE
- H01G4/00—Fixed capacitors; Processes of their manufacture
- H01G4/002—Details
- H01G4/018—Dielectrics
- H01G4/06—Solid dielectrics
- H01G4/08—Inorganic dielectrics
- H01G4/12—Ceramic dielectrics
- H01G4/1209—Ceramic dielectrics characterised by the ceramic dielectric material
- H01G4/1218—Ceramic dielectrics characterised by the ceramic dielectric material based on titanium oxides or titanates
Landscapes
- Engineering & Computer Science (AREA)
- Ceramic Engineering (AREA)
- Chemical & Material Sciences (AREA)
- Power Engineering (AREA)
- Inorganic Chemistry (AREA)
- Manufacturing & Machinery (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Compositions Of Oxide Ceramics (AREA)
- Ceramic Capacitors (AREA)
- Inorganic Insulating Materials (AREA)
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は、積層型セラミックチッ
プコンデンサに関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a multilayer ceramic chip capacitor.
【０００２】[0002]
【従来の技術】積層型セラミックチップコンデンサは、
小型、大容量、高信頼性の電子部品として広く利用され
ており、１台の電子機器の中で使用される個数も多数に
のぼる。近年、機器の小型・高性能化にともない、積層
型セラミックチップコンデンサに対する更なる小型、大
容量、低価格、高信頼性化への要求はますます厳しくな
っている。2. Description of the Related Art Multilayer ceramic chip capacitors are
It is widely used as a small-sized, large-capacity, highly-reliable electronic component, and a large number of electronic components are used in one electronic device. In recent years, with the miniaturization and high performance of devices, the demands for further miniaturization, large capacity, low cost and high reliability of multilayer ceramic chip capacitors have become more and more severe.
【０００３】積層型セラミックチップコンデンサは通
常、内部電極層用のペーストと誘電体層用のペーストと
をシート法や印刷法等により積層し、一体同時焼成して
製造される。A laminated ceramic chip capacitor is usually manufactured by laminating a paste for an internal electrode layer and a paste for a dielectric layer by a sheet method, a printing method or the like, and integrally firing them.
【０００４】内部電極層の導電材には、一般にＰｄやＰ
ｄ合金が用いられているが、Ｐｄは高価であるため、比
較的安価なＮｉやＮｉ合金等の卑金属が使用されつつあ
る。内部電極層の導電材として卑金属を用いる場合、大
気中で焼成を行なうと内部電極層が酸化してしまうた
め、誘電体層と内部電極層との同時焼成を、還元性雰囲
気中で行なう必要がある。しかし、還元性雰囲気中で焼
成すると、誘電体層が還元され、比抵抗が低くなってし
まうため、非還元性の誘電体材料が提案されている。Generally, Pd or P is used as the conductive material of the internal electrode layers.
Although the d alloy is used, since Pd is expensive, base metals such as Ni and Ni alloy, which are relatively inexpensive, are being used. When a base metal is used as the conductive material of the internal electrode layer, the internal electrode layer is oxidized when firing in the air. Therefore, it is necessary to perform simultaneous firing of the dielectric layer and the internal electrode layer in a reducing atmosphere. is there. However, when firing in a reducing atmosphere, the dielectric layer is reduced and the specific resistance decreases, so a non-reducing dielectric material has been proposed.
【０００５】しかし、非還元性の誘電体材料を用いた積
層型セラミックチップコンデンサは、絶縁抵抗ＩＲの寿
命が短くなり、信頼性が低いという問題がある。However, the multilayer ceramic chip capacitor using a non-reducing dielectric material has a problem that the insulation resistance IR has a short life and its reliability is low.
【０００６】また、誘電体を直流電界にさらすと、比誘
電率εs が経時的に低下するという問題が生じる。チッ
プコンデンサを小型、大容量化するために誘電体層の厚
みを薄くすると、直流電圧を印加したときの誘電体層に
かかる電界が強くなるため、比誘電率εs の経時変化、
すなわち容量の経時変化が著しく大きくなってしまう。Further, when the dielectric is exposed to a DC electric field, there arises a problem that the relative permittivity ε s decreases with time. If the thickness of the dielectric layer is reduced in order to reduce the size and increase the capacity of the chip capacitor, the electric field applied to the dielectric layer when a DC voltage is applied becomes stronger, so the relative permittivity ε s changes over time,
That is, the change in capacity with time becomes significantly large.
【０００７】ところで、ＥＩＡ規格に定められたＸ７Ｒ
特性と呼ばれる規格では、容量の変化率が、−５５℃か
ら１２５℃の間で±１５％以内（基準温度２５℃）と定
められている。By the way, the X7R specified in the EIA standard
According to the standard called “characteristics”, the rate of change of capacity is determined to be within ± 15% (reference temperature 25 ° C.) between −55 ° C. and 125 ° C.
【０００８】Ｘ７Ｒ特性を満足する誘電体材料として
は、例えば特開昭６１−３６１７０号公報に示されるＢ
ａＴｉＯ3 ＋ＳｒＴｉＯ3 ＋ＭｎＯ系の組成が知られて
いる。しかし、このものは、直流電界下における容量の
経時変化が大きく、例えば４０℃で５０V の直流電界を
１０００時間印加すると、容量の変化率が−１０〜−３
０％程度となってしまい、Ｘ７Ｒ特性を満足することが
できなくなる。A dielectric material satisfying the X7R characteristic is, for example, B shown in JP-A-61-36170.
A composition of aTiO 3 + SrTiO 3 + MnO system is known. However, this capacitor has a large change with time in the DC electric field, and for example, when a DC electric field of 50 V at 40 ° C. is applied for 1000 hours, the rate of change of the capacitance is −10 to −3.
It becomes about 0% and the X7R characteristic cannot be satisfied.
【０００９】また、この他、非還元性の誘電体磁器組成
物としては、特開昭５７−７１８６６号公報に開示され
ているＢａＴｉＯ3 ＋ＭｎＯ＋ＭｇＯ、特開昭６１−２
５０９０５号公報に開示されている（Ｂａ1-x Ｓｒx
Ｏ）a Ｔｉ1-y Ｚｒy Ｏ2 ＋α（（１−ｚ）ＭｎＯ＋ｚ
ＣｏＯ）＋β（（１−ｔ）Ａ2 Ｏ5 ＋ｔＬ2 Ｏ3 ）＋ｗ
ＳｉＯ2 （ただし、Ａ＝Ｎｂ，Ｔａ，Ｖ、Ｌ＝Ｙまたは
希土類元素）、特開平２−８３２５６号公報に開示され
ているチタン酸バリウムにガラス状態のＢａαＣａ1-α
ＳｉＯ3 を添加したものなどが挙げられる。しかし、こ
れらのいずれの誘電体磁器組成物も、容量の温度特性が
良好で、直流電界下での容量の経時変化が少なく、絶縁
抵抗の加速寿命が長いという特性の全てを満足すること
はできなかった。例えば、特開昭６１−２５０９０５号
公報および特開平２−８３２５６号公報にそれぞれ開示
されているものでは、絶縁抵抗の加速寿命が短い。Other non-reducing dielectric ceramic compositions include BaTiO 3 + MnO + MgO disclosed in JP-A-57-71866 and JP-A-61-2.
No. 50905 (Ba 1-x Sr x
O) a Ti 1-y Zr y O 2 + α ((1-z) MnO + z
CoO) + β ((1-t) A 2 O 5 + tL 2 O 3 ) + w
SiO 2 (however, A = Nb, Ta, V, L = Y or a rare earth element), BaαCa 1- α in the glass state in barium titanate disclosed in JP-A-2-83256.
Examples thereof include those to which SiO 3 is added. However, any of these dielectric porcelain compositions cannot satisfy all of the characteristics that the temperature characteristic of the capacity is good, the capacity does not change with time under a DC electric field, and the accelerated life of the insulation resistance is long. There wasn't. For example, in each of JP-A-61-250905 and JP-A-2-83256, the accelerated life of insulation resistance is short.
【００１０】[0010]
【発明が解決しようとする課題】本発明はこのような事
情からなされたものであり、容量の温度特性であるＸ７
Ｒ特性（ＥＩＡ規格）およびＢ特性（ＥＩＡＪ規格）を
いずれも満足することができ、かつ、直流電界下での容
量の経時変化が小さく、また、絶縁抵抗ＩＲの加速寿命
が長い積層型セラミックチップコンデンサを提供するこ
とを目的とする。SUMMARY OF THE INVENTION The present invention has been made under these circumstances, and it is X7 which is a temperature characteristic of capacity.
A multilayer ceramic chip that can satisfy both the R characteristic (EIA standard) and the B characteristic (EIAJ standard), has a small change in capacitance over time under a DC electric field, and has a long accelerated life of the insulation resistance IR. The purpose is to provide a capacitor.
【００１１】[0011]
【課題を解決するための手段】このような目的は、下記
（１）〜（７）の本発明により達成される。 （１）誘電体層と内部電極層とが交互に積層された構成
のコンデンサチップ体を有する積層型セラミックチップ
コンデンサであって、前記誘電体層が、主成分としてチ
タン酸バリウムを、副成分として酸化マグネシウムと、
酸化マンガンと、酸化バリウムおよび酸化カルシウムか
ら選択される少なくとも１種と、酸化ケイ素とを含有
し、チタン酸バリウムをＢａＴｉＯ3 に、酸化マグネシ
ウムをＭｇＯに、酸化マンガンをＭｎＯに、酸化バリウ
ムをＢａＯに、酸化カルシウムをＣａＯに、酸化ケイ素
をＳｉＯ2 にそれぞれ換算したとき、ＢａＴｉＯ3 １０
０モルに対する比率がＭｇＯ：０．１〜３モル、Ｍｎ
Ｏ：０．０５〜１．０モル、ＢａＯ＋ＣａＯ：２〜１２
モル、ＳｉＯ2 ：２〜１２モルであることを特徴とする
積層型セラミックチップコンデンサ。 （２）前記ＢａＴｉＯ3 、ＭｇＯおよびＭｎＯの合計に
対し、ＢａＯ、ＣａＯおよびＳｉＯ2 が（Ｂａx Ｃａ
1-x Ｏ）y ・ＳｉＯ2 （ただし、０．３≦ｘ≦０．７、
０．９５≦ｙ≦１．０５である。）として１〜１０重量
％含有される上記（１）の積層型セラミックチップコン
デンサ。 （３）誘電体層と内部電極層とが交互に積層された構成
のコンデンサチップ体を有する積層型セラミックチップ
コンデンサであって、前記誘電体層が、主成分としてチ
タン酸バリウムを、副成分として酸化マグネシウムと、
酸化マンガンと、酸化イットリウムと、酸化バリウムお
よび酸化カルシウムから選択される少なくとも１種と、
酸化ケイ素とを含有し、チタン酸バリウムをＢａＴｉＯ
3 に、酸化マグネシウムをＭｇＯに、酸化マンガンをＭ
ｎＯに、酸化イットリウムをＹ2 Ｏ3 に、酸化バリウム
をＢａＯに、酸化カルシウムをＣａＯに、酸化ケイ素を
ＳｉＯ2 にそれぞれ換算したとき、ＢａＴｉＯ3 １００
モルに対する比率がＭｇＯ：０．１〜３モル、ＭｎＯ：
０．０５〜１．０モル、Ｙ2 Ｏ3 ：１モル以下、ＢａＯ
＋ＣａＯ：２〜１２モル、ＳｉＯ2 ：２〜１２モルであ
ることを特徴とする積層型セラミックチップコンデン
サ。 （４）ＢａＴｉＯ3 、ＭｇＯ、ＭｎＯおよびＹ2 Ｏ3 の
合計に対し、ＢａＯ、ＣａＯおよびＳｉＯ2 が（Ｂａx
Ｃａ1-x Ｏ）y ・ＳｉＯ2 （ただし、０．３≦ｘ≦０．
７、０．９５≦ｙ≦１．０５である。）として１〜１０
重量％含有される上記（３）の積層型セラミックチップ
コンデンサ。 （５）前記内部電極層に含まれる導電材が、Ｎｉまたは
Ｎｉ合金である上記（１）ないし（４）のいずれかの積
層型セラミックチップコンデンサ。 （６）酸素分圧が１０-8〜１０-12 気圧である雰囲気中
で、１２００〜１４００℃の温度範囲内にて焼成された
上記（５）の積層型セラミックチップコンデンサ。 （７）焼成後に、酸素分圧が１０-6気圧以上の雰囲気中
で１１００℃以下の温度範囲内にてアニールされた上記
（５）または（６）の積層型セラミックチップコンデン
サ。These objects are achieved by the present invention described in (1) to (7) below. (1) A multilayer ceramic chip capacitor having a capacitor chip body in which dielectric layers and internal electrode layers are alternately laminated, wherein the dielectric layer contains barium titanate as a main component and a sub-component. Magnesium oxide,
It contains manganese oxide, at least one selected from barium oxide and calcium oxide, and silicon oxide. Barium titanate is converted into BaTiO 3 , magnesium oxide is converted into MgO, manganese oxide is converted into MnO, and barium oxide is converted into BaO. When calcium oxide is converted to CaO and silicon oxide is converted to SiO 2 , BaTiO 3 10
The ratio with respect to 0 mol is MgO: 0.1 to 3 mol, Mn
O: 0.05 to 1.0 mol, BaO + CaO: 2 to 12
Mole, SiO 2 : 2 to 12 moles. Multilayer ceramic chip capacitor. (2) BaO, CaO and SiO 2 are (Ba x Ca) based on the total of BaTiO 3 , MgO and MnO.
1-x O) y · SiO 2 (where 0.3 ≦ x ≦ 0.7,
0.95 ≦ y ≦ 1.05. 1 to 10% by weight as the above), the multilayer ceramic chip capacitor of the above (1). (3) A multilayer ceramic chip capacitor having a capacitor chip body in which dielectric layers and internal electrode layers are alternately laminated, wherein the dielectric layer contains barium titanate as a main component and a sub-component as a sub-component. Magnesium oxide,
Manganese oxide, yttrium oxide, and at least one selected from barium oxide and calcium oxide,
Barium titanate containing BaTiO 3 containing silicon oxide
3 , magnesium oxide to MgO, manganese oxide to M
When nO, yttrium oxide are converted into Y 2 O 3 , barium oxide is converted into BaO, calcium oxide is converted into CaO, and silicon oxide is converted into SiO 2 , BaTiO 3 100
The ratio to the moles is MgO: 0.1 to 3 moles, MnO:
0.05 to 1.0 mol, Y 2 O 3: 1 mole or less, BaO
+ CaO: 2 to 12 moles, SiO 2 : 2 to 12 moles, a multilayer ceramic chip capacitor. (4) With respect to the total of BaTiO 3 , MgO, MnO and Y 2 O 3 , BaO, CaO and SiO 2 are (Ba x
Ca 1-x O) y · SiO 2 (where 0.3 ≦ x ≦ 0.
7, 0.95 ≦ y ≦ 1.05. ) As 1-10
The multilayer ceramic chip capacitor as described in (3) above, which is contained in a weight percentage. (5) The multilayer ceramic chip capacitor according to any of (1) to (4) above, wherein the conductive material contained in the internal electrode layers is Ni or a Ni alloy. (6) The multilayer ceramic chip capacitor according to (5) above, which is fired within a temperature range of 1200 to 1400 ° C. in an atmosphere having an oxygen partial pressure of 10 −8 to 10 −12 atm. (7) The multilayer ceramic chip capacitor according to (5) or (6) above, which is annealed in a temperature range of 1100 ° C. or lower in an atmosphere having an oxygen partial pressure of 10 −6 atm or higher after firing.
【００１２】[0012]
【具体的構成】以下、本発明の具体的構成について詳細
に説明する。Specific Structure The specific structure of the present invention will be described in detail below.
【００１３】［積層型セラミックチップコンデンサ］本
発明の積層型セラミックチップコンデンサの構成例の断
面図を、図１に示す。[Multilayer Ceramic Chip Capacitor] FIG. 1 is a sectional view showing an example of the structure of the multilayer ceramic chip capacitor of the present invention.
【００１４】図１に示されるように、本発明の積層型セ
ラミックチップコンデンサ１は、誘電体層２と内部電極
層３とが交互に積層された構成のコンデンサチップ体１
０を有し、このコンデンサチップ体１０表面に、内部電
極層３と導通する外部電極４を有する。コンデンサチッ
プ体１０の形状に特に制限はないが、通常、直方体状と
される。また、その寸法にも特に制限はなく、用途に応
じて適当な寸法とすればよいが、通常、（１．０〜５．
６mm）×（０．５〜５．０mm）×（０．５〜１．９mm）
程度である。内部電極層３は、その端面がコンデンサチ
ップ体１０の対向する２表面に交互に露出するように積
層され、外部電極４は、コンデンサチップ体１０の前記
対向する２表面に形成され、所定のコンデンサ回路を構
成する。As shown in FIG. 1, the multilayer ceramic chip capacitor 1 of the present invention is a capacitor chip body 1 having a structure in which dielectric layers 2 and internal electrode layers 3 are alternately laminated.
0, and the external electrode 4 which is electrically connected to the internal electrode layer 3 is provided on the surface of the capacitor chip body 10. The shape of the capacitor chip body 10 is not particularly limited, but is usually a rectangular parallelepiped shape. The size is not particularly limited, and may be an appropriate size depending on the application, but usually (1.0 to 5.
6 mm) x (0.5 to 5.0 mm) x (0.5 to 1.9 mm)
It is a degree. The internal electrode layers 3 are laminated so that their end faces are alternately exposed on the two opposing surfaces of the capacitor chip body 10, and the external electrodes 4 are formed on the two opposing surfaces of the capacitor chip body 10 to form a predetermined capacitor. Make up the circuit.
【００１５】＜誘電体層２＞誘電体層２は、主成分とし
てチタン酸バリウム、副成分として酸化マグネシウム
と、酸化マンガンと、酸化バリウムおよび酸化カルシウ
ムから選択される少なくとも１種と、酸化ケイ素とを含
有する。チタン酸バリウムをＢａＴｉＯ3 に、酸化マグ
ネシウムをＭｇＯに、酸化マンガンをＭｎＯに、酸化バ
リウムをＢａＯに、酸化カルシウムをＣａＯに、酸化ケ
イ素をＳｉＯ2 にそれぞれ換算したとき、誘電体層中に
おける各化合物の比率は、ＢａＴｉＯ3 １００モルに対
しＭｇＯ：０．１〜３モル、好ましくは０．５〜１．５
モル、ＭｎＯ：０．０５〜１．０モル、好ましくは０．
２〜０．４モル、ＢａＯ＋ＣａＯ：２〜１２モル、Ｓｉ
Ｏ2 ：２〜１２モルである。<Dielectric Layer 2> The dielectric layer 2 includes barium titanate as a main component, magnesium oxide as a subcomponent, manganese oxide, at least one selected from barium oxide and calcium oxide, and silicon oxide. Contains. When barium titanate is converted into BaTiO 3 , magnesium oxide into MgO, manganese oxide into MnO, barium oxide into BaO, calcium oxide into CaO, and silicon oxide into SiO 2 , each compound in the dielectric layer is converted. The ratio of MgO is 0.1 to 3 mol, preferably 0.5 to 1.5, based on 100 mol of BaTiO 3.
Mol, MnO: 0.05 to 1.0 mol, preferably 0.1.
2 to 0.4 mol, BaO + CaO: 2 to 12 mol, Si
O 2 : 2 to 12 mol.
【００１６】（ＢａＯ＋ＣａＯ）／ＳｉＯ2 は特に限定
されないが、通常、０．９〜１．１とすることが好まし
い。ＢａＯ、ＣａＯおよびＳｉＯ2 は、（Ｂａx Ｃａ
1-x Ｏ）y ・ＳｉＯ2 として含まれていてもよい。この
場合、緻密な焼結体を得るためには０．３≦ｘ≦０．
７、０．９５≦ｙ≦１．０５とすることが好ましい。
（Ｂａx Ｃａ1-x Ｏ）y ・ＳｉＯ2 の含有量は、ＢａＴ
ｉＯ3 、ＭｇＯおよびＭｎＯの合計に対し、好ましくは
１〜１０重量％、より好ましくは４〜６重量％である。
なお、各酸化物の酸化状態は特に限定されず、各酸化物
を構成する金属元素の含有量が上記範囲であればよい。Although (BaO + CaO) / SiO 2 is not particularly limited, it is usually preferably 0.9 to 1.1. BaO, CaO and SiO 2 are (Ba x Ca
1-x O) y · SiO 2 may be contained. In this case, in order to obtain a dense sintered body, 0.3 ≦ x ≦ 0.
7, preferably 0.95 ≦ y ≦ 1.05.
The content of (Ba x Ca 1-x O) y · SiO 2 is BaT
It is preferably 1 to 10% by weight, more preferably 4 to 6% by weight, based on the total of iO 3 , MgO and MnO.
The oxidation state of each oxide is not particularly limited as long as the content of the metal element forming each oxide is within the above range.
【００１７】誘電体層２には、ＢａＴｉＯ3 に換算した
チタン酸バリウム１００モルに対し、Ｙ2 Ｏ3 に換算し
て１モル以下の酸化イットリウムが副成分として含まれ
ることが好ましい。Ｙ2 Ｏ3 含有量の下限は特にない
が、十分な効果を実現するためには０．１モル以上含ま
れることが好ましい。酸化イットリウムを含む場合、
（Ｂａx Ｃａ1-x Ｏ）y ・ＳｉＯ2 の含有量は、ＢａＴ
ｉＯ3 、ＭｇＯ、ＭｎＯおよびＹ2 Ｏ3 の合計に対し好
ましくは１〜１０重量％、より好ましくは４〜６重量％
である。The dielectric layer 2 preferably contains 1 mol or less of yttrium oxide as Y 2 O 3 converted to BaTiO 3 converted to 100 mol of barium titanate as an accessory component. There is no particular lower limit to the Y 2 O 3 content, but in order to realize a sufficient effect, it is preferably contained in an amount of 0.1 mol or more. When it contains yttrium oxide,
The content of (Ba x Ca 1-x O) y · SiO 2 is BaT
Preferably 1 to 10% by weight, more preferably 4 to 6% by weight, based on the total of iO 3 , MgO, MnO and Y 2 O 3.
Is.
【００１８】なお、誘電体層２には他の化合物が含まれ
ていてもよいが、酸化コバルトは容量変化率を増大させ
るので実質的に含まれないことが好ましい。Although the dielectric layer 2 may contain other compounds, it is preferable that cobalt oxide is not substantially contained because it increases the rate of change in capacitance.
【００１９】上記各副成分の含有量の限定理由は下記の
とおりである。The reasons for limiting the contents of the above subcomponents are as follows.
【００２０】酸化マグネシウムの含有量が前記範囲未満
であると、容量の温度特性を所望の範囲とすることがで
きない。酸化マグネシウムの含有量が前記範囲を超える
と、焼結性が急激に悪化し、緻密化が不十分となってＩ
Ｒ加速寿命が低下し、また、高い比誘電率が得られな
い。When the content of magnesium oxide is less than the above range, the temperature characteristic of the capacity cannot be set within a desired range. When the content of magnesium oxide exceeds the above range, the sinterability deteriorates rapidly and the densification becomes insufficient.
The R accelerated life is shortened, and a high relative dielectric constant cannot be obtained.
【００２１】酸化マンガンの含有量が前記範囲未満であ
ると、良好な耐還元性が得られずＩＲ加速寿命が不十分
となり、また、損失 tanδを低くすることが困難とな
る。酸化マンガンの含有量が前記範囲を超えている場
合、直流電界印加時の容量の経時変化を小さくすること
が困難となる。When the content of manganese oxide is less than the above range, good reduction resistance cannot be obtained, the IR accelerated life becomes insufficient, and it becomes difficult to reduce the loss tan δ. When the content of manganese oxide exceeds the above range, it becomes difficult to reduce the change with time of the capacity when a DC electric field is applied.
【００２２】ＢａＯ＋ＣａＯや、ＳｉＯ2 、（Ｂａx Ｃ
ａ1-x Ｏ）y ・ＳｉＯ2 の含有量が少なすぎると直流電
界印加時の容量の経時変化が大きくなり、また、ＩＲ加
速寿命が不十分となる。含有量が多すぎると比誘電率の
急激な低下が起こる。BaO + CaO, SiO 2 , (Ba x C
If the content of (a 1-x O) y · SiO 2 is too small, the change of the capacity with time when a DC electric field is applied becomes large, and the IR accelerated life becomes insufficient. If the content is too large, the relative dielectric constant will drop sharply.
【００２３】酸化イットリウムはＩＲ加速寿命を向上さ
せる効果を有する。酸化イットリウムの含有量が前記範
囲を超えると、静電容量が減少し、また、焼結性が低下
して緻密化が不十分となることがある。Yttrium oxide has the effect of improving the IR accelerated life. If the content of yttrium oxide exceeds the above range, the capacitance may decrease, and the sinterability may decrease, resulting in insufficient densification.
【００２４】また、誘電体層中には、酸化アルミニウム
が含有されていてもよい。酸化アルミニウムは比較的低
温での焼結を可能にする作用をもつ。Ａｌ2 Ｏ3 に換算
したときの酸化アルミニウムの含有量は、誘電体材料全
体の１重量％以下とすることが好ましい。酸化アルミニ
ウムの含有量が多すぎると、逆に焼結を阻害するという
問題を生じる。Aluminum oxide may be contained in the dielectric layer. Aluminum oxide has a function of enabling sintering at a relatively low temperature. The content of aluminum oxide when converted to Al 2 O 3 is preferably 1% by weight or less based on the entire dielectric material. If the content of aluminum oxide is too large, on the contrary, there arises a problem of inhibiting sintering.
【００２５】本発明において誘電体層は、いわゆるコア
−シェル構造となっている。すなわち、高誘電率相の結
晶粒（コア）の周囲を低誘電率相の結晶粒界（シェル）
が取り囲む構造となっている。コアには、通常、Ｂａ
Ｏ、ＴｉＯ2 、ＭｎＯ、ＣａＯなどが含まれ、シェルに
は、通常、ＣａＯ、ＴｉＯ2 、ＢａＯ、ＳｉＯ2 、Ｍｎ
Ｏ、ＭｇＯ、Ｙ2 Ｏ3 などが含まれる。In the present invention, the dielectric layer has a so-called core-shell structure. In other words, the crystal grain boundary (shell) of the low dielectric constant phase is surrounded by the crystal grain (core) of the high dielectric constant phase.
Has a structure that surrounds. The core is usually Ba
O, TiO 2 , MnO, CaO, etc. are included, and the shell is usually CaO, TiO 2 , BaO, SiO 2 , Mn.
O, MgO, Y 2 O 3 and the like are included.
【００２６】誘電体層の平均結晶粒径は特に限定されな
いが、上記組成とすることにより微細な結晶粒が得ら
れ、通常、平均結晶粒径は０．２〜０．７μm 程度とな
る。また、シェルの平均幅は、０．０２〜０．２μm 程
度である。The average crystal grain size of the dielectric layer is not particularly limited, but fine crystal grains can be obtained with the above composition, and the average crystal grain size is usually about 0.2 to 0.7 μm. The average width of the shell is about 0.02 to 0.2 μm.
【００２７】誘電体層のキュリー温度は、適用される規
格に応じて組成を選択することにより適宜設定すること
ができるが、一般に８５℃以上、通常、１２０〜１３５
℃程度とする。The Curie temperature of the dielectric layer can be appropriately set by selecting the composition according to the applied standard, but is generally 85 ° C. or higher, usually 120 to 135.
Approximately ℃.
【００２８】誘電体層の一層あたりの厚さは、１００μ
m 以下、特に５０μm 以下、さらには２〜２０μm 程度
とする。本発明は、このような薄層化した誘電体層を有
する積層型セラミックチップコンデンサの容量の経時変
化防止に有効である。なお、誘電体層の積層数は、通常
２〜２００程度とする。The thickness of each dielectric layer is 100 μm.
m or less, especially 50 μm or less, and further about 2 to 20 μm. The present invention is effective in preventing the change with time of the capacitance of the multilayer ceramic chip capacitor having such a thinned dielectric layer. The number of laminated dielectric layers is usually about 2 to 200.
【００２９】＜内部電極層３＞内部電極層３に含有され
る導電材は特に限定されないが、誘電体層２構成材料が
耐還元性を有するため、卑金属を用いることができる。
導電材として用いる卑金属としては、ＮｉまたはＮｉ合
金が好ましい。Ｎｉ合金としては、Ｍｎ、Ｃｒ、Ｃｏお
よびＡｌから選択される１種以上の元素とＮｉとの合金
が好ましく、合金中のＮｉ含有量は９５重量％以上であ
ることが好ましい。<Internal Electrode Layer 3> The conductive material contained in the internal electrode layer 3 is not particularly limited, but a base metal can be used because the material constituting the dielectric layer 2 has reduction resistance.
As the base metal used as the conductive material, Ni or Ni alloy is preferable. The Ni alloy is preferably an alloy of Ni with one or more elements selected from Mn, Cr, Co and Al, and the Ni content in the alloy is preferably 95% by weight or more.
【００３０】なお、ＮｉまたはＮｉ合金中には、Ｐ等の
各種微量成分が０．１重量％程度以下含まれていてもよ
い。The Ni or Ni alloy may contain various trace components such as P in an amount of about 0.1% by weight or less.
【００３１】内部電極層の厚さは用途等に応じて適宜決
定されればよいが、通常、１〜５μm 、特に２〜３μm
程度であることが好ましい。The thickness of the internal electrode layer may be appropriately determined according to the application, etc., but is usually 1 to 5 μm, particularly 2 to 3 μm.
It is preferably about the same.
【００３２】＜外部電極４＞外部電極４に含有される導
電材は特に限定されないが、本発明では安価なＮｉ、Ｃ
ｕや、これらの合金を用いることができる。<External Electrode 4> The conductive material contained in the external electrode 4 is not particularly limited, but in the present invention, inexpensive Ni and C are used.
u and these alloys can be used.
【００３３】外部電極の厚さは用途等に応じて適宜決定
されればよいが、通常、１０〜５０μm 程度であること
が好ましい。The thickness of the external electrode may be appropriately determined according to the application, etc., but normally it is preferably about 10 to 50 μm.
【００３４】［積層型セラミックチップコンデンサの製
造方法］本発明の積層型セラミックチップコンデンサ
は、ペーストを用いた通常の印刷法やシート法によりグ
リーンチップを作製し、これを焼成した後、外部電極を
印刷ないし転写して焼成することにより製造される。[Manufacturing Method of Multilayer Ceramic Chip Capacitor] In the multilayer ceramic chip capacitor of the present invention, a green chip is produced by an ordinary printing method using a paste or a sheet method, and after firing the green chip, an external electrode is formed. It is manufactured by printing or transferring and firing.
【００３５】＜誘電体層用ペースト＞誘電体層用ペース
トは、誘電体原料と有機ビヒクルとを混練して製造され
る。<Dielectric Layer Paste> The dielectric layer paste is produced by kneading a dielectric material and an organic vehicle.
【００３６】誘電体原料には、上記した複合酸化物や酸
化物の混合物を用いることができるが、その他、焼成に
より上記した複合酸化物や酸化物となる各種化合物、例
えば、炭酸塩、シュウ酸塩、硝酸塩、水酸化物、有機金
属化合物等から適宜選択し、混合して用いることができ
る。誘電体原料中の各化合物の含有量は、焼成後に上記
した誘電体層の組成となるように決定すればよい。As the dielectric material, the above-mentioned composite oxide or a mixture of oxides can be used. In addition, various compounds such as carbonate, oxalic acid which become the above-mentioned composite oxide or oxide by firing. A salt, a nitrate, a hydroxide, an organometallic compound or the like can be appropriately selected and mixed and used. The content of each compound in the dielectric material may be determined so that the composition of the dielectric layer described above is obtained after firing.
【００３７】誘電体原料は、通常、平均粒子径０．１〜
１μm 程度の粉末として用いられる。The dielectric material usually has an average particle size of 0.1 to 10.
It is used as a powder of about 1 μm.
【００３８】有機ビヒクルとは、バインダを有機溶剤中
に溶解したものである。有機ビヒクルに用いるバインダ
は特に限定されず、エチルセルロース等の通常の各種バ
インダから適宜選択すればよい。また、用いる有機溶剤
も特に限定されず、印刷法やシート法など、利用する方
法に応じて、テルピネオール、ブチルカルビトール、ア
セトン、トルエン等の各種有機溶剤から適宜選択すれば
よい。The organic vehicle is a binder dissolved in an organic solvent. The binder used for the organic vehicle is not particularly limited, and may be appropriately selected from various ordinary binders such as ethyl cellulose. The organic solvent used is also not particularly limited, and may be appropriately selected from various organic solvents such as terpineol, butyl carbitol, acetone, and toluene according to the method to be used such as the printing method and the sheet method.
【００３９】＜内部電極層用ペースト＞内部電極層用ペ
ーストは、上記した各種導電性金属や合金からなる導電
材、あるいは焼成後に上記した導電材となる各種酸化
物、有機金属化合物、レジネート等と、上記した有機ビ
ヒクルとを混練して調製する。<Internal Electrode Layer Paste> The internal electrode layer paste is a conductive material made of the above-mentioned various conductive metals or alloys, or various oxides, organometallic compounds, resinates, etc. which become the above-mentioned conductive material after firing. It is prepared by kneading the above-mentioned organic vehicle.
【００４０】＜外部電極用ペースト＞外部電極用ペース
トは、上記した内部電極層用ペーストと同様にして調製
すればよい。<External Electrode Paste> The external electrode paste may be prepared in the same manner as the above internal electrode layer paste.
【００４１】＜有機ビヒクル含有量＞上記した各ペース
ト中の有機ビヒクルの含有量に特に制限はなく、通常の
含有量、例えば、バインダは１〜５重量％程度、溶剤は
１０〜５０重量％程度とすればよい。また、各ペースト
中には、必要に応じて各種分散剤、可塑剤、誘電体、絶
縁体等から選択される添加物が含有されていてもよい。
これらの総含有量は、１０重量％以下とすることが好ま
しい。<Organic Vehicle Content> The content of the organic vehicle in each of the above-mentioned pastes is not particularly limited, and the usual content is, for example, about 1 to 5% by weight of the binder and about 10 to 50% by weight of the solvent. And it is sufficient. In addition, each paste may contain additives selected from various dispersants, plasticizers, dielectrics, insulators and the like, if necessary.
The total content of these is preferably 10% by weight or less.
【００４２】＜グリーンチップ作製＞印刷法を用いる場
合、誘電体層用ペーストおよび内部電極層用ペースト
を、ＰＥＴ等の基板上に積層印刷し、所定形状に切断し
た後、基板から剥離してグリーンチップとする。<Preparation of Green Chip> When the printing method is used, the dielectric layer paste and the internal electrode layer paste are laminated and printed on a substrate such as PET, cut into a predetermined shape, and then peeled from the substrate to be green. Use as chips.
【００４３】また、シート法を用いる場合、誘電体層用
ペーストを用いてグリーンシートを形成し、この上に内
部電極層用ペーストを印刷した後、これらを積層してグ
リーンチップとする。When the sheet method is used, a dielectric layer paste is used to form a green sheet, an internal electrode layer paste is printed on the green sheet, and these are laminated to form a green chip.
【００４４】＜脱バインダ処理＞焼成前に行なわれる脱
バインダ処理は、通常の条件で行えばよいが、内部電極
層の導電材にＮｉやＮｉ合金等の卑金属を用いる場合、
特に下記の条件で行うことが好ましい。 昇温速度：５〜３００℃／時間、特に１０〜１００℃／
時間 保持温度：２００〜４００℃、特に２５０〜３００℃ 温度保持時間：０．５〜２４時間、特に５〜２０時間 雰囲気：空気中<Binder removal treatment> The binder removal treatment performed before firing may be performed under normal conditions. When a base metal such as Ni or Ni alloy is used as the conductive material of the internal electrode layers,
It is particularly preferable to carry out under the following conditions. Temperature rising rate: 5 to 300 ° C / hour, especially 10 to 100 ° C /
Time Holding temperature: 200 to 400 ° C, especially 250 to 300 ° C Temperature holding time: 0.5 to 24 hours, especially 5 to 20 hours Atmosphere: In air
【００４５】＜焼成＞グリーンチップ焼成時の雰囲気
は、内部電極層用ペースト中の導電材の種類に応じて適
宜決定されればよいが、導電材としてＮｉやＮｉ合金等
の卑金属を用いる場合、焼成雰囲気中の酸素分圧は、１
０-8〜１０-12 気圧とすることが好ましい。酸素分圧が
前記範囲未満であると、内部電極層の導電材が異常焼結
を起こし、途切れてしまうことがある。また、酸素分圧
が前記範囲を超えると、内部電極層が酸化する傾向にあ
る。<Firing> The atmosphere during firing of the green chip may be appropriately determined according to the type of conductive material in the internal electrode layer paste. When a base metal such as Ni or Ni alloy is used as the conductive material, The oxygen partial pressure in the firing atmosphere is 1
The pressure is preferably 0 -8 to 10 -12 atm. If the oxygen partial pressure is less than the above range, the conductive material of the internal electrode layers may abnormally sinter and be interrupted. When the oxygen partial pressure exceeds the above range, the internal electrode layers tend to be oxidized.
【００４６】また、焼成時の保持温度は、１２００〜１
４００℃、特に１２５０〜１３００℃とすることが好ま
しい。保持温度が前記範囲未満であると緻密化が不十分
であり、前記範囲を超えると直流電界印加時の容量の経
時変化が大きくなる。The holding temperature during firing is 1200 to 1
The temperature is preferably 400 ° C., particularly 1250 to 1300 ° C. If the holding temperature is less than the above range, the densification will be insufficient, and if the holding temperature exceeds the above range, the change with time of the capacitance when a DC electric field is applied becomes large.
【００４７】上記条件以外の各種条件は、下記のように
することが好ましい。 昇温速度：５０〜５００℃／時間、特に２００〜３００
℃／時間 温度保持時間：０．５〜８時間、特に１〜３時間 冷却速度：５０〜５００℃／時間、特に２００〜３００
℃／時間 焼成雰囲気は還元性雰囲気とすることが好ましく、雰囲
気ガスとしては、例えば、Ｎ2 とＨ2 との混合ガスを加
湿して用いることが好ましい。Various conditions other than the above conditions are preferably as follows. Temperature rising rate: 50 to 500 ° C./hour, especially 200 to 300
° C / hour Temperature holding time: 0.5 to 8 hours, especially 1 to 3 hours Cooling rate: 50 to 500 ° C / hour, especially 200 to 300
C./hour The firing atmosphere is preferably a reducing atmosphere, and as the atmosphere gas, for example, a mixed gas of N 2 and H 2 is preferably humidified and used.
【００４８】＜アニール＞還元性雰囲気中で焼成した場
合、コンデンサチップ体にはアニールが施されることが
好ましい。アニールは、誘電体層を再酸化するための処
理であり、これによりＩＲ加速寿命を著しく長くするこ
とができる。<Annealing> When firing in a reducing atmosphere, the capacitor chip body is preferably annealed. Annealing is a process for reoxidizing the dielectric layer, which can significantly increase the IR accelerated life.
【００４９】アニール雰囲気中の酸素分圧は、１０-6気
圧以上、特に１０-5〜１０-4気圧とすることが好まし
い。酸素分圧が前記範囲未満であると誘電体層の再酸化
が困難であり、前記範囲を超えると内部電極層が酸化す
る傾向にある。The oxygen partial pressure in the annealing atmosphere is preferably 10 -6 atm or more, and particularly preferably 10 -5 to 10 -4 atm. If the oxygen partial pressure is less than the above range, it is difficult to reoxidize the dielectric layer, and if it exceeds the above range, the internal electrode layers tend to be oxidized.
【００５０】アニールの際の保持温度は、１１００℃以
下、特に５００〜１０００℃とすることが好ましい。保
持温度が前記範囲未満であると誘電体層の酸化が不十分
となって寿命が短くなる傾向にあり、前記範囲を超える
と内部電極層が酸化し、容量が低下するだけでなく、誘
電体素地と反応してしまい、寿命も短くなる傾向にあ
る。なお、アニールは昇温および降温だけから構成して
もよい。この場合、温度保持時間は零であり、保持温度
は最高温度と同義である。The holding temperature during annealing is preferably 1100 ° C. or lower, particularly 500 to 1000 ° C. If the holding temperature is less than the above range, oxidation of the dielectric layer tends to be insufficient and the life tends to be shortened. If the holding temperature exceeds the above range, the internal electrode layer is oxidized and the capacity is reduced, and the dielectric It reacts with the base material and tends to shorten the life. It should be noted that the annealing may be constituted only by raising and lowering the temperature. In this case, the temperature holding time is zero and the holding temperature is synonymous with the maximum temperature.
【００５１】上記条件以外の各種条件は下記のようにす
ることが好ましい。 温度保持時間：０〜２０時間、特に６〜１０時間 冷却速度：５０〜５００℃／時間、特に１００〜３００
℃／時間 雰囲気用ガスには、加湿したＮ2 ガス等を用いることが
好ましい。Various conditions other than the above conditions are preferably as follows. Temperature holding time: 0 to 20 hours, especially 6 to 10 hours Cooling rate: 50 to 500 ° C./hour, especially 100 to 300
C./hour It is preferable to use a humidified N 2 gas or the like as the atmosphere gas.
【００５２】なお、上記した脱バインダ処理、焼成およ
びアニールにおいて、Ｎ2 ガスや混合ガス等を加湿する
には、例えばウェッター等を使用すればよい。この場
合、水温は５〜７５℃程度が好ましい。In the above binder removal processing, firing and annealing, for example, a wetter or the like may be used to moisten the N 2 gas or the mixed gas. In this case, the water temperature is preferably about 5 to 75 ° C.
【００５３】脱バインダ処理、焼成およびアニールは、
連続して行なっても、独立に行なってもよい。The binder removal processing, firing and annealing are
It may be carried out continuously or independently.
【００５４】これらを連続して行なう場合、脱バインダ
処理後、冷却せずに雰囲気を変更し、続いて焼成の際の
保持温度まで昇温して焼成を行ない、次いで冷却し、ア
ニールの保持温度に達したときに雰囲気を変更してアニ
ールを行なうことが好ましい。In the case of continuously performing these, after the binder removal treatment, the atmosphere is changed without cooling, the temperature is raised to the holding temperature at the time of firing, firing is performed, and then the temperature is kept at annealing. It is preferable to anneal by changing the atmosphere when the temperature reaches.
【００５５】また、これらを独立して行なう場合、焼成
に際しては、脱バインダ処理時の保持温度までＮ2 ガス
あるいは加湿したＮ2 ガス雰囲気下で昇温した後、雰囲
気を変更してさらに昇温を続けることが好ましく、アニ
ール時の保持温度まで冷却した後は、再びＮ2 ガスある
いは加湿したＮ2 ガス雰囲気に変更して冷却を続けるこ
とが好ましい。また、アニールに際しては、Ｎ2 ガス雰
囲気下で保持温度まで昇温した後、雰囲気を変更しても
よく、アニールの全工程を加湿したＮ2 ガス雰囲気とし
てもよい。In the case where these are carried out independently, upon firing, the temperature is raised up to the holding temperature at the time of binder removal treatment in an atmosphere of N 2 gas or humidified N 2 gas, and then the atmosphere is changed to further raise the temperature. It is preferable to continue the above, and after cooling to the holding temperature at the time of annealing, it is preferable to change to N 2 gas or a humidified N 2 gas atmosphere again and continue cooling. In annealing, the temperature may be raised to the holding temperature in an N 2 gas atmosphere and then the atmosphere may be changed, or the entire annealing process may be performed in a humidified N 2 gas atmosphere.
【００５６】＜外部電極形成＞上記のようにして得られ
たコンデンサチップ体に、例えばバレル研磨やサンドブ
ラストなどにより端面研磨を施し、外部電極用ペースト
を印刷ないし転写して焼成し、外部電極４を形成する。
外部電極用ペーストの焼成条件は、例えば、６００〜８
００℃にて１０分間〜１時間程度とすることが好まし
い。<Formation of External Electrodes> The capacitor chip body obtained as described above is subjected to end face polishing by, for example, barrel polishing or sandblasting, and the external electrode paste is printed or transferred and baked to form the external electrodes 4. Form.
The firing conditions of the external electrode paste are, for example, 600 to 8
It is preferable to set the temperature to 00 ° C. for about 10 minutes to 1 hour.
【００５７】そして、必要に応じ、外部電極４表面に、
めっき等により被覆層を形成する。Then, if necessary, on the surface of the external electrode 4,
A coating layer is formed by plating or the like.
【００５８】このようにして製造された本発明の積層型
セラミックチップコンデンサは、ハンダ付等によりプリ
ント基板上などに実装され、各種電子機器等に使用され
る。The thus-fabricated multilayer ceramic chip capacitor of the present invention is mounted on a printed circuit board or the like by soldering or the like and used in various electronic devices or the like.
【００５９】そして、本発明の積層型セラミックチップ
コンデンサの誘電体層には、使用時に、０．０２V/μm
以上、 特に０．２V/μm 以上、さらには０．５V/μm 以
上、一般に５V/μm 程度以下の直流電界と、通常、これ
に重畳する交流成分とが印加されるが、このような直流
電界を負荷しても、容量の経時変化は極めて少ないもの
である。The dielectric layer of the multilayer ceramic chip capacitor of the present invention contains 0.02 V / μm when used.
Above, in particular, 0.2 V / μm or more, more preferably 0.5 V / μm or more, generally 5 V / μm or less, and an AC component that is usually superimposed on this are applied. Even if a load is applied, the change in capacity with time is extremely small.
【００６０】[0060]
【実施例】以下、本発明の具体的実施例を挙げ、本発明
をさらに詳細に説明する。EXAMPLES Hereinafter, the present invention will be described in more detail with reference to specific examples of the present invention.
【００６１】下記の各ペーストを調製した。誘電体層用ペースト 粒径０．１〜１μm のＢａＴｉＯ3 、（ＭｇＣＯ3 ）4
・Ｍｇ（ＯＨ）2 ・５Ｈ2 Ｏ、ＭｎＣＯ3 、（Ｂａ0.5
Ｃａ0.5 ）ＳｉＯ3 、Ｙ2 Ｏ3 から選択した材料粉末を
ボールミルにより１６時間湿式混合し、次いでスプレー
ドライヤーで乾燥させて、誘電体原料とした。各粉末の
混合比率を変えて、複数の誘電体原料を作製した。The following pastes were prepared. Dielectric layer paste BaTiO 3 , (MgCO 3 ) 4 having a particle size of 0.1 to 1 μm
· Mg (OH) 2 · 5H 2 O, MnCO 3, (Ba 0.5
A material powder selected from Ca 0.5 ) SiO 3 and Y 2 O 3 was wet mixed by a ball mill for 16 hours and then dried by a spray dryer to obtain a dielectric material. A plurality of dielectric materials were produced by changing the mixing ratio of each powder.
【００６２】各誘電体原料１００重量部と、アクリル樹
脂４．８重量部、塩化メチレン４０重量部、トリクロロ
エタン２０重量部、ミネラルスピリット６重量部および
アセトン４重量部とをボールミルで混合してペースト化
した。100 parts by weight of each dielectric material, 4.8 parts by weight of acrylic resin, 40 parts by weight of methylene chloride, 20 parts by weight of trichloroethane, 6 parts by weight of mineral spirit and 4 parts by weight of acetone were mixed by a ball mill to form a paste. did.
【００６３】内部電極層用ペースト 平均粒径０．８μm のＮｉ粒子１００重量部と、有機ビ
ヒクル（エチルセルロース樹脂８重量部をブチルカルビ
トール９２重量部に溶解したもの）４０重量部およびブ
チルカルビトール１０重量部とを３本ロールにより混練
し、ペースト化した。 Internal electrode layer paste : 100 parts by weight of Ni particles having an average particle size of 0.8 μm, 40 parts by weight of an organic vehicle (8 parts by weight of ethyl cellulose resin dissolved in 92 parts by weight of butyl carbitol) and 10 parts of butyl carbitol. 3 parts by weight were kneaded with 3 parts by weight to form a paste.
【００６４】外部電極用ペースト 平均粒径０．５μm のＣｕ粒子１００重量部と、有機ビ
ヒクル（エチルセルロース樹脂８重量部をブチルカルビ
トール９２重量部に溶解したもの）３５重量部およびブ
チルカルビトール７重量部とを混練し、ペースト化し
た。100 parts by weight of Cu particles having an average particle diameter of 0.5 μm of external electrode paste, 35 parts by weight of organic vehicle (8 parts by weight of ethyl cellulose resin dissolved in 92 parts by weight of butyl carbitol) and 7 parts by weight of butyl carbitol. The parts were kneaded to form a paste.
【００６５】上記各誘電体層用ペーストおよび上記内部
電極層用ペーストを用い、図１に示される構成の積層型
セラミックコンデンサを作製した。Using each of the above dielectric layer pastes and the above internal electrode layer pastes, a laminated ceramic capacitor having the structure shown in FIG. 1 was produced.
【００６６】まず、誘電体層用ペーストを用いてＰＥＴ
フィルム上にグリーンシートを作製し、この上に内部電
極層用ペーストを印刷した。次いで、ＰＥＴフィルムか
らシートを剥離して積層し、加圧接着してグリーンチッ
プを得た。積層数は４層とした。First, using a dielectric layer paste, PET
A green sheet was prepared on the film, and the internal electrode layer paste was printed on the green sheet. Next, the sheets were peeled from the PET film, laminated, and pressure-bonded to obtain a green chip. The number of layers was four.
【００６７】次いでグリーンチップを所定サイズに切断
し、脱バインダ処理、焼成およびアニールを下記の条件
にて連続的に行ない、コンデンサチップ体を作製した。Next, the green chip was cut into a predetermined size, and binder removal treatment, firing and annealing were continuously performed under the following conditions to produce a capacitor chip body.
【００６８】脱バインダ処理 昇温速度：１５℃／時間 保持温度：２８０℃ 温度保持時間：８時間 雰囲気ガス：空気中 Binder removal temperature rising rate: 15 ° C./hour Holding temperature: 280 ° C. Temperature holding time: 8 hours Atmosphere gas: In air
【００６９】焼成 昇温速度：２００℃／時間 保持温度：１３００℃ 温度保持時間：２時間 冷却速度：３００℃／時間 雰囲気ガス：加湿したＮ2 とＨ2 との混合ガス 酸素分圧：１０-9気圧[0069] baking Atsushi Nobori rate: 200 ° C. / Time holding temperature: 1300 ° C. Temperature holding time: 2 hours Cooling rate: 300 ° C. / Time Atmosphere gas: wet mixed gas of oxygen partial pressure of N 2 and H 2: 10 - 9 bar
【００７０】アニール 保持温度：９００℃ 温度保持時間：９時間 冷却速度：３００℃／時間 雰囲気ガス：加湿したＮ2 ガス 酸素分圧：１０-5気圧 Annealing holding temperature: 900 ° C. Temperature holding time: 9 hours Cooling rate: 300 ° C./hour Atmosphere gas: humidified N 2 gas Oxygen partial pressure: 10 −5 atm
【００７１】なお、それぞれの雰囲気ガスの加湿にはウ
ェッターを用い、水温は３５℃とした。A wetter was used to humidify each atmosphere gas, and the water temperature was set to 35 ° C.
【００７２】得られたコンデンサチップ体の端面をサン
ドブラストにて研磨した後、上記外部電極用ペーストを
前記端面に転写し、Ｎ2 ＋Ｈ2 雰囲気中で８００℃にて
１０分間焼成して外部電極を形成し、積層型セラミック
チップコンデンササンプルを得た。After polishing the end faces of the obtained capacitor chip body by sandblasting, the above external electrode paste was transferred to the above end faces and baked at 800 ° C. for 10 minutes in an N 2 + H 2 atmosphere to form external electrodes. Then, a multilayer ceramic chip capacitor sample was obtained.
【００７３】このようにして製造した各サンプルのサイ
ズは、３．２mm×１．６mm×１．２mmであり、誘電体層
の厚さは１５μm 、内部電極層の厚さは２．５μm であ
った。The size of each sample manufactured in this manner was 3.2 mm × 1.6 mm × 1.2 mm, the thickness of the dielectric layer was 15 μm, and the thickness of the internal electrode layer was 2.5 μm. It was
【００７４】各サンプルの誘電体層の組成を、下記表１
に示す。これらの組成は、前述した基準に従って算出し
た。なお、表１中の（Ｂａ，Ｃａ）ＳｉＯ3 とは、（Ｂ
ａ0. 5 Ｃａ0.5 ）ＳｉＯ3 である。The composition of the dielectric layer of each sample is shown in Table 1 below.
Shown in. These compositions were calculated according to the above-mentioned criteria. In addition, (Ba, Ca) SiO 3 in Table 1 means (B
a 0. 5 Ca 0.5) is SiO 3.
【００７５】各サンプルについて、下記の測定を行なっ
た。結果を表１に示す。The following measurements were carried out for each sample. The results are shown in Table 1.
【００７６】容量の温度特性 Ｘ７Ｒ特性：ＬＣＲメータにより、−５５〜１２５℃に
ついて測定電圧１V で容量を測定し、容量変化率が±１
５％以内（基準温度２５℃）を満足するかどうかを調べ
た。満足する場合を○、満足しない場合を×とした。 Capacitance temperature characteristic X7R characteristic: The capacity was measured with an LCR meter at a measuring voltage of 1 V at −55 to 125 ° C., and the capacity change rate was ± 1.
It was examined whether or not the content was within 5% (reference temperature 25 ° C.). When satisfied, it was evaluated as ○, and when not satisfied, it was evaluated as ×.
【００７７】直流電界下での容量の経時変化 誘電体層の厚さ１μm あたり１．０６V の直流電界（サ
ンプルへの印加電圧１６V ）を４０℃にて６６時間印加
し、次いで、無負荷状態で室温にて２４時間放置した
後、容量を測定し、直流電界印加前の容量Ｃ0 （初期容
量）からの変化量ΔＣを求めて、変化率ΔＣ／Ｃ0 を算
出した。なお、容量は上記条件にて測定した。 Change of capacity with time under DC electric field A DC electric field of 1.06 V per 1 μm thickness of the dielectric layer (voltage applied to the sample: 16 V) was applied at 40 ° C. for 66 hours, and then, under no load condition. After being left at room temperature for 24 hours, the capacitance was measured, the change amount ΔC from the capacitance C 0 (initial capacitance) before application of a DC electric field was determined, and the change rate ΔC / C 0 was calculated. The capacity was measured under the above conditions.
【００７８】絶縁抵抗ＩＲの加速寿命 １８０℃にて１０V/μm の電界下で加速試験を行ない、
抵抗（ＩＲ）が２×１０5 Ω以下になるまでの時間を寿
命時間とした。 The accelerated life of the insulation resistance IR is 180 ° C. and an acceleration test is performed under an electric field of 10 V / μm.
The time until the resistance (IR) became 2 × 10 5 Ω or less was defined as the life time.
【００７９】比誘電率εs ２５℃における比誘電率を測定した。 Specific permittivity ε s The specific permittivity at 25 ° C. was measured.
【００８０】[0080]
【表１】 [Table 1]
【００８１】表１に示される結果から、本発明の効果が
明らかである。すなわち、誘電体層の組成が本発明の範
囲内であるサンプルでは、Ｘ７Ｒ特性を満足し、かつ、
直流電界下での容量の経時変化率が１０％以下と極めて
低く、また、加速試験における絶縁抵抗ＩＲの寿命が長
い。そして、Ｙ2 Ｏ3 の添加により、ＩＲ加速寿命が著
しく向上することがわかる。また、表１の本発明サンプ
ルは、静電容量の温度特性がＢ特性［−２５〜８５℃で
容量変化率±１０％以内（基準温度２０℃）］も満足し
ていた。From the results shown in Table 1, the effect of the present invention is clear. That is, in the sample in which the composition of the dielectric layer is within the range of the present invention, the X7R characteristic is satisfied, and
The rate of change of the capacitance with time under a DC electric field is extremely low at 10% or less, and the life of the insulation resistance IR in the acceleration test is long. Then, it is found that the IR accelerated life is remarkably improved by the addition of Y 2 O 3 . Further, the samples of the present invention in Table 1 also satisfied the temperature characteristic of the electrostatic capacity as the B characteristic [capacity change rate within ± 10% at −25 to 85 ° C. (reference temperature 20 ° C.)].
【００８２】本発明のサンプルNo. １および比較例のサ
ンプルNo. １６の誘電体層断面の走査型電子顕微鏡写真
を、それぞれ図２および図３に示す。これらの写真は、
断面を鏡面研磨し、フッ酸−硝酸の混合水溶液によりエ
ッチングした後に撮影した。比較例であるサンプルNo.
１６（図３）では平均結晶粒径が約１μm 、結晶粒界の
平均幅が約０．２μm であるが、本発明のサンプルNo.
１（図２）では平均結晶粒径が約０．５μm 、結晶粒界
の平均幅が約０．２μm と細かい。なお、表１に示され
る他の比較サンプルおよび本発明サンプルについても、
同様な関係がみられた。Scanning electron micrographs of the dielectric layer cross sections of sample No. 1 of the present invention and sample No. 16 of the comparative example are shown in FIGS. 2 and 3, respectively. These pictures are
The cross-section was mirror-polished and then photographed after etching with a mixed aqueous solution of hydrofluoric acid-nitric acid. Sample No. which is a comparative example.
In Fig. 16 (Fig. 3), the average crystal grain size is about 1 µm and the average grain boundary width is about 0.2 µm.
In Fig. 1 (Fig. 2), the average grain size is about 0.5 µm and the average grain boundary width is about 0.2 µm. The other comparative samples and the sample of the present invention shown in Table 1 were also
A similar relationship was seen.
【００８３】また、比較例のサンプルNo. １６の誘電体
層の透過型電子顕微鏡写真を、上記直流電界印加前およ
び印加後に撮影した。印加前の写真を図４に、印加後の
写真を図５にそれぞれ示す。図４および図５から、直流
電界の印加によりドメインが減少していることがわか
る。Further, transmission electron micrographs of the dielectric layer of sample No. 16 of the comparative example were taken before and after the application of the DC electric field. A photograph before application is shown in FIG. 4, and a photograph after application is shown in FIG. From FIGS. 4 and 5, it can be seen that the domain is reduced by the application of the DC electric field.
【００８４】[0084]
【発明の効果】本発明では、誘電体層を所定の組成とす
ることにより、容量の温度特性に関するＸ７Ｒ特性およ
びＢ特性を満足することができ、かつ、直流電界下での
容量の経時変化が小さく、また、絶縁抵抗ＩＲの加速寿
命が長い積層型セラミックチップコンデンサを実現する
ことができる。According to the present invention, by making the dielectric layer have a predetermined composition, the X7R characteristic and the B characteristic relating to the temperature characteristic of the capacitance can be satisfied, and the variation of the capacitance with time under a DC electric field can be improved. It is possible to realize a multilayer ceramic chip capacitor that is small and has a long accelerated life of the insulation resistance IR.
【図１】本発明の積層型セラミックチップコンデンサの
構成例を示す断面図である。FIG. 1 is a cross-sectional view showing a configuration example of a multilayer ceramic chip capacitor of the present invention.
【図２】粒子構造を示す図面代用写真であって、本発明
の積層型セラミックチップコンデンサの誘電体層断面の
走査型電子顕微鏡写真である。FIG. 2 is a drawing-substitute photograph showing a particle structure, which is a scanning electron microscope photograph of a cross section of a dielectric layer of the multilayer ceramic chip capacitor of the present invention.
【図３】粒子構造を示す図面代用写真であって、従来の
積層型セラミックチップコンデンサの誘電体層断面の走
査型電子顕微鏡写真である。FIG. 3 is a drawing-substituting photograph showing a particle structure, which is a scanning electron microscope photograph of a cross section of a dielectric layer of a conventional multilayer ceramic chip capacitor.
【図４】粒子構造を示す図面代用写真であって、積層型
セラミックチップコンデンサの誘電体層の透過型電子顕
微鏡写真である。FIG. 4 is a drawing-substitute photograph showing a particle structure, which is a transmission electron microscope photograph of a dielectric layer of a multilayer ceramic chip capacitor.
【図５】粒子構造を示す図面代用写真であって、直流電
界印加後の積層型セラミックチップコンデンサの誘電体
層の透過型電子顕微鏡写真である。FIG. 5 is a drawing-substitute photograph showing a particle structure, which is a transmission electron microscope photograph of a dielectric layer of a multilayer ceramic chip capacitor after application of a DC electric field.
１ 積層型セラミックチップコンデンサ １０ コンデンサチップ体 ２ 誘電体層 ３ 内部電極層 ４ 外部電極 1 Multilayer Ceramic Chip Capacitor 10 Capacitor Chip Body 2 Dielectric Layer 3 Internal Electrode Layer 4 External Electrode
─────────────────────────────────────────────────────
─────────────────────────────────────────────────── ───
【手続補正書】[Procedure amendment]
【提出日】平成５年６月２３日[Submission date] June 23, 1993
【手続補正１】[Procedure Amendment 1]
【補正対象書類名】明細書[Document name to be amended] Statement
【補正対象項目名】００２４[Name of item to be corrected] 0024
【補正方法】変更[Correction method] Change
【補正内容】[Correction content]
【００２４】誘電体層中には、酸化アルミニウムが含有
されていてもよい。酸化アルミニウムは比較的低温での
焼結を可能にする作用をもつ。Ａｌ２Ｏ３に換算したと
きの酸化アルミニウムの含有量は、誘電体材料全体の１
重量％以下とすることが好ましい。酸化アルミニウムの
含有量が多すぎると比誘電率が著しく低下してしまい、
同時にＩＲ加速寿命も短くなってしまう。Aluminum oxide may be contained in the dielectric layer. Aluminum oxide has a function of enabling sintering at a relatively low temperature. The content of aluminum oxide when converted to Al 2 O 3 is 1 of the whole dielectric material.
It is preferable to set the content to be not more than weight%. If the content of aluminum oxide is too large, the relative dielectric constant will decrease significantly,
At the same time, the IR accelerated life also becomes shorter.
【手続補正２】[Procedure Amendment 2]
【補正対象書類名】明細書[Document name to be amended] Statement
【補正対象項目名】００２５[Name of item to be corrected] 0025
【補正方法】変更[Correction method] Change
【補正内容】[Correction content]
【００２５】本発明において誘電体層は、いわゆるコア
ーシェル構造となっている。すなわち、ペロブスカイト
構造を有する高誘電率相の結晶粒（コア）の周囲を低誘
電率相の結晶粒界（シェル）が取り囲む構造となってい
る。コアには、通常、ＢａＯ、ＴｉＯ２、ＭｎＯ、Ｃａ
Ｏなどが含まれ、シエルには、通常、ＣａＯ、Ｔｉ
Ｏ２、ＢａＯ、ＳｉＯ２、ＭｎＯ、ＭｇＯ、Ｙ２Ｏ３な
どが含まれる。In the present invention, the dielectric layer has a so-called core-shell structure. That is, the crystal grain boundary (shell) of the low dielectric constant phase surrounds the crystal grain (core) of the high dielectric constant phase having the perovskite structure. The core is usually made of BaO, TiO 2 , MnO, Ca.
O, etc. are included, and the shell is usually CaO, Ti
O 2 , BaO, SiO 2 , MnO, MgO, Y 2 O 3 and the like are included.
【手続補正３】[Procedure 3]
【補正対象書類名】明細書[Document name to be amended] Statement
【補正対象項目名】００２８[Correction target item name] 0028
【補正方法】変更[Correction method] Change
【補正内容】[Correction content]
【００２８】誘電体層の一層あたりの厚さは、５０μｍ
以下、好ましくは２０μｍ程度以下とする。厚さの下限
は０．５μｍ程度、好ましくは２μｍ程度である。本発
明は、このような薄層化した誘電体層を有する積層型セ
ラミックチップコンデンサの容量の経時変化防止に有効
である。なお、誘電体層は、通常、２〜３００層程度、
好ましくは２〜２００層程度積層する。The thickness of each dielectric layer is 50 μm.
The following is preferably about 20 μm or less. The lower limit of the thickness is about 0.5 μm, preferably about 2 μm. The present invention is effective in preventing the change with time of the capacitance of the multilayer ceramic chip capacitor having such a thinned dielectric layer. The dielectric layer is usually about 2 to 300 layers,
Preferably, about 2 to 200 layers are laminated.
【手続補正４】[Procedure amendment 4]
【補正対象書類名】明細書[Document name to be amended] Statement
【補正対象項目名】００３１[Correction target item name] 0031
【補正方法】変更[Correction method] Change
【補正内容】[Correction content]
【００３１】内部電極層の厚さは用途等に応じて適宜決
定すればよいが、厚さの上限は通常５μｍ、好ましくは
２．５μｍ、厚さの下限は通常０．５μｍ、好ましくは
１μｍである。The thickness of the internal electrode layer may be appropriately determined depending on the application etc., but the upper limit of the thickness is usually 5 μm, preferably 2.5 μm, and the lower limit of the thickness is usually 0.5 μm, preferably 1 μm. is there.
【手続補正５】[Procedure Amendment 5]
【補正対象書類名】明細書[Document name to be amended] Statement
【補正対象項目名】００３７[Name of item to be corrected] 0037
【補正方法】変更[Correction method] Change
【補正内容】[Correction content]
【００３７】誘電体原料は、通常、平均粒子径０．１〜
３μｍ程度、特に０．１〜１μｍ程度の粉末として用い
られる。The dielectric material usually has an average particle size of 0.1 to 10.
It is used as a powder of about 3 μm, particularly about 0.1 to 1 μm.
【手続補正６】[Procedure correction 6]
【補正対象書類名】明細書[Document name to be amended] Statement
【補正対象項目名】００４６[Correction target item name] 0046
【補正方法】変更[Correction method] Change
【補正内容】[Correction content]
【００４６】また、焼成時の保持温度は、好ましくは１
１００〜１４００℃、より好ましくは１２００〜１４０
０℃、さらに好ましくは１２００〜１３００℃とする。
保持温度が前記範囲未満であると緻密化が不十分であ
り、前記範囲を超えると直流電界印加時の容量の経時変
化が大きくなる。The holding temperature during firing is preferably 1
100-1400 ° C, more preferably 1200-140
0 degreeC, More preferably, it is 1200-1300 degreeC.
If the holding temperature is less than the above range, the densification will be insufficient, and if the holding temperature exceeds the above range, the change with time of the capacitance when a DC electric field is applied becomes large.
【手続補正７】[Procedure Amendment 7]
【補正対象書類名】明細書[Document name to be amended] Statement
【補正対象項目名】００５６[Correction target item name] 0056
【補正方法】変更[Correction method] Change
【補正内容】[Correction content]
【００５６】＜外部電極形成＞上記のようにして得られ
たコンデンサチップ体に、例えばバレル研磨やサンドプ
ラストなどにより端面研磨を施し、外部電極用ペースト
を印刷ないし転写して焼成し、外部電極４を形成する。
外部電極用ペーストの焼成条件は、例えば、加湿したＮ
２とＨ２との混合ガス中で６００〜８００℃にて１０分
間〜１時間程度とすることが好ましい。<Formation of External Electrodes> The capacitor chip body obtained as described above is subjected to end face polishing by, for example, barrel polishing or sand plast, and the external electrode paste is printed or transferred and baked to form the external electrodes 4. To form.
The firing conditions of the external electrode paste are, for example, wet N
It is preferable to set the temperature at 600 to 800 ° C. for about 10 minutes to 1 hour in a mixed gas of 2 and H 2 .
【手続補正８】[Procedure Amendment 8]
【補正対象書類名】明細書[Document name to be amended] Statement
【補正対象項目名】００７２[Name of item to be corrected] 0072
【補正方法】変更[Correction method] Change
【補正内容】[Correction content]
【００７２】得られたコンデンサチップ体の端面をサン
ドブラストにて研磨した後、上記外部電極用ペーストを
前記端面に転写し、加湿したＮ２＋Ｈ２雰囲気中で８０
０℃にて１０分間焼成して外部電極を形成し、積層型セ
ラミックチップコンデンササンプルを得た。After polishing the end faces of the obtained capacitor chip body by sandblasting, the above-mentioned external electrode paste was transferred onto the end faces, and the paste was heated to 80 in a humidified N 2 + H 2 atmosphere.
External electrodes were formed by firing at 0 ° C. for 10 minutes to obtain a multilayer ceramic chip capacitor sample.
───────────────────────────────────────────────────── フロントページの続き (72)発明者 野村 武史 東京都中央区日本橋一丁目13番１号 ティ ーディーケイ株式会社内 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Takeshi Nomura 1-13-1 Nihonbashi, Chuo-ku, Tokyo TDC Corporation
Claims (7)
れた構成のコンデンサチップ体を有する積層型セラミッ
クチップコンデンサであって、 前記誘電体層が、主成分としてチタン酸バリウムを、副
成分として酸化マグネシウムと、酸化マンガンと、酸化
バリウムおよび酸化カルシウムから選択される少なくと
も１種と、酸化ケイ素とを含有し、チタン酸バリウムを
ＢａＴｉＯ3 に、酸化マグネシウムをＭｇＯに、酸化マ
ンガンをＭｎＯに、酸化バリウムをＢａＯに、酸化カル
シウムをＣａＯに、酸化ケイ素をＳｉＯ2 にそれぞれ換
算したとき、ＢａＴｉＯ3 １００モルに対する比率が ＭｇＯ：０．１〜３モル、 ＭｎＯ：０．０５〜１．０モル、 ＢａＯ＋ＣａＯ：２〜１２モル、 ＳｉＯ2 ：２〜１２モル であることを特徴とする積層型セラミックチップコンデ
ンサ。1. A multilayer ceramic chip capacitor having a capacitor chip body in which dielectric layers and internal electrode layers are alternately laminated, wherein the dielectric layer contains barium titanate as a main component. The composition contains magnesium oxide, manganese oxide, at least one selected from barium oxide and calcium oxide, and silicon oxide. Barium titanate is converted into BaTiO 3 , magnesium oxide is converted into MgO, and manganese oxide is converted into MnO. When barium oxide is converted to BaO, calcium oxide is converted to CaO, and silicon oxide is converted to SiO 2 , the ratio to BaTiO 3 100 mol is MgO: 0.1 to 3 mol, MnO: 0.05 to 1.0 mol. , BaO + CaO: 2 to 12 moles, SiO 2: multilayer canceller, characterized in that 2 to 12 mol Click chip capacitor.
の合計に対し、ＢａＯ、ＣａＯおよびＳｉＯ2 が（Ｂａ
x Ｃａ1-x Ｏ）y ・ＳｉＯ2 （ただし、０．３≦ｘ≦
０．７、０．９５≦ｙ≦１．０５である。）として１〜
１０重量％含有される請求項１の積層型セラミックチッ
プコンデンサ。2. The BaTiO 3 , MgO and MnO
Of BaO, CaO and SiO 2 (Ba
x Ca 1-x O) y · SiO 2 (where 0.3 ≦ x ≦
0.7 and 0.95 ≦ y ≦ 1.05. ) As 1
The multilayer ceramic chip capacitor according to claim 1, which contains 10% by weight.
れた構成のコンデンサチップ体を有する積層型セラミッ
クチップコンデンサであって、 前記誘電体層が、主成分としてチタン酸バリウムを、副
成分として酸化マグネシウムと、酸化マンガンと、酸化
イットリウムと、酸化バリウムおよび酸化カルシウムか
ら選択される少なくとも１種と、酸化ケイ素とを含有
し、チタン酸バリウムをＢａＴｉＯ3 に、酸化マグネシ
ウムをＭｇＯに、酸化マンガンをＭｎＯに、酸化イット
リウムをＹ2 Ｏ3 に、酸化バリウムをＢａＯに、酸化カ
ルシウムをＣａＯに、酸化ケイ素をＳｉＯ2 にそれぞれ
換算したとき、ＢａＴｉＯ3 １００モルに対する比率が ＭｇＯ：０．１〜３モル、 ＭｎＯ：０．０５〜１．０モル、 Ｙ2 Ｏ3 ：１モル以下、 ＢａＯ＋ＣａＯ：２〜１２モル、 ＳｉＯ2 ：２〜１２モル であることを特徴とする積層型セラミックチップコンデ
ンサ。3. A multilayer ceramic chip capacitor having a capacitor chip body in which dielectric layers and internal electrode layers are alternately stacked, wherein the dielectric layer contains barium titanate as a main component. It contains magnesium oxide, manganese oxide, yttrium oxide, at least one selected from barium oxide and calcium oxide, and silicon oxide as components. Barium titanate is converted into BaTiO 3 , magnesium oxide is converted into MgO, and oxidized. When manganese is converted into MnO, yttrium oxide is converted into Y 2 O 3 , barium oxide is converted into BaO, calcium oxide is converted into CaO, and silicon oxide is converted into SiO 2 , the ratio with respect to 100 mol of BaTiO 3 is MgO: 0.1. 3 moles, MnO: 0.05 to 1.0 mol, Y 2 O 3: 1 mole or less, BaO + CaO 2-12 mol, SiO 2: 2 to 12 multilayer ceramic chip capacitor which is a mole.
2 Ｏ3 の合計に対し、ＢａＯ、ＣａＯおよびＳｉＯ2 が
（Ｂａx Ｃａ1-x Ｏ）y ・ＳｉＯ2 （ただし、０．３≦
ｘ≦０．７、０．９５≦ｙ≦１．０５である。）として
１〜１０重量％含有される請求項３の積層型セラミック
チップコンデンサ。4. BaTiO 3 , MgO, MnO and Y
With respect to the total of 2 O 3 , BaO, CaO and SiO 2 are (Ba x Ca 1-x O) y · SiO 2 (where 0.3 ≦
x ≦ 0.7 and 0.95 ≦ y ≦ 1.05. 1 to 10% by weight as a).
ｉまたはＮｉ合金である請求項１ないし４のいずれかの
積層型セラミックチップコンデンサ。5. The conductive material contained in the internal electrode layer is N
The multilayer ceramic chip capacitor according to claim 1, which is an i or Ni alloy.
雰囲気中で、１２００〜１４００℃の温度範囲内にて焼
成された請求項５の積層型セラミックチップコンデン
サ。6. The multilayer ceramic chip capacitor according to claim 5, which is fired within a temperature range of 1200 to 1400 ° C. in an atmosphere having an oxygen partial pressure of 10 −8 to 10 −12 atm.
雰囲気中で１１００℃以下の温度範囲内にてアニールさ
れた請求項５または６の積層型セラミックチップコンデ
ンサ。7. The multilayer ceramic chip capacitor according to claim 5, which is annealed in a temperature range of 1100 ° C. or lower in an atmosphere having an oxygen partial pressure of 10 −6 atm or higher after firing.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP5085705A JP2762427B2 (en) | 1992-07-13 | 1993-03-19 | Multilayer ceramic chip capacitors |
| US08/090,257 US5335139A (en) | 1992-07-13 | 1993-07-13 | Multilayer ceramic chip capacitor |
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP20848392 | 1992-07-13 | ||
| JP4-208483 | 1992-07-13 | ||
| JP5085705A JP2762427B2 (en) | 1992-07-13 | 1993-03-19 | Multilayer ceramic chip capacitors |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH0684692A true JPH0684692A (en) | 1994-03-25 |
| JP2762427B2 JP2762427B2 (en) | 1998-06-04 |
Family
ID=26426710
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP5085705A Expired - Lifetime JP2762427B2 (en) | 1992-07-13 | 1993-03-19 | Multilayer ceramic chip capacitors |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2762427B2 (en) |
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| WO1996013046A1 (en) * | 1994-10-19 | 1996-05-02 | Tdk Corporation | Multilayer ceramic chip capacitor |
| WO2000062583A1 (en) * | 1999-04-08 | 2000-10-19 | Tdk Corporation | El element |
| WO2000062582A1 (en) * | 1999-04-07 | 2000-10-19 | Tdk Corporation | Composite substrate, thin film el element using it, and method of producing the same |
| JP2001240467A (en) * | 2000-02-29 | 2001-09-04 | Kyocera Corp | Porcelain of dielectrics, process of producing the same and laminated ceramic condenser |
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| US6628502B2 (en) | 2000-03-31 | 2003-09-30 | Tdk Corporation | Multilayer ceramic chip capacitor and method for producing same |
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1993
- 1993-03-19 JP JP5085705A patent/JP2762427B2/en not_active Expired - Lifetime
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| US5668694A (en) * | 1994-10-19 | 1997-09-16 | Sato; Akira | Multilayer ceramic chip capacitor |
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| JP2002265260A (en) * | 2001-03-07 | 2002-09-18 | Kyocera Corp | Dielectric ceramic and lamination type electronic part |
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