JP3326513B2 - Multilayer ceramic chip capacitors - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a multilayer ceramic chip capacitor.

[0002]

2. Description of the Related Art Multilayer ceramic chip capacitors are:
It is widely used as a small, large-capacity, high-reliability electronic component, and the number used in one electronic device is large. In recent years, with the miniaturization and high performance of devices, demands for further miniaturization, large capacity, low price, and high reliability of multilayer ceramic chip capacitors have become more and more severe.

A multilayer ceramic chip capacitor is usually manufactured by laminating a paste for an internal electrode layer and a paste for a dielectric layer by a sheet method, a printing method, or the like, and simultaneously firing them.

The conductive material of the internal electrode layer is generally Pd or Pd.
Although d alloys are used, Pd is expensive, and relatively inexpensive base metals such as Ni and Ni alloys are being used. When a base metal is used as the conductive material of the internal electrode layer, if the firing is performed in the air, the internal electrode layer is oxidized. Therefore, the simultaneous firing of the dielectric layer and the internal electrode layer must be performed in a reducing atmosphere. is there. However, when firing in a reducing atmosphere, the dielectric layer is reduced and the specific resistance is reduced, and thus non-reducing dielectric materials have been proposed.

However, a multilayer ceramic chip capacitor using a non-reducing dielectric material has a problem that the life of the insulation resistance IR is short and the reliability is low.

Further, when exposing the dielectric to a DC electric field, the dielectric constant epsilon _s is caused a problem that decreases over time. When the dielectric layer is made thinner to make the chip capacitor smaller and larger in capacity, the electric field applied to the dielectric layer when a DC voltage is applied becomes stronger, so that the relative dielectric constant ε _s changes with time, that is, the capacitance changes with time. Becomes significantly larger. Also,
When the dielectric layer is made thin, dielectric breakdown easily occurs.

Further, the capacitor is required to have good DC bias characteristics. DC bias characteristics represent the rate of change of capacitance when an AC electric field and a DC component superimposed on it are applied to a chip capacitor.When the applied DC electric field increases, the capacitance generally decreases. . If this property is insufficient, there is a problem that when a DC electric field is applied during normal use, the capacity is significantly reduced and the capacity does not reach the standard capacity.

By the way, the X7R specified in the EIA standard
In a standard called characteristics, the rate of change of the capacitance is defined to be within ± 15% (reference temperature 25 ° C.) between −55 ° C. and 125 ° C.

As a dielectric material satisfying the X7R characteristic, for example, a dielectric material disclosed in JP-A-61-36170 is disclosed.
A composition of aTiO ₃ + SrTiO ₃ + MnO system is known. However, in this case, the change of the capacitance with time under a DC electric field is large.
It becomes about 0%, and the X7R characteristic cannot be satisfied.

Other non-reducing dielectric porcelain compositions include BaTiO ₃ + MnO + MgO disclosed in JP-A-57-71866 and JP-A-61-2.
No. 50905 (Ba _1-x Sr _{x
O) a Ti 1-y Zr} y O 2 + α ((1-z) MnO + z
(CoO) + β ((1-t) A ₂ O ₅ + tL ₂ O ₃ ) + w
SiO ₂ (where A = Nb, Ta, V, L = Y or a rare earth element), barium titanate disclosed in JP-A-2-83256, and BaαCa _1- α in a glassy state
One to which SiO ₃ is added is exemplified. However, all of these dielectric ceramic compositions have good temperature characteristics of capacitance, small change with time of capacitance under DC electric field, good DC bias characteristics, and accelerated life of insulation resistance. Is not long enough to satisfy all the required characteristics. For example, JP-A-61-2509
No. 05 and JP-A-2-83256, respectively, have a short accelerated life of insulation resistance.

Under such circumstances, the present inventors have disclosed in Japanese Patent Application Nos. 5-85705 and 5-154355 that barium titanate is contained as a main component, and magnesium oxide and yttrium oxide are used as subcomponents. And a multilayer ceramic chip capacitor having a dielectric layer containing a predetermined amount of at least one selected from barium oxide and calcium oxide and silicon oxide.

[0012]

SUMMARY OF THE INVENTION It is an object of the present invention to provide a capacitor which can satisfy the X7R characteristic which is a temperature characteristic, has a small change with time in a capacitance under a DC electric field, and has an accelerated life of an insulation resistance IR. It is an object of the present invention to provide a multilayer ceramic chip capacitor having a long DC bias characteristic, good DC bias characteristics, and less likely to cause dielectric breakdown.

[0013]

This and other objects are achieved by any one of the following constitutions (1) to (4).
(1) A multilayer ceramic chip capacitor having a capacitor chip body having a configuration in which dielectric layers and internal electrode layers are alternately stacked, wherein the dielectric layer is composed of barium titanate as a main component and oxidation as a subcomponent. At least one selected from barium oxide and calcium oxide as at least one of magnesium oxide and yttrium oxide, and at least one selected from silicon oxide, manganese oxide, vanadium oxide and molybdenum oxide as other subcomponents
And barium titanate to BaTiO ₃ , magnesium oxide to MgO, and yttrium oxide to Y ₂ O
₃ , barium oxide to BaO, calcium oxide to Ca
O, silicon oxide to SiO ₂ , manganese oxide to MnO
Vanadium oxide to V ₂ O ₅ and molybdenum oxide to M
When converted to oO ₃ , respectively, the ratio of MgO: 0.1 to ₃ moles to 100 moles of BaTiO ₃ , Y ₂ O ₃ :
More than 0 mol and 5 mol or less, BaO + CaO: 2 to 12 mol,
SiO ₂ : 2 to 12 mol, MnO: more than 0 mol and 0.5 mol or less, V ₂ O ₅ : 0 to 0.3 mol, MoO ₃ : 0 to 0.
A multilayer ceramic chip capacitor in which 3 mol, V ₂ O ₅ + MoO ₃ : more than 0 mol, and the average crystal grain size of the dielectric layer is 0.6 μm or less. (2) The average crystal grain size of the dielectric layer is 0.45 μm or less, and in the X-ray diffraction chart of the dielectric layer, (200)
The diffraction line of the plane and the diffraction line of the (002) plane at least partially overlap each other to form a wide diffraction line, and the half-width of the wide diffraction line is equal to or less than 0.35 °. A) Multilayer ceramic chip capacitors. (3) In the cross section of the dielectric layer, the ratio of crystal grains in which the existence of domain walls can be confirmed is 35 to 85%. (1)
Or the multilayer ceramic chip capacitor of (2). (4) The multilayer ceramic chip capacitor according to any one of the above (1) to (3), wherein the conductive material contained in the internal electrode layer is Ni or a Ni alloy.

[0014]

According to the present invention, Japanese Patent Application No. 5-857 is disclosed.
As reported in Japanese Patent Application No. 05 and Japanese Patent Application No. 5-154355, it is possible to satisfy the X7R characteristic relating to the temperature characteristic of the capacitance, to have a small change with time in the capacitance under a DC electric field, and to accelerate the insulation life of the insulation resistance IR. And a multilayer ceramic chip capacitor having a long DC bias characteristic. Moreover, in the present invention, since the dielectric layer contains a predetermined amount of vanadium oxide and / or molybdenum oxide, the change with time of the capacitance under a DC electric field is further improved. The addition of vanadium oxide improves the dielectric breakdown voltage, and the addition of molybdenum oxide improves the accelerated IR life.

The average crystal grain size of the dielectric layer is set to 0.45
By setting the dielectric layer to not more than μm, and by setting the characteristics of the dielectric layer expressed by X-ray diffraction to a predetermined value, it is possible to further improve the time-dependent change in capacitance under a DC electric field.
Further, by shortening the average crystal grain size in this way, the accelerated IR life is improved.

As described above, in the multilayer ceramic chip capacitor of the present invention, sufficiently high reliability can be obtained even when the electric field strength is increased due to the thin dielectric layer.

It should be noted that a report on "low-temperature sinterable barium titanate" is described on pages 33 to 38 of "Multilayer Ceramic Capacitor" (Gakudensha). In this report, fine barium titanate powder is manufactured by using various manufacturing methods, and liquid phase sintering is performed by adding CuO, Bi ₂ O ₃ , PbO, etc. to obtain a grain size of 0.3. A sintered body of about 0.8 μm is obtained. The report included:
As described above, a sintered body having a grain size overlapping with the average crystal grain size range defined in the present invention is described. However, the diffraction line of the (200) plane and the diffraction line of the (002) plane in the X-ray diffraction chart of the dielectric layer are described. There is no description about diffraction lines. Further, the barium titanate sintered body having a grain size of 0.3 to 0.8 μm described in the same report, unlike the composition of the dielectric layer in the present invention, cannot be fired in a reducing atmosphere. Ni-based electrodes cannot be used.

[0018]

[Specific Configuration] Hereinafter, a specific configuration of the present invention will be described in detail.

[Laminated Ceramic Chip Capacitor] FIG. 1 is a cross-sectional view of a configuration example of the laminated ceramic chip capacitor of the present invention.

As shown in FIG. 1, a multilayer ceramic chip capacitor 1 according to the present invention has a structure in which dielectric layers 2 and internal electrode layers 3 are alternately stacked.
0, and the outer surface of the capacitor chip body 10 has an external electrode 4 which is electrically connected to the internal electrode layer 3. The shape of the capacitor chip body 10 is not particularly limited, but is generally a rectangular parallelepiped. The size is not particularly limited and may be an appropriate size depending on the application.
6mm) × (0.5-5.0mm) × (0.5-1.9mm)
It is about. The internal electrode layer 3 is laminated so that the end faces thereof are alternately exposed on the two opposing surfaces of the capacitor chip body 10, and the external electrodes 4 are formed on the two opposing surfaces of the capacitor chip body 10, Configure the circuit.

<Dielectric Layer 2> The dielectric layer 2 contains barium titanate as a main component, magnesium oxide and yttrium oxide as subcomponents, and further contains other subcomponents.
At least one selected from barium oxide and calcium oxide, silicon oxide, manganese oxide, and at least one selected from vanadium oxide and molybdenum oxide. Barium titanate is replaced with BaTiO
₃ , magnesium oxide to MgO, yttrium oxide to Y ₂ O ₃ , barium oxide to BaO, calcium oxide to CaO, silicon oxide to SiO ₂ , manganese oxide to MnO, and vanadium oxide to V ₂ O ₅ When molybdenum oxide is converted to MoO ₃ , the ratio of each compound in the dielectric layer is MgO: 0.1 to 3 mol, preferably 0.5 to 2.0 with respect to 100 mol of BaTiO _3.
Mol, Y ₂ O ₃ : more than 0 mol and 5 mol or less, preferably 0.1 mol or less.
1-5 mol, more preferably more than 1 mol and 5 mol or less, still more preferably 1.1-3.5 mol, BaO + CaO: 2
１２12 mol, preferably 2-6 mol, SiO ₂ : 2-1
2 mol, preferably 2 to 6 mol, MnO: more than 0 mol
5 mol or less, preferably 0.01 to 0.4 mol, V ₂ O
₅ : 0 to 0.3 mol, preferably 0 to 0.25 mol, M
oO _3: 0 to 0.3 mol, preferably 0 to 0.25 _{mol, V 2 O 5 + MoO 3} : 0 mol, preferably greater than 0.0
It is 1 to 0.3 mol, more preferably 0.05 to 0.25 mol.

The oxidation state of each oxide is not particularly limited as long as the ratio of the metal element constituting each oxide is within the above range.

The dielectric layer 2 may contain other compounds, but it is preferable that cobalt oxide is not substantially contained because it increases the rate of change in capacity.

The reasons for limiting the contents of the respective subcomponents are as follows.

When the content of magnesium oxide is less than the above range, it is difficult to reduce the change over time of the capacity. When the content of magnesium oxide exceeds the above range,
Sinterability deteriorates rapidly, densification becomes insufficient, the IR accelerated life is shortened, and a high relative dielectric constant cannot be obtained.

[0026] Yttrium oxide has the effect of improving the IR accelerated life and also improves the DC bias characteristics. If the content of yttrium oxide is small, the effect of the addition becomes insufficient, and in particular, the DC bias characteristics become insufficient. If the content of yttrium oxide exceeds the above range, the specific permittivity decreases, and the sinterability decreases, resulting in insufficient densification.

If the content of BaO + CaO is less than the above range, the change with time of the capacity when a DC electric field is applied becomes large, the IR accelerated life becomes insufficient, and the temperature characteristic of the capacity is set in a desired range. Can not do. When the content exceeds the above range, the IR accelerated life becomes insufficient and the relative dielectric constant sharply decreases. On the other hand, if the content of SiO ₂ is less than the above range, the sinterability is reduced and densification becomes insufficient, and if it exceeds the above range, the initial insulation resistance becomes too low.

Manganese oxide has a function of densifying the dielectric layer and a function of improving the IR accelerated life. However, if the manganese oxide content is too large, it is difficult to reduce the time-dependent change in the capacity when a DC electric field is applied. .

Vanadium oxide and molybdenum oxide are:
Improves the aging of capacitance under DC electric field. Vanadium oxide improves the breakdown voltage, and molybdenum oxide improves the accelerated IR lifetime. V ₂ O ₅ and MoO
_If at least one of the _three is too large, the initial IR will be extremely reduced.

Further, the dielectric layer may contain aluminum oxide. Aluminum oxide has the effect of enabling sintering at relatively low temperatures. The content of aluminum oxide when converted to Al ₂ O ₃ is 1 in the dielectric layer.
% By weight or less. If the content of aluminum oxide is too large, the relative dielectric constant will be significantly reduced,
At the same time, the IR accelerated life is shortened.

The average crystal grain size of the dielectric layer is 0.6 μm or less, preferably 0.45 μm or less, more preferably 0.1 μm or less.
35 μm or less. When the average crystal grain size is 0.6 μm or less, the change over time in the capacity and the IR accelerated life are improved. In particular, when the average crystal grain size is reduced to 0.45 μm or less, the anisotropy of the crystal is reduced, and the change over time in the capacity is further reduced. Further, when the average crystal grain size is reduced to 0.45 μm or less, the IR accelerated life is further improved. There is no particular lower limit on the crystal grain size, but in order to reduce the average crystal grain size, it is necessary to use a correspondingly small dielectric material powder, which makes it difficult to form a paste. For this reason, it is usually preferable that the average crystal grain size of the dielectric layer be 0.10 μm or more. The average crystal grain size of the dielectric layer is calculated from a scanning electron microscope image using a planimetric method after polishing the dielectric layer and chemically or thermally etching the polished surface.

The crystals constituting the dielectric layer are tetragonal at around room temperature. Decreasing crystal anisotropy means approaching a cubic system. The degree of crystal anisotropy can be confirmed by X-ray diffraction of the dielectric layer. When the anisotropy of the crystal becomes small, the diffraction line of the (200) plane shifts to the low angle side and the diffraction line of the (002) plane shifts to the high angle side, so that the two diffraction lines at least partially overlap each other. become. When the average crystal grain size is 0.45 μm or less, usually both diffraction lines are not apparently observed independently,
A wide diffraction line is observed between the diffraction line position of the (200) plane (around 2θ = 45.4 °) and the diffraction line position of the (002) plane (around 2θ = 44.9 °). Become. In the present invention, the half value width of this wide diffraction line is preferably 0.35
° or less, more preferably 0.30 ° or less.
When the half width is too large, the reduction of the crystal anisotropy is insufficient. Although there is no particular lower limit of the half width, it is difficult to make the half width less than 0.10 °, and usually 0.15 ° or more. Note that CuKα was used for X-ray diffraction.
_{Use one} line.

When the anisotropy of the crystal is relatively large,
In some cases, the peak of the diffraction line of the (200) plane and the peak of the diffraction line of the (002) plane are observed independently. (00
2) It becomes a wide diffraction line in which the peak of the surface diffraction line appears. In this case, the width at which the wide diffraction line is cut at a position at half the height of the highest peak is defined as the half width of the wide diffraction line.

When the average crystal grain size is 0.45 μm or less, the proportion of crystal grains in which the presence of domain walls can be confirmed in a transmission electron micrograph of the cross section of the dielectric layer is preferably 35 to 85%. More preferably 35 to 5
0%. When the ratio of the crystal grains in which the domain wall can be confirmed is high, the change with time of the capacity tends to be large.

It is preferable that elements are unevenly distributed in the crystal grains of the dielectric layer. In this case, there are usually elements whose concentration increases at the central part of the crystal grain and elements whose concentration increases at the peripheral part of the crystal grain, but it is usually difficult to clearly confirm the composition with an electron microscope.

The Curie temperature of the dielectric layer can be appropriately set by selecting the composition according to the applicable standard, but is generally 85 ° C. or higher, usually 120 to 135.
About ℃.

Although the thickness of one dielectric layer is not particularly limited, the thickness of the dielectric layer is reduced to 4 μm by applying the present invention.
m or less, and even 2 μm or less, there is little change with time in the capacity, and sufficient reliability can be obtained. In the case of manufacturing by a printing method, the lower limit of the thickness is usually 0.5
It is about μm. The number of stacked dielectric layers is usually 2 to 30.
It is about 0.

<Internal Electrode Layer 3> The conductive material contained in the internal electrode layer 3 is not particularly limited, but a base metal can be used because the material constituting the dielectric layer 2 has reduction resistance.
As the base metal used as the conductive material, Ni or a Ni alloy is preferable. As the Ni alloy, an alloy of one or more elements selected from Mn, Cr, Co, and Al and Ni is preferable, and the Ni content in the alloy is preferably 95% by weight or more.

Incidentally, various trace components such as P may be contained in Ni or Ni alloy in an amount of about 0.1% by weight or less.

The thickness of the internal electrode layer may be appropriately determined according to the application and the like, but is usually 0.5 to 5 μm, especially 0.5 to 5 μm.
It is preferably about 2.5 μm.

<External Electrode 4> The conductive material contained in the external electrode 4 is not particularly limited.
u or an alloy thereof can be used.

The thickness of the external electrode may be appropriately determined according to the application and the like, but is usually preferably about 10 to 50 μm.

[Production Method of Multilayer Ceramic Chip Capacitor] In the multilayer ceramic chip capacitor of the present invention, a green chip is produced by a usual printing method or sheet method using a paste, and after firing, a green chip is formed. It is manufactured by printing or transferring and firing.

<Dielectric Layer Paste> The dielectric layer paste is produced by kneading a dielectric material and an organic vehicle.

As the dielectric material, a powder according to the composition of the dielectric layer is used. The method for producing the dielectric material is not particularly limited. For example, BaTiO ₃ synthesized by hydrothermal synthesis or the like is used.
Then, a method of mixing the auxiliary component raw materials can be used.
Further, a dry synthesis method in which a mixture of BaCO ₃ , TiO _2, and auxiliary component raw materials is calcined to cause a solid phase reaction may be used, or a hydrothermal synthesis method may be used. Alternatively, a mixture of a precipitate obtained by a coprecipitation method, a sol-gel method, an alkaline hydrolysis method, a precipitation mixing method, and the like and a secondary component raw material may be calcined for synthesis. In addition, as the auxiliary component raw material, an oxide or various compounds that become an oxide upon firing, for example, at least one of a carbonate, an oxalate, a nitrate, a hydroxide, and an organometallic compound can be used.

The average particle size of the dielectric material may be determined in accordance with the target average crystal grain size of the dielectric layer. However, since the composition system used in the present invention hardly grows crystal grains, When the average crystal grain size of the layer is 0.45 μm or less, powder having an average particle size of 0.4 μm or less is usually used as the dielectric material. In this case, the specific surface area (BET value) of the dielectric material is preferably 2.5 m ² / g or more.

The organic vehicle is obtained by dissolving a binder in an organic solvent. The binder used for the organic vehicle is not particularly limited, and may be appropriately selected from various ordinary binders such as ethyl cellulose. In addition, the organic solvent to be used is not particularly limited, and may be appropriately selected from various organic solvents such as terpineol, butyl carbitol, acetone, and toluene according to a method to be used such as a printing method and a sheet method.

<Paste for Internal Electrode Layer> The paste for the internal electrode layer is made of a conductive material made of the above-described various conductive metals or alloys, or various oxides, organometallic compounds, resinates, etc. which become the above-mentioned conductive material after firing. And the above-mentioned organic vehicle.

<Paste for External Electrode> The paste for the external electrode may be prepared in the same manner as the paste for the internal electrode layer described above.

<Organic Vehicle Content> The content of the organic vehicle in each of the above-mentioned pastes is not particularly limited, and is usually a content, for example, about 1 to 5% by weight of a binder and about 10 to 50% by weight of a solvent. And it is sufficient. Further, each paste may contain additives selected from various dispersants, plasticizers, dielectrics, insulators, and the like, as necessary.
The total content of these is preferably 10% by weight or less.

<Preparation of Green Chip> When the printing method is used, the paste for the dielectric layer and the paste for the internal electrode layer are laminated and printed on a substrate such as PET, and cut into a predetermined shape. Chips.

When the sheet method is used, a green sheet is formed by using a dielectric layer paste, and a printed sheet of an internal electrode layer is laminated on the green sheet, and then cut into a predetermined shape. , A green chip.

<Binder Removal Step> The conditions of the binder removal processing performed before firing may be ordinary conditions. However, when a base metal such as Ni or a Ni alloy is used as the conductive material of the internal electrode layer, the following conditions are particularly preferable. It is preferable to carry out in. Heating rate: 5 to 300 ° C / hour, especially 10 to 100 ° C / hour
Time Holding temperature: 200 to 400 ° C, especially 250 to 300 ° C Temperature holding time: 0.5 to 24 hours, especially 5 to 20 hours Atmosphere: in air

<Firing Step> The atmosphere during firing of the green chip may be appropriately determined according to the type of the conductive material in the internal electrode layer paste. When a base metal such as Ni or a Ni alloy is used as the conductive material, The oxygen partial pressure in the firing atmosphere is 1
The pressure is preferably from 0 ^-8 to 10 ^-12 atm. If the oxygen partial pressure is less than the above range, the conductive material of the internal electrode layer may abnormally sinter and be interrupted. If the oxygen partial pressure exceeds the above range, the internal electrode layer tends to be oxidized.

The holding temperature during firing is 1100 to 1400
° C, particularly preferably 1200 to 1300 ° C.
If the holding temperature is lower than the above range, the densification is insufficient, and if the holding temperature is higher than the above range, the change with time of the capacity when a DC electric field is applied becomes large.

Various conditions other than the above conditions are preferably as follows.

Heating rate: 50 to 500 ° C./hour, especially 2
00 to 300 ° C / hour Temperature holding time: 0.5 to 8 hours, especially 1 to 3 hours Cooling rate: 50 to 500 ° C / hour, especially 200 to 300
C / hour The firing atmosphere is preferably a reducing atmosphere. As the atmosphere gas, for example, a mixed gas of N ₂ and H ₂ is preferably used after being humidified.

<Annealing Step> When firing in a reducing atmosphere, it is preferable to anneal the capacitor chip body. Annealing is a process for reoxidizing the dielectric layer, which can significantly increase the IR accelerated life.

The oxygen partial pressure in the annealing atmosphere is preferably 10 ⁻⁶ atm or more, particularly preferably 10 ⁻⁵ to 10 ⁻⁴ atm. When the oxygen partial pressure is less than the above range, it is difficult to reoxidize the dielectric layer, and when the oxygen partial pressure exceeds the above range, the internal electrode layer tends to be oxidized.

The holding temperature at the time of annealing is preferably 1100 ° C. or less, particularly preferably 500 to 1000 ° C. If the holding temperature is less than the above range, the oxidation of the dielectric layer tends to be insufficient and the life tends to be short, and if the holding temperature exceeds the above range, the internal electrode layer is oxidized and the capacity is reduced, It tends to react with the substrate and shorten its life. Note that the annealing step may be configured only by raising and lowering the temperature. In this case, the temperature holding time is zero, and the holding temperature is synonymous with the maximum temperature.

Various conditions other than the above conditions are preferably as follows.

Temperature holding time: 0 to 20 hours, especially 6 to 10 hours Cooling rate: 50 to 500 ° C./hour, especially 100 to 300
C / hour It is preferable to use a humidified N ₂ gas or the like as the atmosphere gas.

In each of the above-described steps of the binder removal processing, firing and annealing, for example, a wetter may be used to humidify the N ₂ gas or the mixed gas.
In this case, the water temperature is preferably about 5 to 75 ° C.

The binder removing step, the firing step, and the annealing step may be performed continuously or independently.

In the case where these steps are continuously performed, after removing the binder, the atmosphere is changed without cooling, the temperature is raised to the holding temperature for firing, firing is performed, and then cooling is performed. It is preferable to perform annealing by changing the atmosphere when the temperature reaches the threshold value.

In the firing step in which these steps are performed independently, when the temperature is raised to the holding temperature in the binder removal step, the same atmosphere as in the binder removal processing is used, and the temperature is then raised to the holding temperature. When baking is performed and the temperature is further lowered to the holding temperature in the annealing step, the above firing atmosphere is preferably used, and when the temperature is subsequently lowered from the holding temperature in the annealing step, the above annealing atmosphere is preferably used. In addition, in the annealing step performed independently, N
After raising the temperature to the holding temperature in the _two- gas atmosphere, the atmosphere may be changed, or the entire annealing process may be performed in a humidified N ₂ gas atmosphere.

<Formation of External Electrodes> The capacitor chip body obtained as described above is polished by, for example, barrel polishing or sand blasting, and the external electrode paste is printed or transferred and baked. Form.
The firing conditions for the external electrode paste are, for example, humidified N
It is preferable to set the temperature in a mixed gas of ₂ and H ₂ at 600 to 800 ° C. for about 10 minutes to 1 hour.

Then, if necessary, on the surface of the external electrode 4,
A coating layer is formed by plating or the like.

The multilayer ceramic chip capacitor of the present invention manufactured as described above is mounted on a printed circuit board or the like by soldering or the like, and is used for various electronic devices and the like.

The dielectric layer of the multilayer ceramic chip capacitor of the present invention has a thickness of 0.02 V / μm or more, particularly 0.2 V / μm or more, more preferably 0.5 V / μm or more, and generally about 5 V / μm when used. The following DC electric field and an AC component superimposed on the DC electric field are usually applied. Even when such a DC electric field is applied, the change of the capacitance with time is extremely small.

[0071]

EXAMPLES Hereinafter, the present invention will be described in more detail with reference to specific examples of the present invention.

Example 1 The following pastes were prepared. BaTiO ₃ produced by the paste hydrothermal synthesis method for the dielectric layer was added with (MgCO _{3
3) 4 · Mg (OH)} 2 · 5H 2 O, MnCO 3, Ba
A compound selected from CO ₃ , CaCO ₃ , SiO ₂ , Y ₂ O ₃ , V ₂ O ₅ and MoO ₃ was added so as to have a composition shown in each of the following tables, and wet-mixed by a ball mill for 16 hours. It was used as a dielectric material.

100 parts by weight of each dielectric material, 4.8 parts by weight of acrylic resin, 40 parts by weight of methylene chloride, 20 parts by weight of trichloroethane, 6 parts by weight of mineral spirit and 4 parts by weight of acetone are mixed by a ball mill to form a paste. did.

100 parts by weight of Ni particles having an average particle diameter of 0.8 μm for the internal electrode layer paste, 40 parts by weight of an organic vehicle (8 parts by weight of ethyl cellulose resin dissolved in 92 parts by weight of butyl carbitol) and 10 parts by weight of butyl carbitol By weight and kneaded with three rolls to form a paste.

100 parts by weight of Cu particles having an average particle diameter of 0.5 μm for the external electrode paste, 35 parts by weight of an organic vehicle (8 parts by weight of ethyl cellulose resin dissolved in 92 parts by weight of butyl carbitol) and 7 parts by weight of butyl carbitol And kneaded to form a paste.

A multilayer ceramic chip capacitor having the structure shown in FIG. 1 was manufactured using the above-mentioned pastes for the dielectric layers and the pastes for the internal electrode layers.

First, PET is used by using a dielectric layer paste.
A green sheet having a thickness of 5 μm was formed on the film, a paste for an internal electrode layer was printed thereon, and the sheet was peeled off from the PET film. A plurality of sheets produced in this manner were laminated and bonded under pressure to obtain a green laminate. The number of stacked sheets was four.

Next, the green laminate was cut into a predetermined size to obtain a green chip, and binder removal, firing and annealing were continuously performed under the following conditions to produce a capacitor chip.

Binder removal temperature increase rate: 15 ° C./hour Holding temperature: 280 ° C. Temperature holding time: 8 hours Atmospheric gas: in air

Firing temperature rising rate: 200 ° C./hour Holding temperature: 1300 ° C. Temperature holding time: 2 hours Cooling rate: 300 ° C./hour Atmospheric gas: humidified mixed gas of N ₂ and H ₂ Oxygen partial pressure: 10 ^{− 9} atm

Annealing holding temperature: 900 ° C. Temperature holding time: 9 hours Cooling rate: 300 ° C./hour Atmospheric gas: humidified N ₂ gas Oxygen partial pressure: 10 ⁻⁵ atm

A wetter was used for humidifying each atmosphere gas, and the water temperature was 35 ° C.

After polishing the end face of the obtained capacitor chip body by sandblasting, the above-mentioned external electrode paste was transferred to the end face, and the paste was removed in a humidified N ₂ + H ₂ atmosphere.
An external electrode was formed by baking at 0 ° C. for 10 minutes to obtain a multilayer ceramic chip capacitor sample.

The size of each sample manufactured as described above was 3.2 mm × 1.6 mm × 0.6 mm, the thickness of the dielectric layer was 3 μm, and the thickness of the internal electrode layer was 2 μm.

The composition of the dielectric layer of each sample is shown in each table. The composition is expressed as a ratio to 100 moles of BaTiO ₃ as described above.

The average crystal grain size of the dielectric layer of each sample was:
It was 0.35 μm. The average crystal grain size was calculated by the above-described method using a scanning electron micrograph of the cross section of the sample. A scanning electron micrograph of the dielectric layer of Sample No. 110 is shown in FIG.

Further, the surface of each sample was irradiated with CuKα ₁ ray to perform X-ray diffraction of the dielectric layer. As a result, in all the samples, the diffraction line of the (200) plane and the diffraction line of the (002) plane overlapped to form a wide diffraction line, and it was impossible to distinguish the two diffraction lines. The half value widths of these wide diffraction lines were in the range of 2θ = 0.30 to 0.34 °.
An X-ray diffraction chart of Sample No. 116 is shown in FIG.

Further, transmission electron micrographs of the dielectric layer of each sample were taken, and the ratio of crystal grains where domain walls were observed was examined. As a result, the ratio of crystal grains where domain walls were observed was in the range of 44 to 50%. A transmission electron micrograph of Sample No. 102 is shown in FIG.

The following measurement was performed for each sample. The results are shown in each table.

Temperature characteristic of capacitance X7R characteristic: The capacitance was measured at a measurement voltage of 1 V at -55 to 125 ° C. with an LCR meter, and the capacitance change rate was ± 1
It was examined whether or not 5% or less (reference temperature: 25 ° C.) was satisfied. When satisfied, it was evaluated as ○, and when it was not satisfied, as ×.

Change of Capacitance with Time under DC Electric Field The initial capacity C ₀ was measured at a measurement voltage of 1.0 V (alternating current) using an LCR meter. Next, the thickness of the dielectric layer is 1 μm.
After applying a DC electric field of 2.1 V per hour at 40 ° C. for 1000 hours, the device was left at room temperature for 24 hours without load. After the standing, the capacitance was measured, and the amount of change ΔC ₁ from the initial capacitance C ₀ was measured.
And the rate of change ΔC ₁ / C ₀ was calculated. The capacity after standing was measured under the above conditions.

An acceleration test was performed under an electric field of 15 V / μm at an accelerated life of insulation resistance IR at 140 ° C.
The time until the resistance (IR) became 2 × 10 ⁵ Ω or less was defined as the life time.

Relative permittivity ε _s The relative permittivity at 25 ° C. was measured.

Breakdown voltage V _{B At} room temperature, a DC voltage was applied using an automatic voltage raising device to perform a breakdown test. The voltage when the leakage current became 1 mA or more was defined as the breakdown voltage.

[0095]

[Table 1]

[0096]

[Table 2]

From the results shown in the above tables, the effect of the present invention is clear. Note that a sample in which the IR accelerated life or breakdown voltage is not indicated is a sample that could not be measured due to a semiconductor or the like.

Example 2 The composition of the dielectric layer was as shown in Table 3, and the average crystal grain size of the dielectric layer was 0.60 μm.
A sample was obtained in the same manner as in Example 1, except that The same measurement as in Example 1 was performed on these samples. Table 3 shows the results.

[0099]

[Table 3]

The sample of the present invention shown in each of the above tables also satisfies the temperature characteristic of capacitance as B characteristic {capacitance change within ± 10% at −25 to 85 ° C. (reference temperature 20 ° C.)}. Was.

[Brief description of the drawings]

FIG. 1 is a sectional view showing a configuration example of a multilayer ceramic chip capacitor of the present invention.

FIG. 2 is a drawing substitute photograph, which is a scanning electron microscope photograph of a cross section of a dielectric layer of a multilayer ceramic chip capacitor.

FIG. 3 is an X-ray diffraction chart of a dielectric layer of the multilayer ceramic chip capacitor.

FIG. 4 is a drawing substitute photograph, which is a transmission electron microscope photograph of a dielectric layer of the multilayer ceramic chip capacitor.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Multilayer ceramic chip capacitor 10 Capacitor chip body 2 Dielectric layer 3 Internal electrode layer 4 External electrode

──────────────────────────────────────────────────続 き Continuing on the front page (72) Inventor Yo Sato 1-13-1 Nihonbashi, Chuo-ku, Tokyo TDK Corporation (72) Inventor Tomohiro Arashi 1-13-1 Nihonbashi, Chuo-ku, Tokyo TDK Inside (72) Inventor Junko Yamamatsu 1-1-13 Nihonbashi, Chuo-ku, Tokyo Inside TDK Corporation (56) References JP-A-61-250905 (JP, A) JP-A-6-275459 ( JP, A) JP-A-6-5460 (JP, A) (58) Fields investigated (Int. Cl. ⁷ , DB name) H01G 4/12

Claims (1)

(57) [Claims] 1. A multilayer ceramic chip capacitor having a capacitor chip body having a structure in which dielectric layers and internal electrode layers are alternately stacked, wherein the dielectric layer comprises barium titanate as a main component, and a sub-component. containing magnesium oxide, and yttrium oxide as
And barium titanate containing at least one selected from barium oxide and calcium oxide, silicon oxide, manganese oxide, and at least one selected from vanadium oxide and molybdenum oxide as other auxiliary components. To BaTiO ₃ and magnesium oxide to Mg
O, yttrium oxide to Y ₂ O ₃ , barium oxide to BaO, calcium oxide to CaO, silicon oxide to S
When iO ₂ , manganese oxide is converted to MnO, vanadium oxide is converted to V ₂ O ₅ , and molybdenum oxide is converted to MoO ₃ , the ratio of Mg to 100 mol of BaTiO ₃ is Mg.
O: 0.1 to 3 mol, Y ₂ O ₃ : more than 0 mol, 5 mol or less, BaO + CaO: 2 to 12 mol, SiO ₂ : 2 to 12 mol, MnO: more than 0 mol, 0.5 mol or less, V ₂ O _5: 0 to 0.3 mole, _MoO 3: 0 to 0.3 _{mole, V 2 O 5 + MoO 3} : 0 is the molar excess, a multilayer ceramic average crystal grain diameter of the dielectric layer is 0.6μm or less Chip capacitors.