JP4728051B2 - Dielectric ceramic and multilayer ceramic capacitor - Google Patents

Dielectric ceramic and multilayer ceramic capacitor Download PDF

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JP4728051B2
JP4728051B2 JP2005174622A JP2005174622A JP4728051B2 JP 4728051 B2 JP4728051 B2 JP 4728051B2 JP 2005174622 A JP2005174622 A JP 2005174622A JP 2005174622 A JP2005174622 A JP 2005174622A JP 4728051 B2 JP4728051 B2 JP 4728051B2
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智也 萩原
潤 西川
浩一郎 都竹
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太陽誘電株式会社
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本発明は、誘電体セラミック、その誘電体セラミックを用いた、Niなどの卑金属を内部電極とする積層セラミックコンデンサ及びその積層セラミックコンデンサの製造方法に関する。   The present invention relates to a dielectric ceramic, a multilayer ceramic capacitor using the dielectric ceramic and a base metal such as Ni as an internal electrode, and a method for manufacturing the multilayer ceramic capacitor.

卑金属を内部電極とする積層セラミックコンデンサにおいて、材料は還元雰囲気で焼成しなければいけない。そのため、高信頼性を確保するためには耐還元性と再酸化性を付与する必要がある。Vは添加剤として、耐還元性と再酸化性を与えることがわかっており、寿命特性の改善に効果があり、また、静電容量の経時変化を改善する効果がある(特許文献1及び2参照)。
特開2004−210613号公報 特開平8−124785号公報
In a multilayer ceramic capacitor having a base metal as an internal electrode, the material must be fired in a reducing atmosphere. Therefore, in order to ensure high reliability, it is necessary to provide reduction resistance and reoxidation property. V has been found to give reduction resistance and reoxidation as an additive, and is effective in improving the life characteristics, and also has the effect of improving the change in capacitance with time (Patent Documents 1 and 2). reference).
Japanese Patent Laid-Open No. 2000-210613 JP-A-8-124785

上記のように、Vは効果を有するものであるが、Vを添加したセラミック誘電体を用いて内部電極が卑金属の積層セラミックコンデンサを製造すると、製品の絶縁特性及び寿命特性にバラツキが多く発生し、安定して所望の特性を得ることが難しいという問題があった。また、静電容量の温度変化率にもバラツキが発生し、所望の温度特性例えばX7R特性からはずれるものが発生するという問題を有していた。
このような現象について鋭意研究したところ、Vは還元焼成雰囲気下において、価数が3〜5価にわたって幅広い状態で存在することがわかった。そのため、電子のやり取りによるホッピング伝導が生じて、絶縁抵抗が低下することがわかった。また、3価のVは、BaTiO3における拡散性が高く、Ti4+との置換反応が進む。そのため、3価のVが多いと、コアシェル構造を破壊しやすくなり、比誘電率の低下、温度特性の悪化が起こることがわかった。一方、5価のVは、BaTiO3に拡散しにくく、Baと二次相を形成してバナジウム酸バリウムとして析出する。そのため5価のVが多いと、誘電率の低下と、耐還元性と再酸化性が損なわれることによる寿命特性の悪化が生じてしまうことがわかった。
As described above, V has an effect. However, when a multilayer ceramic capacitor whose internal electrode is a base metal is manufactured using a ceramic dielectric added with V, there are many variations in the insulation characteristics and life characteristics of the product. There is a problem that it is difficult to stably obtain desired characteristics. Further, there is a problem that the variation rate of the temperature of the electrostatic capacitance also varies, and there is a problem that a deviation from desired temperature characteristics, for example, X7R characteristics occurs.
As a result of earnest research on such a phenomenon, it has been found that V exists in a wide range of valences ranging from 3 to 5 in a reducing firing atmosphere. Therefore, it has been found that hopping conduction is caused by the exchange of electrons and the insulation resistance is lowered. Trivalent V is highly diffusible in BaTiO 3 and the substitution reaction with Ti 4+ proceeds. For this reason, it has been found that when the trivalent V is large, the core-shell structure is easily broken, and the relative permittivity is lowered and the temperature characteristics are deteriorated. On the other hand, pentavalent V hardly diffuses into BaTiO 3 , forms a secondary phase with Ba, and precipitates as barium vanadate. For this reason, it has been found that when pentavalent V is large, the dielectric constant is lowered and the life characteristics are deteriorated due to the reduction in resistance to reduction and reoxidation.

本発明は、上記のような問題を解決しようとするものであり、絶縁抵抗、寿命特性および静電容量の温度特性のバラツキの小さい積層セラミックコンデンサ及びその積層セラミックコンデンサの製造方法を提供することを課題とする。   The present invention is intended to solve the above-described problems, and provides a multilayer ceramic capacitor having small variations in insulation resistance, life characteristics, and capacitance temperature characteristics, and a method of manufacturing the multilayer ceramic capacitor. Let it be an issue.

本発明は、上記課題を解決するために、以下の手段を採用する。
(1) BaTiO3を主成分とし、Vを含有する誘電体セラミックにおいて、
前記誘電体セラミックは、主成分BaTiO 3 と、
副成分として、
BaTiO 3 100molに対し、
Vを0.05〜5.0mol、
希土類酸化物を0〜5.0mol、
MgO、CaO及びSrOから選ばれる一種又は二種以上のアルカリ土類酸化物を0.1〜5.0mol含有し、
前記誘電体セラミックは、コアシェル構造を有し、前記コアシェル構造中にVがV 3+ 、V 4+ 、V 5+ として存在し、前記コアシェル構造中に存在するVの平均価数が3.8〜4.1で、かつ、(V 3+ 、V 4+ 、V 5+ )の存在量に対しV 4+ の存在量が、30%以上であること特徴とする誘電体セラミックである。
(2)前記(1)の誘電体セラミックを、セラミック誘電体層に用い、
前記セラミック誘電体層と内部電極層とを交互に積層した積層チップの表面に外部電極を備えた積層セラミックコンデンサである。
(3)内部電極が卑金属であることを特徴とする前記(2)の積層セラミックコンデンサである。
The present invention employs the following means in order to solve the above problems.
(1) In a dielectric ceramic mainly containing BaTiO 3 and containing V,
The dielectric ceramic comprises a main component BaTiO 3 and
As a minor component
For 100 mol of BaTiO 3 ,
V to 0.05 to 5.0 mol,
0 to 5.0 mol of rare earth oxide,
Containing 0.1 to 5.0 mol of one or more alkaline earth oxides selected from MgO, CaO and SrO;
The dielectric ceramic has a core-shell structure, V is present as V 3+ , V 4+ , V 5+ in the core-shell structure, and an average valence of V present in the core-shell structure is 3.8. The dielectric ceramic is characterized in that it is ˜4.1 and the abundance of V 4+ is 30% or more with respect to the abundance of (V 3+ , V 4+ , V 5+ ) .
(2) The dielectric ceramic of (1) is used for a ceramic dielectric layer,
The multilayer ceramic capacitor includes an external electrode on a surface of a multilayer chip in which the ceramic dielectric layers and internal electrode layers are alternately stacked.
(3) The multilayer ceramic capacitor according to (2) , wherein the internal electrode is a base metal.

ホッピング伝導機構が抑制されることにより、リーク電流量が減少し、絶縁抵抗のバラツキを小さくすることができる。また、適度な濃度勾配を持ったシェル相により、静電容量の温度特性のバラツキを小さくすることができる。さらに、V添加による耐還元性と再酸化性の効果が損なわれずに発揮され、寿命特性を悪化させる酸素欠陥の導入が抑制されるため、寿命特性のバラツキを小さくすることができる。   By suppressing the hopping conduction mechanism, the amount of leakage current can be reduced and the variation in insulation resistance can be reduced. Moreover, the variation in the temperature characteristic of the capacitance can be reduced by the shell phase having an appropriate concentration gradient. Furthermore, the effects of reduction resistance and reoxidation by V addition are exhibited without being impaired, and the introduction of oxygen defects that deteriorate the life characteristics is suppressed, so that variations in the life characteristics can be reduced.

本発明は、BaTiO3を主成分とし、Vを含有する誘電体セラミックにおいて、誘電体セラミック中にVの価数が3.8以上4.1以下の間で存在させる。また、V4+の存在割合を30%以上となるようにする。
Vの価数と存在割合の算出法には、XPSによるV2pスペクトル観測結果からスペクトル分離を用いる。
According to the present invention, in a dielectric ceramic containing BaTiO 3 as a main component and containing V, the valence of V is present in the dielectric ceramic between 3.8 and 4.1. Also, the proportion of V 4+ is made 30% or more.
For the calculation method of the valence and the existence ratio of V, spectrum separation is used from the V2p spectrum observation result by XPS.

Vの価数分布を狭い範囲で存在させることで、ホッピング伝導機構の発生を抑制する。
また、4価に近い状態にすることで、BaTiO3への過剰な拡散あるいはバナジウム酸バリウム相の析出が抑制され、適度な濃度勾配があるシェル相を持ったコアシェル構造を形成することができる。
Vの添加量は、BaTiO3100molに対して0.05〜5.0molが好ましい。
By causing the valence distribution of V to exist within a narrow range, generation of a hopping conduction mechanism is suppressed.
Moreover, by setting it to a state close to tetravalent, excessive diffusion to BaTiO 3 or precipitation of the barium vanadate phase is suppressed, and a core-shell structure having a shell phase with an appropriate concentration gradient can be formed.
The amount of V added is preferably 0.05 to 5.0 mol with respect to 100 mol of BaTiO 3 .

また、本発明の誘電体セラミックは、BaTiO3、V以外に、希土類酸化物を含有させることができる。希土類酸化物の添加範囲は、BaTiO3100molに対して0〜5.0molが好ましい。希土類酸化物を添加することにより、直流バイアス特性が向上する。しかし、5.0molを超えると、比誘電率の低下と、焼結性の低下が生じるので、好ましくない。以下の実施例では、Ho23を含有させているが、Ho23を以下に挙げる他の希土類酸化物;Sm23、Eu23、Tb23、Dy23、Er23、Tm23、Yb23、Y23で一部あるいは全量置換しても、実施例の場合と同様に、微細構造が得られ、所望の電気特性を得ることができる。 The dielectric ceramic of the present invention can contain rare earth oxides in addition to BaTiO 3 and V. The addition range of the rare earth oxide is preferably 0 to 5.0 mol with respect to 100 mol of BaTiO 3 . By adding the rare earth oxide, the DC bias characteristics are improved. However, if it exceeds 5.0 mol, the relative dielectric constant and the sinterability are lowered, which is not preferable. In the following examples, Ho 2 O 3 is contained, but Ho 2 O 3 is another rare earth oxide listed below: Sm 2 O 3 , Eu 2 O 3 , Tb 2 O 3 , Dy 2 O 3 , Er 2 O 3 , Tm 2 O 3 , Yb 2 O 3 , Y 2 O 3 , even if part or all of the amount is substituted, a fine structure is obtained and desired electrical characteristics are obtained as in the case of the examples. be able to.

さらに、本発明の誘電体セラミックは、Ba以外のアルカリ土類酸化物を含有させることもできる。アルカリ土類酸化物の添加範囲は、BaTiO3100molに対して0.1〜5.0molが好ましい。0.1molより少ないと、粒成長を抑制することが困難となり、5.0molより多いと、比誘電率の低下と、焼結性の低下が生じるので、好ましくない。以下の実施例では、MgOを含有させているが、MgOをCaO、SrOで一部あるいは全量置換した場合でも、実施例の場合と同様に、微細構造が得られ、所望の電気特性を得ることができる。 Furthermore, the dielectric ceramic of the present invention may contain an alkaline earth oxide other than Ba. The addition range of the alkaline earth oxide is preferably 0.1 to 5.0 mol with respect to 100 mol of BaTiO 3 . If the amount is less than 0.1 mol, it is difficult to suppress grain growth. If the amount is more than 5.0 mol, the relative permittivity and the sinterability decrease, which is not preferable. In the following examples, MgO is contained. However, even when MgO is partially or entirely replaced with CaO or SrO, a fine structure can be obtained and desired electrical characteristics can be obtained as in the case of the examples. Can do.

なお、本発明の誘電体セラミックは、Mn23、BaSiO3等の他の金属酸化物、複合酸化物等を含有させてもよい。これらの金属酸化物、複合酸化物の添加範囲は、BaTiO3100molに対して0.1〜2.0molが好ましい。この範囲内であれば、焼結性が向上する。 The dielectric ceramic of the present invention may contain other metal oxides such as Mn 2 O 3 and BaSiO 3 , composite oxides, and the like. The addition range of these metal oxides and composite oxides is preferably 0.1 to 2.0 mol with respect to 100 mol of BaTiO 3 . Within this range, the sinterability is improved.

本発明の積層セラミックコンデンサは、上記のようなBaTiO3を主成分とし、Vを含有する誘電体セラミックからなるセラミック誘電体層と内部電極層とを交互に積層した積層チップの表面に外部電極を備えたものであり、以下の(a)〜(i)で示されるような、グリーンセラミック層、内部電極層及び外部電極の焼成を同時に行う従来の積層セラミックコンデンサの製造工程と同様な工程を経て製造される。 The multilayer ceramic capacitor of the present invention has an external electrode on the surface of a multilayer chip in which the above-mentioned BaTiO 3 as a main component and ceramic dielectric layers made of a dielectric ceramic containing V and internal electrode layers are alternately laminated. Through the same process as the manufacturing process of the conventional multilayer ceramic capacitor in which the green ceramic layer, the internal electrode layer and the external electrode are simultaneously fired as shown in the following (a) to (i) Manufactured.

(a)材料粉末の仮焼工程
主成分のBaTiO3になる粉末と副成分のV酸化物等になる粉末をボールミル等で混合粉砕したセラミック材料粉末を仮焼し、BaTiO3とV酸化物等からなる仮焼物を製造する。仮焼温度は800℃程度が好ましい。
なお、V酸化物は、V25の他、V24等価数の異なるものを混合したものを適宜用いても良い。
(A) Calcination process of material powder A ceramic material powder obtained by mixing and pulverizing a powder that becomes BaTiO 3 as a main component and a powder that becomes V oxide as a subcomponent with a ball mill or the like is calcined, and BaTiO 3 and V oxide, etc. A calcined product made of The calcining temperature is preferably about 800 ° C.
Note that as the V oxide, in addition to V 2 O 5, a mixture of different V 2 O 4 equivalent numbers may be used as appropriate.

(b)グリーンシートの形成工程
得られた仮焼物にバインダ及び溶剤を加え、これを数時間ボールミル等で撹拌・混合することにより適度な粘度をもったスラリーを作製する。次に、ドクターブレード法等により、スラリーからセラミックグリーンシートを作製する。このドクターブレード法では、PET等のベースフィルム上にスラリーを流し、その厚みをドクターブレードとの隙間で調整する。この後、これを乾燥させて所定の厚みのセラミックグリーンシートを得る。
(B) Green sheet forming step A binder and a solvent are added to the obtained calcined product, and this is stirred and mixed with a ball mill or the like for several hours to prepare a slurry having an appropriate viscosity. Next, a ceramic green sheet is produced from the slurry by a doctor blade method or the like. In this doctor blade method, slurry is flowed on a base film such as PET, and the thickness thereof is adjusted by a gap with the doctor blade. Thereafter, this is dried to obtain a ceramic green sheet having a predetermined thickness.

(c)内部電極層の形成工程
予め用意された導体ペーストをスクリーン印刷法等の印刷手法によってグリーンシートの表面に所定パターン、所定厚で印刷することにより内部電極層とする。内部電極としてはNi等の卑金属が好ましい。
(C) Internal electrode layer forming step A conductor paste prepared in advance is printed on the surface of the green sheet with a predetermined pattern and a predetermined thickness by a printing method such as a screen printing method to form an internal electrode layer. The internal electrode is preferably a base metal such as Ni.

(d)積層工程
印刷後のグリーンシートを所定の単位寸法でカットしてベースフィルムから取り出し、取り出されたグリーンシートを必要枚数積み重ねる。
積み重ねられたグリーンシートを仮圧着し、さらに本圧着する。
(D) Lamination process The green sheet after printing is cut by a predetermined unit size, taken out from the base film, and the required number of the taken green sheets is stacked.
The green sheets that have been stacked are temporarily pressed and further pressed.

(e)切断工程
本圧着後の積層グリーンシートを回転ブレードや昇降ブレード等のブレードによって個々の積層チップに切断する。
(E) Cutting step The laminated green sheet after the main press-bonding is cut into individual laminated chips with a blade such as a rotating blade or a lifting blade.

(f)脱バインダ工程
切断した積層チップを脱バインダ炉に投入して、所定の温度及び時間等の条件下で積層チップ本体(グリーンセラミック層)に含まれているバインダを除去する。雰囲気としては、N2雰囲気が好ましい。
(F) Debinding process The cut multilayer chip is put into a binder removal furnace, and the binder contained in the multilayer chip body (green ceramic layer) is removed under conditions such as a predetermined temperature and time. The atmosphere is preferably an N 2 atmosphere.

(g)焼成工程
積層チップを焼成炉に投入して、所定の温度及び時間等の条件下で焼成する。焼成温度は、1150℃〜1350℃が好ましい。
焼成時の雰囲気は、酸素分圧が10-9atm(10-4Pa)〜10-12atm(10-7Pa)が一般的であるが、Vの価数を制御するため、例えばNi−NiOの平衡酸素分圧相当の10-8atm(10-3Pa)付近までの雰囲気が適用可能である。なお、Vの価数制御は、焼成温度の昇温速度あるいは降温速度、後述の再酸化処理工程の条件によっても可能である。
(G) Firing step The laminated chip is put into a firing furnace and fired under conditions such as a predetermined temperature and time. The firing temperature is preferably 1150 ° C to 1350 ° C.
The atmosphere during firing is generally an oxygen partial pressure of 10 −9 atm (10 −4 Pa) to 10 −12 atm (10 −7 Pa). In order to control the valence of V, Ni— An atmosphere up to about 10 −8 atm (10 −3 Pa) corresponding to the equilibrium oxygen partial pressure of NiO is applicable. The valence control of V can also be performed by the rate of temperature increase or decrease of the firing temperature and the conditions of the reoxidation process described later.

(h)外部電極の形成工程
予め用意された導体ペーストをローラ塗布法やディップ法等の塗布手法によって、焼成された積層チップ両端部に所定厚及び所定形状で塗布し、焼付けて外部電極を形成する。外部電極としてはNi、Cu、Ag等が好ましい。
なお、外部電極ペーストの塗布を焼成前の積層チップの段階で行い、グリーンセラミック層、内部電極層及び外部電極を同時焼成してもよい。
(H) External electrode forming step A conductor paste prepared in advance is applied to both ends of the fired laminated chip in a predetermined thickness and shape by a coating method such as a roller coating method or a dip method, and baked to form an external electrode. To do. Ni, Cu, Ag or the like is preferable as the external electrode.
The external electrode paste may be applied at the stage of the laminated chip before firing, and the green ceramic layer, the internal electrode layer, and the external electrode may be fired simultaneously.

(i)再酸化処理工程
焼成工程の後で、焼成温度よりも低い温度の酸化性雰囲気下で再酸化処理を行う。再酸化処理の温度は600〜800℃が好ましい。
酸化性雰囲気としては、大気雰囲気に限定することなく、例えば、N2や、N2に数ppmのO2を混合したような低酸素濃度の雰囲気も使用することができる。
どのような温度あるいはどのような酸素濃度の雰囲気にするかは、内部電極(Ni等の卑金属)の酸化、あるいはVの価数制御などを考慮して種々変更する必要がある。
(I) Reoxidation treatment step After the firing step, reoxidation treatment is performed in an oxidizing atmosphere at a temperature lower than the firing temperature. The reoxidation temperature is preferably 600 to 800 ° C.
The oxidizing atmosphere is not limited to the air atmosphere, and for example, an atmosphere having a low oxygen concentration such as N 2 or a mixture of N 2 with several ppm of O 2 can also be used.
It is necessary to make various changes in consideration of the oxidation of the internal electrode (base metal such as Ni) or the control of the valence of V, etc.

BaTiO3;100molに対してV25;0.1mol、Ho23;0.5mol、MgO;1.0mol、Mn23;0.1mol、BaSiO3;0.5molの組成割合になるよう秤量し、ボールミルで充分に湿式混合粉砕して混合物を得た。
次に、この混合物を脱水し乾燥して、空気中、800℃の条件で仮焼し、仮焼物を得た。この仮焼物をエタノールで湿式解砕し、乾燥した。これに有機バインダ、溶剤を加えてドクターブレード法で約4μmの厚みでシート化した。
次に、このシートにNiの内部電極を印刷法により形成した。このシートを10層に積層して、熱圧着して積層体を得、縦3.2mm×横1.6mmの3216形状に切断した。
そして、得られた積層体を、N2雰囲気で脱バインダ処理した後、酸素分圧が2.5×10-9atm(=2.5×10-4Pa)〜2.0×10-8atm(=2.0×10-3Pa)の範囲で1200℃にて熱処理し、チップ焼結体を得た。
得られた焼結体にAg外部電極をディップで形成し、その後、チップ焼結体をN2/600〜800℃の条件で再酸化処理を行い、積層セラミックコンデンサを得た。
BaTiO 3 ; 100 mol, V 2 O 5 ; 0.1 mol, Ho 2 O 3 ; 0.5 mol, MgO; 1.0 mol, Mn 2 O 3 ; 0.1 mol, BaSiO 3 ; The mixture was weighed and sufficiently wet-mixed and pulverized with a ball mill to obtain a mixture.
Next, this mixture was dehydrated and dried, and calcined in air at 800 ° C. to obtain a calcined product. This calcined product was wet crushed with ethanol and dried. An organic binder and a solvent were added thereto to form a sheet with a thickness of about 4 μm by the doctor blade method.
Next, Ni internal electrodes were formed on the sheet by a printing method. This sheet was laminated into 10 layers, and thermocompression bonded to obtain a laminate, which was cut into a 3216 shape having a length of 3.2 mm and a width of 1.6 mm.
Then, after the obtained laminate was treated to remove the binder in an N 2 atmosphere, the oxygen partial pressure was 2.5 × 10 −9 atm (= 2.5 × 10 −4 Pa) to 2.0 × 10 −8. Heat treatment was performed at 1200 ° C. in the range of atm (= 2.0 × 10 −3 Pa) to obtain a chip sintered body.
The Ag external electrodes were formed by dipping the obtained sintered body, then subjected to reoxidation tip sintered under conditions of N 2/600 to 800 ° C., to obtain a laminated ceramic capacitor.

得られた試料(積層セラミックコンデンサ)について、Vの価数評価を行った。Vの価数評価には、XPSを用いた。V2pスペクトルを観測し、カーブフィッティングによるピーク分離からV3+、V4+、V5+の存在量を算出した。その結果を表1に示す。また、ピーク分離の一例を図1に示す。 The valence evaluation of V was performed about the obtained sample (multilayer ceramic capacitor). XPS was used for the valence evaluation of V. The V2p spectrum was observed, and the abundances of V 3+ , V 4+ and V 5+ were calculated from peak separation by curve fitting. The results are shown in Table 1. An example of peak separation is shown in FIG.

表1に示したとおり、酸素分圧が4.0×10-9atm(=4.1×10-4Pa)〜9.9×10-9atm(=1.0×10-3Pa)においてVの平均価数が3.83〜4.04、V4+が30%以上で存在する微細構造が得られたことを確認した。 As shown in Table 1, the oxygen partial pressure is 4.0 × 10 −9 atm (= 4.1 × 10 −4 Pa) to 9.9 × 10 −9 atm (= 1.0 × 10 −3 Pa). It was confirmed that a microstructure having an average valence of V of 3.83 to 4.04 and a V 4+ of 30% or more was obtained.

得られた試料の電気特性評価を行った。電気特性として、室温の誘電率測定、静電容量の温度変化率の測定、室温での抵抗率測定、及び150℃・100V負荷における高温加速寿命試験を行った。その結果を表2に示す。   The electrical characteristics of the obtained sample were evaluated. As electrical characteristics, a room temperature dielectric constant measurement, a capacitance temperature change rate measurement, a room temperature resistivity measurement, and a high temperature accelerated life test at 150 ° C./100 V load were performed. The results are shown in Table 2.

表2に示したとおり、酸素分圧が4.0×10-9atm(=4.1×10-4Pa)以上で、誘電率、抵抗率、及び寿命特性の向上が確認された。 As shown in Table 2, when the oxygen partial pressure was 4.0 × 10 −9 atm (= 4.1 × 10 −4 Pa) or more, improvement in dielectric constant, resistivity, and life characteristics was confirmed.

また、図2に示したとおり、酸素分圧が9.9×10-9atm(=1.0×10-3Pa)以下でX7R特性を満たすことが確認できた。 Further, as shown in FIG. 2, it was confirmed that the X7R characteristic was satisfied when the oxygen partial pressure was 9.9 × 10 −9 atm (= 1.0 × 10 −3 Pa) or less.

以上、Vの平均価数を3.8〜4.1、V4+を30%以上となるよう作製した積層コンデンサにおいて、X7R特性を満たし、高誘電率、高寿命特性で且つ、高絶縁抵抗が得られることを確認した。 As described above, in the multilayer capacitor manufactured so that the average valence of V is 3.8 to 4.1 and V 4+ is 30% or more, the X7R characteristic is satisfied, the dielectric constant is high, the life is long, and the high insulation resistance is satisfied. It was confirmed that

V2pスペクトルによるピーク分離から積層セラミックコンデンサのVの価数評価を行う一例を示す図である。It is a figure which shows an example which performs the valence evaluation of V of a multilayer ceramic capacitor from the peak separation by a V2p spectrum. 積層セラミックコンデンサの静電容量の温度変化率(25℃基準)を示す図である。It is a figure which shows the temperature change rate (25 degreeC reference | standard) of the electrostatic capacitance of a multilayer ceramic capacitor.

Claims (3)

  1. BaTiO3を主成分とし、Vを含有する誘電体セラミックにおいて、
    前記誘電体セラミックは、主成分BaTiO 3 と、
    副成分として、
    BaTiO 3 100molに対し、
    Vを0.05〜5.0mol、
    希土類酸化物を0〜5.0mol、
    MgO、CaO及びSrOから選ばれる一種又は二種以上のアルカリ土類酸化物を0.1〜5.0mol含有し、
    前記誘電体セラミックは、コアシェル構造を有し、前記コアシェル構造中にVがV 3+ 、V 4+ 、V 5+ として存在し、前記コアシェル構造中に存在するVの平均価数が3.8〜4.1で、かつ、(V 3+ 、V 4+ 、V 5+ )の存在量に対しV 4+ の存在量が、30%以上であること特徴とする誘電体セラミック。
    In a dielectric ceramic mainly containing BaTiO 3 and containing V,
    The dielectric ceramic comprises a main component BaTiO 3 and
    As a minor component
    For 100 mol of BaTiO 3 ,
    V to 0.05 to 5.0 mol,
    0 to 5.0 mol of rare earth oxide,
    Containing 0.1 to 5.0 mol of one or more alkaline earth oxides selected from MgO, CaO and SrO;
    The dielectric ceramic has a core-shell structure, V is present as V 3+ , V 4+ , V 5+ in the core-shell structure, and an average valence of V present in the core-shell structure is 3.8. A dielectric ceramic characterized in that the abundance of V 4+ is 30% or more with respect to the abundance of (V 3+ , V 4+ , V 5+ ) .
  2. 請求項1記載の誘電体セラミックを、セラミック誘電体層に用い、
    前記セラミック誘電体層と内部電極層とを交互に積層した積層チップの表面に外部電極を備えた積層セラミックコンデンサ。
    The dielectric ceramic according to claim 1 is used for a ceramic dielectric layer,
    The ceramic dielectric layers and the multilayer ceramic capacitor having an external electrode and an internal electrode layer on the surface of the laminated chip laminated alternately.
  3. 前記内部電極が卑金属であることを特徴とする請求項に記載の積層セラミックコンデンサ。 The multilayer ceramic capacitor according to claim 2 , wherein the internal electrode is a base metal.
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