JPH0682757A - Image display method for electro-optical device - Google Patents

Abstract

PURPOSE:To perform an extremely homogeneous gradation display even with a slight dispersion in thin film transistor(TFT) by conducting digital mode gradation display. CONSTITUTION:Each of four deformed buffer circuits is formed of at least two NTFTs and at least two PTFTs. In this circuit, the gate electrode of one set of NTFT and PTFT in the center part is first connected, and further connected to a signal line Xn, and one-side sources or drains of the NTFT and PTFT are mutually connected and then connected to the electrode of a picture element Zn,m. The other sources or drains of the NTFT and PTFT are connected to the sources or drains of the second PTFT, NTFT, respectively. The time of applying voltage to a liquid crystal is controlled, whereby gradation is visually provided. Namely, the interval between i-th and (i+1)-th pulses is represented by 2<i+1>T1 ((i) is a finite natural number, T1 is a constant).

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image display method in a liquid crystal electro-optical device using a thin film transistor (hereinafter referred to as a TFT) as a switching element for driving, and in particular, a gradation display for obtaining an intermediate color tone or gradation expression. It is about the method. The present invention particularly relates to so-called fully digital gradation display, which performs gradation display without applying any analog signal from the outside to the active element.

[0002]

2. Description of the Related Art Liquid crystal compositions have different permittivities in the horizontal and vertical directions with respect to the molecular axis because of their material properties, and therefore they can be aligned horizontally or vertically with respect to an external electric field. It can be done easily. The liquid crystal electro-optical device utilizes the anisotropy of the dielectric constant to control the amount of transmitted light or the amount of scattered light, thereby performing ON / OFF, that is, bright / dark display. Liquid crystal materials include TN (Twisted Nematic) liquid crystal, STN (Super
Materials called twisted nematic) liquid crystal, ferroelectric liquid crystal, polymer liquid crystal, or dispersion type liquid crystal are known. It is known that liquid crystal does not respond to an external voltage in an infinitely short time, but it takes a certain time to respond. The value is unique to each liquid crystal material. In the case of TN liquid crystal, it is several tens of msec, ST
It is several 100 msec in the case of N liquid crystal, several hundred μsec in the case of ferroelectric liquid crystal, and several tens msec in the case of dispersion type or polymer liquid crystal.

Among electro-optical devices using liquid crystals, the one which can obtain the most excellent image quality is one using the active matrix system. In a conventional active matrix type liquid crystal electro-optical device, a thin film transistor (TFT) is used as an active element, an amorphous or polycrystalline semiconductor is used for the TFT, and P is used for one pixel.
The TFT of only one of the N type and the N type was used. That is, in general, N-channel TFT
(Referred to as NTFT) is connected in series to the pixel. Then, a signal voltage is applied to the signal lines of the matrix, and when signals are applied from both sides to the TFTs provided at the orthogonal positions of the respective signal lines, the TFTs are turned on. It was to control OFF individually. By controlling the pixels by such a method, a liquid crystal electro-optical device having a large contrast can be realized.

[0004]

However, in such an active matrix system, it is extremely difficult to perform gradation display such as brightness and color tone. Conventionally, a method of utilizing the fact that the light transmittance of the liquid crystal changes depending on the magnitude of the applied voltage has been studied for gradation display. This is, for example, the source of the TFT in the matrix
By supplying an appropriate voltage from the peripheral circuit between the drains and applying a signal voltage to the gate electrode in that state,
It was intended to apply a voltage of that magnitude to the liquid crystal pixels.

However, in such a method, the voltage applied to the liquid crystal pixel actually varies from pixel to pixel by at least several percent due to, for example, the non-uniformity of the TFT and the non-uniformity of the matrix wiring. Oops. On the other hand, for example, the voltage dependence of the light transmittance of liquid crystal is extremely non-linear, and the light transmittance changes abruptly at a certain voltage. It could be significantly different. Therefore, actually, it was a limit to achieve 16 gradations.

The difficulty of gradation display is extremely disadvantageous in that the liquid crystal display device competes with the CRT (cathode ray tube) which is a conventional general display device.

An object of the present invention is to propose a completely new method for realizing gradation display which has been difficult in the past.

[0008]

As described above, it is possible to control the light transmissivity of the liquid crystal by controlling the voltage applied to the liquid crystal in an analog manner. It has been found that the gradation can be visually obtained by controlling the time when voltage is applied to the liquid crystal.

For example, in the case of using TN (twisted nematic) liquid crystal which is a typical liquid crystal material,
For example, it has been found that the brightness can be changed by applying the various pulses shown in FIG. 1 to the liquid crystal pixels. That is, “1” in FIG.
The brightness can be gradually increased in the order of "2", ... "15". That is, in the example of FIG. 1, 16 gradations can be displayed. At this time, with "1", a pulse having a length of 1 unit is applied. Further, at "2", a pulse having a length of 2 units is applied. At "3", a pulse of 1 unit and a pulse of 2 units are applied, and as a result, a pulse of a length of 3 units is applied. At "4", a pulse having a length of 4 units is applied, at "5", a pulse of 1 unit and a pulse of 4 units are applied, and at "6", a pulse of 2 units and a pulse of 4 units are applied, respectively. It Further, by preparing a pulse having a length of 8 units, it is possible to obtain a pulse having a maximum length of 15 units.

That is, by properly combining four types of pulses of 1 unit, 2 units, 4 units, and 8 units, it is possible to display 2 ⁴ = 16 gradations. Furthermore, 1
By preparing many pulses, such as 6 units, 32 units, 64 units, and 128 units, respectively,
High gradation display of 32 gradations, 64 gradations, 128 gradations and 256 gradations is possible. For example, in order to obtain 256 gradations, eight kinds of pulses may be prepared.

Further, in the example of FIG. 1, the duration of the voltage applied to the pixel is first T ₁ , second 2T ₁ , and then 4T.
An example is shown in which are arranged to increase geometric progression manner as that _1, which is for example, as shown in FIG. 3, the first T _1,
It may be 8T ₁ , then 2T ₁ , and finally 4T ₁ . By arranging in this way, the load on the device for transmitting data to the display device can be reduced.

For implementing the present invention, as the liquid crystal material, TN liquid crystal, STN liquid crystal, ferroelectric liquid crystal and dispersed (polymer) liquid crystal are suitable. Further, the pulse width of one unit is slightly different depending on which liquid crystal material is selected, but 10 nsec or more is suitable for the TN liquid crystal material.

In order to further implement the present invention, for example, a matrix circuit using TFTs as shown in FIG. 4 may be assembled. Unlike the circuit used in the conventional active matrix, the circuit shown in FIG. 4 is a CMOS buffer circuit modified and used as its switching element.

In FIG. 4, four modified buffer circuits are depicted. Each modified buffer circuit is composed of at least two NTFTs and at least two PTFTs.
The number of TFTs may be further increased in case there is a defect. In this circuit, first, the gate electrodes of a set of NTFT and PTFT in the central portion are connected, and further connected to the signal line X _n , and one of the source and drain of the NTFT and PTFT is connected to each other, which is the pixel. It is connected to the Z _{n, m} electrode. This state is the same as in a normal complementary field effect element (CMOS). This NT
The other source or drain of the FT and PTFT is connected to the source or drain of the second PTFT or NTFT, respectively. Also, this second PT
The other sources or drains of the FT and NTFT are connected to the signal lines Y _m and Y _{m + 1} , respectively. Further, the gate electrodes of the second PTFT and NTFT are connected to the signal lines Y _{m + 1} and Y _m , respectively. Below,
Signal lines X _1, X _2, a _.. X _N, collectively, or individually X
Signal lines Y _1, Y _{2, ...,} Y _M are collectively or individually referred to as Y lines.

In the figure, a capacitor is artificially inserted in parallel with the pixel capacitor. The capacitor inserted at this time has a function of suppressing the voltage of the pixel from dropping due to the natural discharge of the pixel. Since the voltage drop speed of the pixel is determined by the pixel variation, the deterioration of the image quality is caused especially in the invention for performing the gradation display with the voltage applied to the pixel being constant as in the present invention. It is an invitation. However, by thus inserting the capacitors in parallel with the pixels, the voltage effect due to the variation of the pixels can be significantly suppressed, and high image quality can be obtained.

Further, by incorporating an organic ferroelectric material such as tetrafluoroethylene or polyvinylidene fluoride into a pixel of a liquid crystal cell or the like, the capacitance of the pixel is increased, and thus the time constant of discharge of the pixel is increased. It is also possible to obtain high image quality without increasing such an artificial capacitor.

Of course, if the pixel discharge is sufficiently small, such an artificial capacitor is unnecessary. In particular, the presence of an excessive capacitance requires a long time for charging / discharging operations, which is not desirable in the practice of the present invention. To reduce the pixel discharge, for example, the O
It is necessary to increase the FF resistance, reduce the leak current, and sufficiently increase the interelectrode resistance of the pixel itself such as liquid crystal. Particularly for the latter purpose, it is effective to cover the pixel electrode with an insulating material such as silicon nitride, silicon oxide, tantalum oxide, or aluminum oxide.

In such a circuit, ON / OFF of the voltage applied to the pixel can be controlled by controlling the gate voltage and the source / drain voltage of each TFT. In the example of FIG. 4, the matrix is 480
Although it is × 640 dots, in order to avoid complication, only the vicinity of the nth row and the mth column is shown. If you expand the same thing up, down, left and right, you can get the perfect one. An example of the operation of this circuit is shown in FIG. A rectangular pulse signal is sequentially applied to the Y line as shown in FIG. On the other hand, for X-rays,
A signal composed of a plurality of pulses is applied. This pulse train contains 480 pieces of information in one unit of time T ₁ .

In the following, four pixels Z _{n, m} , Z _{n, m + 1} ,
Focus on Z _{n + 1, m} and Z _{n + 1, m + 1} . These pixels include
For example, taking Z _{n, m} as an example, X _n is a positive potential, or in a more general expression, a high potential state (V _H ).
And Y _m is also V _H , the pixel electrode becomes V _H. On the other hand, if Y _m is V _L , no change occurs in the pixel regardless of the state of X _n . Therefore,
Regarding these four pixels, it suffices to pay attention to the signal lines X _n and X _{n + 1} and Y _m and Y _{m + 1} .

Consider a case where a rectangular pulse is applied to Y _m and enters the V _H state as shown in the figure. Now, since attention is paid to four pixels, it suffices to pay attention to the current states of X _n and X _{n + 1} . At this time, since X _n is V _H and X _{n + 1} is V _L , the pixel Z _{n, m} is eventually V _H and the pixel Z.
_{n + 1, m} becomes V _L. Then, if the Y line is set to V _L earlier than the next signal is applied to the X line, the pixel voltage state is maintained by the pixel capacitor, so that the pixel Z _{n, m} maintains V _H. After that, basically, the state of each pixel continues until the next Y _m becomes V _H. Then, Y
_A pulse is applied to _{m + 1} . As shown in the figure,
At that time, since X _n is V _L and X _{n + 1} is V _H , the pixel Z _{n, m + 1} is V _L and the pixel Z _{n + 1, m + 1} is V _H. Then, as described above, each state is maintained.

Next, when a pulse is applied to Y _m and then a pulse is applied again to Y _m after time T ₁ , X _n is V _L and X _{n + 1} is V _H. So pixel Z
_{The state of n, m} changes to V _L , and the state of the pixel Z _{n + 1, m} changes to V _H. Further, a pulse is applied to Y _{m + 1} . At this time, as shown in the figure, since both X _n and X _{n + 1} are V _H , both the pixel Z _{n, m + 1} and the pixel Z _{n + 1, m + 1} are V _H. At this time, the pixel Z _{n + 1, m + 1} continues V _H.

Then, after a time 2T ₁ , a third pulse is applied to Y _m . At that time, both X _n and X _{n + 1} are V
_Since it is _H , the pixel Z _{n, m} changes from V _L to V _H , and the pixel Z _{n + 1, m} continues V _H. Furthermore, Y
_A pulse is applied to _{m + 1} . At that time, X _n is also X
_{Since n + 1 is} also V _L , the pixel Z _{n, m + 1} is also a pixel Z _{n + 1, m + 1.}
Also becomes V _L.

Then, after time 4T ₁ , a fourth pulse is applied to Y _m . At that time, both X _n and X _{n + 1} are V
_Since it is _L , both the pixel Z _{n, m} and the pixel Z _{n + 1, m} are V _L. Furthermore, a pulse is applied to Y _{m + 1} , but again,
Since both X _n and X _{n + 1} are V _L , the pixel Z _{n, m + 1} is also the pixel Z.
_{n + 1 and m + 1} also remain V _L.

In this way, one cycle is completed. During this time, four pulses are applied to each Y line, and 3 × 640 = 1920 information signals are applied to each X line. Also,
The time of this one cycle is 8T ₁ , and as T ₁ , for example, 10 nsec to 10 msec is suitable. Then, paying attention to each pixel, the pixel Z _{n, m} has a time T
A pulse of _{1 and} a pulse of 4T ₁ are applied, and visually 5
The same effect is obtained as if the pulse of T ₁ was applied. That is, a brightness of "5" is obtained. Similarly, pixel Z
_{n + 1, m} , pixel Z _{n, m + 1} and pixel Z _{n + 1, m + 1} ,
Brightnesses of "2", "6", and "3" are obtained.

In the above example, display of 8 gradations is possible, but by adding more pulse signals,
Higher gradation is possible. For example, in one cycle, a pulse is further applied to the Y-ray 5 times, and 8 × 640 is applied to each X-ray.
If an information signal of 5120 is applied, a high gradation display of 256 gradations can be achieved.

For high-gradation display, extremely high-speed switching is required, as is apparent from FIG. For example, in order to realize 256 gradations, it is necessary to feed out 30 or more moving images per second, so 256T ₁
<30 msec. Therefore, T ₁ <100 μsec. Therefore, when the number of Y lines is 640, it is necessary to apply a pulse having a width of 150 nsec or less to the Y lines. Since such an operation performance is required, it is necessary to use a CMOS buffer circuit unlike the conventional one.

In the above description, the counter electrode of the pixel is not described in order to facilitate understanding, but by applying an appropriate bias voltage to the counter electrode of the pixel, it is possible to substantially affect the pixel material. It is possible to change various voltages. For example, the counter electrode of the pixel, by applying an appropriate voltage, the direction of the voltage applied to the pixel material varied V _L and V _H, can also be adapted can take both positive and negative. Such an operation is necessary, for example, in a ferroelectric liquid crystal.

Further, in order to make the explanation easy to understand,
The zero level and voltage level of the signal are clarified. Is this below the threshold voltage of the liquid crystal or TFT,
It does not have to be absolutely zero, as it is just a matter of whether or not it is above. Further, since the voltage is a relative physical quantity with reference to the potential at any point, in the above example,
It will be clear that the pulses can be of opposite polarity.

Further, in the above example, although the method of line by line scanning, for example, first _{Y 1, Y 3, Y 5} , .. to the scanning and so, then, Y _2, Y ₄ Needless to say, a method of so-called interlaced scanning, in which scanning is performed as Y _, Y _{6 ,} .

[0030]

【Example】

Example 1 In this example, a wall-mounted television was manufactured using a liquid crystal display device having a circuit configuration as shown in FIG. Further, the TFT at that time was made of polycrystalline silicon using laser annealing.

FIG. 5 shows the actual arrangement of electrodes and the like corresponding to this circuit structure for one pixel. First, a method for manufacturing a liquid crystal panel used in this example will be described with reference to FIGS. In order to carry out the present invention, two NTFTs and two PTFTs are required for one pixel.
Although a total of four TFTs are shown in the figure, for simplification, the number is attached to only one of the NTFT and the PTFT. Figure 6
In (A), a silicon oxide film as a blocking layer 51 is formed on a glass 50, such as quartz glass, which can withstand a heat treatment at 700 ° C. or less, for example, about 600 ° C.
It is made to a thickness of 0Å. The process conditions were an atmosphere of 100% oxygen, a film forming temperature of 15 ° C., an output of 400 to 800 W, and a pressure of 0.5 Pa. The film formation rate using quartz or single crystal silicon for the target was 30 to 100 Å / min.

A silicon film 52 was formed on this by a plasma CVD method. The film forming temperature is 250 ° C. to 35
The temperature is set to 0 ° C., and in this embodiment, the temperature is set to 320 ° C.
₄ ) was used. Not only monosilane (SiH ₄ ) but also disilane (Si ₂
H ₆ ) Alternatively, trisilane (Si ₃ H ₈ ) may be used. These were introduced into the PCVD device at a pressure of 3 Pa, and 13.56M
A high frequency power of Hz was applied to form a film. At this time, the high frequency power is suitably 0.02 to 0.10 W / cm ² , and in this example, 0.055 W / cm ² was used. The flow rate of monosilane (SiH ₄ ) was 20 SCCM, and the film formation rate at that time was about 120 Å / min. In order to control the threshold voltage (Vth) of the PTFT and the NTFT to be approximately the same, boron is used in an amount of 1 × 10 ¹⁵ to 1 × 10 ¹⁸ cm by using diborane.
^-3 may be added during film formation. Further, not only the plasma CVD but also the sputtering method or the low pressure CVD method may be used for forming the silicon layer to be the channel region of the TFT. The method will be briefly described below.

When the sputtering method is used, the back pressure before sputtering is set to 1 × 10 ^-5 Pa or less, the single crystal silicon is used as the target, and the atmosphere is mixed with 20-80% of hydrogen in argon. For example, argon is 20% and hydrogen is 80%.
The film forming temperature was 150 ° C., the frequency was 13.56 MHz, the sputter output was 400 to 800 W, and the pressure was 0.5 Pa.

When formed by the reduced pressure vapor phase method, it is 450 to 550 ° C., which is 100 to 200 ° C. lower than the crystallization temperature, for example, 5
Disilane (Si ₂ H ₆ ) or trisilane (Si ₃ H ₈ ) was supplied to a CVD apparatus at 30 ° C. to form a film. The reactor pressure is 30 ~
It was set to 300 Pa. The film forming rate was 50 to 250 Å / min. In order to control the threshold voltage (Vth) of the PTFT and that of the NTFT to be approximately the same, boron may be added during film formation using diborane at a concentration of 1 × 10 ¹⁵ to 1 × 10 ¹⁸ cm ^-3. .

The film formed by these methods is
It is preferable that oxygen is 5 × 10 ²¹ cm ⁻³ or less. In order to promote crystallization, the oxygen concentration is 7 × 10 ¹⁹ cm ^-3 or less,
It is preferable that the size is 1 × 10 ¹⁹ cm ^-3 or less,
If the amount is too small, the leak current in the off state increases due to the backlight, so this concentration was selected. If the oxygen concentration is high, it is difficult to crystallize, and the laser annealing temperature must be high or the laser annealing time must be long. Hydrogen is 4 × 10 ²⁰ cm ^-3 and silicon is 4 × 10 ²²
It was 1 atom% when compared as cm ^-3 .

In order to further promote crystallization of the source and drain, the oxygen concentration is set to 7 × 10 ¹⁹ cm ^-3 or less, preferably 1 × 10 ¹⁹ cm ^-3 or less, and the TF for forming a pixel is set.
Oxygen may be added only to the channel forming region of T by the ion implantation method so as to have a concentration of 5 × 10 ^{20 to} 5 × 10 ²¹ cm ⁻³ .
By the above method, an amorphous silicon film is formed into 500
The film was formed to a thickness of ˜5000 Å, 1000 Å in this example.

After that, the photoresist 53 is used as a mask P1.
Was used to form a pattern in which only the source / drain regions were opened. A silicon film 54, which will be an n-type active layer, was formed thereon by a plasma CVD method. Film formation temperature is 250 ° C
The temperature is set to 320 ° C. in this embodiment, and monosilane (SiH ₄ ) and monosilane-based phosphine (P
H ₃ ) with 3% concentration was used. These were introduced into the PCVD apparatus at a pressure of 5 Pa, and high frequency power of 13.56 MHz was applied to form a film. At this time, the high frequency power is 0.05 to
0.20 W / cm ² is suitable, and is 0.1 in this embodiment.
20 W / cm ² was used.

The specific conductivity of the n-type silicon layer produced by this method was about 2 × 10 ^-1 [Ωcm ^-1 ]. The film thickness was 50Å. Thereafter, the lift-off method was used to remove the resist 53 and form the n-type impurity region 55.

A p-type active layer was formed using the same process. The gas introduced at this time was a monosilane (SiH ₄ ) and monosilane-based diborane (B ₂ H ₆ ) concentration of 5%. These were introduced into a PCVD device at a pressure of 4 Pa, and high frequency power of 13.56 MHz was applied to form a film.
At this time, the high-frequency power is suitably 0.05~0.20W / cm ^2, in this embodiment using 0.120W / cm ^2. The specific conductivity of the p-type silicon layer produced by this method was about 5 × 10 ^-2 [Ωcm ^-1 ]. The film thickness was 50Å. After that, the p-image impurity region 59 was formed by using the lift-off method similarly to the N-type region. Then, the silicon film 52 was removed by etching using the mask P3 to form an N-channel type thin film transistor island region 63 and a P-channel type thin film transistor island region 64.

Thereafter, the source / drain / channel regions were laser-annealed using a XeCl excimer laser, and at the same time, laser doping was performed on the active layer. The laser energy at this time has a threshold energy of 130 mJ / cm ² , and 220 for melting the entire film thickness.
mJ / cm ² is required. However, 220m from the beginning
When the energy of J / cm ² or more is applied, hydrogen contained in the film is rapidly released, so that the film is broken. Therefore, it is necessary to first drive out hydrogen with low energy and then melt it. In this embodiment, first 150 m
After ejecting hydrogen at J / cm ² , 230mJ
Crystallization was performed at / cm ² .

On this, a silicon oxide film was formed as a gate insulating film to a thickness of 500 to 2000Å, for example 1000Å. This was performed under the same conditions as the production of the silicon oxide film as the blocking layer. During this film formation, a small amount of fluorine may be added to immobilize sodium ions.

After this, 1-5 × 10 ²¹ cm of phosphorus is placed on the upper side.
^-3 concentration silicon film or this silicon film with molybdenum (Mo), tungsten (W), MoSi ₂ or
A multilayer film with WSi ₂ was formed. This was patterned with a fourth photomask P4 to obtain FIG. 6 (D). A gate electrode 66 for NTFT and a gate electrode 67 for PTFT were formed. For example, the channel length is 7 μm, the gate electrode is 0.2 μm of phosphorus-doped silicon, and 0.3 molybdenum is formed thereon.
It was formed to a thickness of μm. At the same time, as shown in FIG. 6D ', the gate wiring and the wiring 68 arranged in parallel therewith are formed.
Also patterned.

When aluminum (Al) is used as the gate electrode material, the self-alignment method can be applied by patterning this with the fourth photomask P4 and then anodizing the surface. Since the source / drain contact holes can be formed at positions closer to the gate, the characteristics of the TFT can be further improved by reducing the mobility and the threshold voltage.

In this way, a C / TFT can be manufactured without applying a temperature above 400 ° C. in all steps. Therefore, an expensive substrate such as quartz does not have to be used as the substrate material, and it can be said that the process is extremely suitable for the large-screen liquid crystal display device of the present invention.

In FIG. 6E, the inter-layer insulator 69 was formed as a silicon oxide film by the above-mentioned sputtering method. This silicon oxide film is formed by LPCVD method, photo CVD method.
Method, atmospheric pressure CVD method may be used. For example, 0.2-0.
Formed to a thickness of 6 μm, and then a fifth photomask P
5 was used to form the window 79 for the electrode. After that, aluminum was further formed on the entire surface by a sputtering method to a thickness of 0.3 μm, and a lead 74 and contacts 73 and 75 were formed using a sixth photomask P6. Thus, FIGS. 6E and 6E ′ were obtained. After that, an organic resin 77 for flattening the surface, for example, a translucent polyimide resin is applied and formed, and the electrode hole is formed again by the seventh photomask P7.
I went there. Further, ITO (Indium Tin Oxide) was formed on the whole of these by a sputtering method to a thickness of 0.1 μm, and the pixel electrode 71 was formed using the eighth photomask P8. This ITO film is formed at room temperature to 150 ° C.
It was accomplished by oxygen at 00 ° C or by annealing in air.

Thus, FIGS. 6F and 6F 'were obtained.
A cross-sectional view taken along the line AA 'in FIG. 6 (F') is shown in FIG. 6 (G).
Actually, a counter electrode is provided on top of this with a liquid crystal material interposed therebetween, and as shown in the figure, a capacitance is generated between the counter electrode and the electrode 71. At the same time, electrostatic capacitance is generated between the wiring 68 and the electrode 71. Then, by keeping the wiring 68 at the same potential as the counter electrode, as shown in FIG. 4, a circuit in which a capacitor is inserted in parallel with the liquid crystal pixel is configured. In particular, by arranging as in this embodiment, since the wiring 68 is parallel to the gate wiring 65, the parasitic capacitance between the two wirings is small, and therefore, there is an effect of reducing the attenuation or delay of the signal transmitted through the gate wiring.

In addition, the wiring 68 formed in this way
When used by being grounded, can be used as a ground line of a protection circuit provided at the end of each matrix. The protection circuit is provided between the peripheral drive circuit and the pixel as shown in FIG. 9, and is a circuit as shown in FIGS. In both cases, when an excessive voltage is applied to the wiring of the pixel, it is turned on and has the action of removing the voltage.
These protection circuits are made of doped or undoped semiconductor material such as silicon or I
It is configured by using a transparent conductive material such as TO or a normal wiring material. Therefore, the pixel circuits can be formed at the same time when they are formed. .

This means that, for example, each protection circuit in FIG. 10 has an NTFT, a PTFT, or a C in which they are combined.
It will be clear from the fact that it is composed of / TFT. Further, although the TFT is not used in the protection circuit of FIG. 11, the diode is composed of, for example, a PIN junction, and the diode which attaches particular importance to the Zener characteristic is N.
It is obvious that it has a structure such as IN, PIP, NPN, or PNP, and it can be manufactured by applying the manufacturing method shown in this embodiment without needing to describe it one by one.

The electrical characteristics of the TFT thus obtained are PTFT and have a mobility of 40 (cm ² / Vs) and Vth.
Is -5.9 (V), the mobility is 80 (cm ² / V with NTFT)
s) and Vth were 5.0 (V).

It was possible to obtain one substrate for a liquid crystal electro-optical device manufactured by the above method. FIG. 5 shows how electrodes and the like of this liquid crystal display device are arranged.
Complementary TFT constituting a deformation buffer according to the present invention
(C / TFT) is provided between the signal lines Y ₁ and Y ₂ and between the signal lines Y ₂ and Y ₃ in parallel with the signal lines X ₁ and X ₂ . A matrix structure using such C / TFT is provided. By repeating this structure horizontally and vertically, a liquid crystal display device with large pixels of 640 × 480 and 1280 × 960 can be obtained. In this embodiment, 19
It was set to 20 × 400. Thus, the first substrate was obtained.

FIG. 7 shows a method of manufacturing the other substrate. A polyimide resin in which a black pigment is mixed with polyimide is formed on a glass substrate to a thickness of 1 μm by a spin coating method,
Black stripe 8 using the ninth photomask P9
1 was produced. Then, a polyimide resin mixed with a red pigment is formed into a film having a thickness of 1 μm by a spin coating method,
Red filter 8 using the tenth photomask P10
3 was produced. Similarly, using the masks P11 and P12, a green filter 85 and a blue filter 86 were produced. During manufacture of these filters, each filter was baked at 350 ° C. in nitrogen for 60 minutes. After that, the leveling layer 89 was made of transparent polyimide by using the spin coating method.

After that, ITO (Indium Tin Oxide) was formed on the entire surface by sputtering to a thickness of 0.1 μm, and the common electrode 90 was formed using the thirteenth photomask P13. This ITO film is formed at room temperature to 150 ° C.
The second substrate was obtained by the conditions of 0 to 300 ° C. oxygen or annealing in air.

A polyimide precursor was printed on the substrate by the offset method, and baked at 350 ° C. for 1 hour in a non-oxidizing atmosphere such as nitrogen. Then, a known rubbing method was used to modify the surface of the polyimide, and a means for orienting liquid crystal molecules in a certain direction was provided at least in the initial stage.

Thereafter, the nematic liquid crystal composition was sandwiched between the first substrate and the second substrate, and the periphery was fixed with an epoxy adhesive. A TAB-shaped drive IC, a PCB having a common signal and a potential wiring were connected to the leads on the substrate, and a polarizing plate was attached to the outside to obtain a transmissive liquid crystal electro-optical device. This was connected to a rear lighting device in which three cold cathode tubes were arranged, and a tuner for receiving TV radio waves, to complete a wall-mounted TV. Compared with the conventional CRT type TV, the device has a planar shape, so that it can be installed on a wall or the like. The operation of this liquid crystal television was confirmed by applying a signal substantially equivalent to that shown in FIGS. 1 and 2 to the liquid crystal pixel.

[Embodiment 2] In this embodiment, a wall-mounted television is manufactured by using a liquid crystal display device having a circuit configuration as shown in FIG. 4, which will be described. Also T at that time
FT was polycrystalline silicon using laser annealing.

In the following, a method of manufacturing the TFT portion will be described with reference to FIG. In FIG. 8 (A), it is less expensive than quartz glass such as 700 ° C. or less, eg, about 600 ° C.
Magnetron RF on glass 100 that can withstand the heat treatment of
(High frequency) A silicon oxide film as the blocking layer 101 is formed to a thickness of 1000 to 3000 Å by using a sputtering method. Process conditions are 100% oxygen atmosphere, film formation temperature 1
The temperature was 5 ° C., the output was 400 to 800 W, and the pressure was 0.5 Pa.
The film formation rate using quartz or single crystal silicon for the target was 30 to 100 Å / min.

A silicon film 102 was formed on this by a plasma CVD method. Film formation temperature is 250 ° C to 3
It is carried out at 50 ° C., and in this embodiment 320 ° C., and monosilane (S
iH ₄ ) was used. Not only monosilane (SiH ₄ ) but also disilane (S
i ₂ H ₆ ) or trisilane (Si ₃ H ₈ ) may be used. These were introduced into the PCVD device at a pressure of 3 Pa, and 13.56
A high frequency power of MHz was applied to form a film. At this time, the high frequency power is suitably 0.02 to 0.10 W / cm ² , and in this example, 0.055 W / cm ² was used. The flow rate of monosilane (SiH ₄ ) was 20 SCCM, and the film formation rate at that time was about 120 Å / min. In order to control the threshold voltage (Vth) of the PTFT and the NTFT to be approximately the same, boron is used in an amount of 1 × 10 ¹⁵ to 1 × 10 ¹⁸ by using diborane.
It may be added as a concentration of cm ⁻³ during film formation. Also TFT
In addition to the plasma CVD, a sputtering method or a low pressure CVD method may be used for forming the silicon layer to be the channel region of the above. The method will be briefly described below.

When the sputtering method is used, the back pressure before the sputtering is set to 1 × 10 ^-5 Pa or less, the single crystal silicon is used as the target, and the atmosphere is mixed with argon and hydrogen of 20 to 80%. For example, argon is 20% and hydrogen is 80%.
The film forming temperature was 150 ° C., the frequency was 13.56 MHz, the sputter output was 400 to 800 W, and the pressure was 0.5 Pa.

When forming by the reduced pressure gas phase method, it is 450 to 550 ° C., which is 100 to 200 ° C. lower than the crystallization temperature, for example, 5
Disilane (Si ₂ H ₆ ) or trisilane (Si ₃ H ₈ ) was supplied to a CVD apparatus at 30 ° C. to form a film. The reactor pressure is 30 ~
It was set to 300 Pa. The film forming rate was 50 to 250 Å / min. In order to control the threshold voltage (Vth) of the PTFT and that of the NTFT to be approximately the same, boron may be added during film formation using diborane at a concentration of 1 × 10 ¹⁵ to 1 × 10 ¹⁸ cm ^-3. .

The coatings formed by these methods are
It is preferable that oxygen is 5 × 10 ²¹ cm ⁻³ or less. In order to promote crystallization, the oxygen concentration is 7 × 10 ¹⁹ cm ^-3 or less,
It is preferable that the size is 1 × 10 ¹⁹ cm ^-3 or less,
If the amount is too small, the leak current in the off state increases due to the backlight, so this concentration was selected. If the oxygen concentration is high, it is difficult to crystallize, and the laser annealing temperature must be high or the laser annealing time must be long. Hydrogen is 4 × 10 ²⁰ cm ^-3 and silicon is 4 × 10 ²²
It was 1 atom% when compared as cm ^-3 .

In order to further promote crystallization of the source and drain, the oxygen concentration is set to 7 × 10 ¹⁹ cm ^-3 or less, preferably 1 × 10 ¹⁹ cm ^-3 or less, and the TF for forming a pixel is set.
Oxygen may be added only to the channel forming region of T by the ion implantation method so as to have a concentration of 5 × 10 ^{20 to} 5 × 10 ²¹ cm ⁻³ .
By the above method, an amorphous silicon film is formed into 500
The film was formed to a thickness of ˜5000 Å, 1000 Å in this example.

Then, the photoresist 103 is used as a mask P.
1 was used to form a pattern in which only the regions to be the source / drain regions of the NTFT were opened. Then, using the resist 103 as a mask, phosphorus ions are ion-implanted to 2 × 10 ^{14 to} 5 × 10 ¹⁶ cm ⁻² , preferably 2 ×
^Implanting only 10 ¹⁶ cm ⁻² to form the n-type impurity region 104. After that, the resist 103 was removed.

Similarly, a resist 105 was applied, and a mask P2 was used to form a pattern in which only the regions to be the source / drain regions of the PTFT were opened. Then, using the resist 105 as a mask, the p-type impurity region 106 is formed.
Was formed. As the impurities, boroso is used, and also by the ion implantation method, 2 × 10 ^{14 to} 5 × 10 ¹⁶ cm ⁻² ,
Impurities were introduced preferably by 2 × 10 ¹⁶ cm ^-2 .
In this way. 8B is obtained.

After that, a thickness of 50 to 3 is formed on the silicon film 102.
00 nm, for example, 100 nm of silicon oxide film 107
Was formed by the RF sputtering method described above. And
Source / drain / channel regions are crystallized by laser annealing using a XeCl excimer laser.
Activated. The laser energy at this time has a threshold energy of 130 mJ / cm ² , and 220 mJ / cm ² is required for melting the entire film thickness. However, when the energy of 220 mJ / cm ² or more is applied from the beginning, the hydrogen contained in the film is rapidly released, so that the film is broken. Therefore, it is necessary to first drive out hydrogen with low energy and then melt it. In this embodiment, first 1
After expulsion of hydrogen at 50 mJ / cm ² , 23
Crystallization was performed at 0 mJ / cm ² . Further, the silicon oxide film 107 was removed after the laser annealing was completed.

After that, the island-shaped NTFT region 111 and the PTFT region 112 were formed by the photomask P3. A silicon oxide film 108 is formed thereon as a gate insulating film with a thickness of 500 to 2000Å, for example, 1000Å. This was performed under the same conditions as the production of the silicon oxide film as the blocking layer. During this film formation, a small amount of fluorine may be added to immobilize sodium ions.

After this, 1-5 × 10 ²¹ cm of phosphorus is placed on the upper side.
^-3 concentration silicon film or this silicon film with molybdenum (Mo), tungsten (W), MoSi ₂ or
A multilayer film with WSi ₂ was formed. This was patterned with a fourth photomask P4 to obtain FIG. 6 (D). A gate electrode 109 for NTFT and a gate electrode 110 for PTFT were formed. For example, the channel length is 7 μm, the gate electrode is 0.2 μm of phosphorus-doped silicon, and molybdenum is 0.3 μm thick thereon. Although not shown in the drawing, a gate wiring and a wiring parallel to the gate wiring were formed as in the case of the first embodiment.

In addition to the above materials, for example, aluminum (Al) can be used as the material of this wiring. When aluminum is used, the self-alignment method can be applied by patterning this with the fourth photomask P4 and then anodizing the surface, so that the contact holes of the source / drain are closer to the gate. Since it can be formed at a position, the characteristics of the TFT can be further improved by reducing the mobility and the threshold voltage.

In FIG. 8E, the inter-layer insulator 113 was formed as a silicon oxide film by the above-mentioned sputtering method. This silicon oxide film is formed by LPCVD method, photo CVD method.
Method, atmospheric pressure CVD method may be used. For example, 0.2-0.
Formed to a thickness of 6 μm, and then a fifth photomask P
5 was used to form the window 117 for the electrode.

After that, aluminum is further formed on the entire surface to a thickness of 0.3 μm by a sputtering method to form a lead 116 and contacts 114 and 115 using a sixth photomask P6, and then the surface is flattened. A coating organic resin 119, for example, a translucent polyimide resin,
The electrode hole was re-drilled with the seventh photomask P7. Furthermore, ITO (Indium Tin Oxide)
Was formed to a thickness of 0.1 μm by the sputtering method, and the pixel electrode 118 was formed using the eighth photomask P8. This ITO film is formed at room temperature to 150 ° C., and 200 to 400 ° C.
Of oxygen or air in the atmosphere.

The electric characteristics of the obtained TFT are PTFT.
The mobility is 35 (cm ² / Vs), Vth is -5.9 (V),
Mobility is 90 (cm ² / Vs) and Vth is 4.8 with NTFT
(V).

It was possible to obtain one substrate for a liquid crystal electro-optical device manufactured by the above method. Since the method for manufacturing the other substrate is the same as that in the first embodiment, it will be omitted.
Then, the nematic liquid crystal composition was sandwiched between the first substrate and the second substrate, and the periphery was fixed with an epoxy adhesive. A TAB-shaped drive IC, a PCB having a common signal and a potential wiring were connected to the leads on the substrate, and a polarizing plate was attached to the outside to obtain a transmissive liquid crystal electro-optical device. This was connected to a rear lighting device in which three cold cathode tubes were arranged, and a tuner for receiving TV radio waves, to complete a wall-mounted TV. Compared with the conventional CRT type TV, the device has a planar shape, so that it can be installed on a wall or the like. It was confirmed that the operation of this liquid crystal television can display 128 gradations by applying a signal substantially equivalent to that shown in FIGS. 1 and 2 to the liquid crystal pixel.

[0072]

The present invention is characterized in that digital gradation display is performed in contrast to conventional analog gradation display. As an effect, if a liquid crystal electro-optical device having a number of pixels of 640 × 400 dots is assumed, it is very difficult to manufacture the characteristics of all 256,000 TFTs in total without variations. In consideration of mass productivity and yield, 16 gradation display is considered to be the limit, whereas as in the present invention, gradation display is performed by purely digital control without adding any analog signal. By doing so, gradation display of 256 gradations or more became possible. Since it is a completely digital display, T
The gradation ambiguity due to the variation in FT characteristics is completely eliminated, and therefore, even if there is a slight variation in TFT, extremely uniform gradation display was possible. Therefore, in the past, the yield was extremely poor in order to obtain a TFT with little variation, but the yield of the TFT was not so much a problem according to the present invention, so that the yield of the liquid crystal device was improved and the manufacturing cost was significantly suppressed. I was able to.

For example, 256,0 of 640 × 400 dots
When normal analog gradation display is performed on a liquid crystal electro-optical device in which 00 sets of TFTs are formed in a 300 mm square,
Since there is about ± 10% variation in TFT characteristics, 1
6 gradation display was the limit. However, when the digital gray scale display according to the present invention is performed, it is possible to display up to 256 gray scales because it is hardly affected by the characteristic variation of the TFT element, and the color display is 16,777,2.
A wide variety of 16 colors and subtle colors can be displayed. When displaying software such as a television image, for example, even "rocks" of the same color have slightly different shades due to their fine depressions. If you try to display something close to the natural color,
16 gradations are difficult. The gradation display according to the present invention makes it possible to impart these minute color tone changes.

In the embodiment of the present invention, T using silicon is used.
I explained mainly about FT, but T using germanium
FT can be used as well. In particular, single crystal germanium has an electron mobility of 3600 cm ² / Vs and a hole mobility of 1800 cm ² / Vs, which is the value of single crystal silicon (electron mobility is 1350 cm ² / Vs, hole mobility is 480 c).
Since it exceeds the characteristic of m ² / Vs), it is an extremely excellent material for carrying out the present invention which requires high-speed operation. Further, germanium has a lower transition temperature from an amorphous state to a crystalline state than silicon, and is suitable for a low temperature process. Further, the nucleus generation rate during crystal growth is small, and therefore, generally, large crystals are obtained when polycrystal growth is performed. Thus, germanium has characteristics comparable to those of silicon.

In order to explain the technical idea of the present invention, an electro-optical device using liquid crystal, particularly a display device has been described as an example. However, to apply the idea of the present invention, any display device is used. However, it may be a so-called projection type television, other optical switch, or optical shutter. Further, the electro-optical material is not limited to liquid crystal, and it will be apparent that the present invention can be applied as long as the optical characteristics change due to electrical influences such as electric field and voltage.

[Brief description of drawings]

FIG. 1 shows an example of drive waveforms according to the present invention.

FIG. 2 shows an example of drive waveforms according to the present invention.

FIG. 3 shows an example of drive waveforms according to the present invention.

FIG. 4 shows an example of a matrix configuration according to the present invention.

FIG. 5 shows a planar structure of a device according to an example.

FIG. 6 shows a process of a TFT according to an example.

FIG. 7 shows a process of a color filter according to an embodiment.

FIG. 8 shows a process of a TFT according to an example.

FIG. 9 shows a connection example of a protection circuit in the embodiment.

FIG. 10 shows an example of a protection circuit in the embodiment.

FIG. 11 shows an example of a protection circuit in the embodiment.

─────────────────────────────────────────────────── ───

[Procedure amendment]

[Submission date] July 30, 1993

[Procedure Amendment 1]

[Document name to be amended] Statement

[Name of item to be corrected] Brief description of the drawing

[Correction method] Change

[Correction content]

[Brief description of drawings]

FIG. 1 shows an example of drive waveforms according to the present invention.

FIG. 2 shows an example of drive waveforms according to the present invention.

FIG. 3 shows an example of drive waveforms according to the present invention.

FIG. 4 shows an example of a matrix configuration according to the present invention.

FIG. 5 shows a planar structure of a device according to an example.

FIG. 6 shows a process of a TFT according to an example.

FIG. 7 shows a process of a TFT according to an example.

FIG. 8 shows a process of a color filter according to an example.

FIG. 9 shows a process of a TFT according to an example.

FIG. 10 shows a connection example of a protection circuit in the embodiment.

FIG. 11 shows an example of a protection circuit in the embodiment.

FIG. 12 shows an example of a protection circuit in the embodiment.

[Procedure Amendment 2]

[Document name to be corrected] Drawing

[Correction target item name] All drawings

[Correction method] Change

[Correction content]

[Figure 1]

[Fig. 2]

[Figure 8]

FIG. 11

[Figure 3]

[Figure 4]

[Figure 5]

[Figure 6]

[Fig. 12]

[Figure 7]

[Figure 9]

[Figure 10]

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Yasuhiko Takemura 398 Hase, Atsugi, Kanagawa Prefecture Semiconductor Energy Research Institute Co., Ltd.

Claims (1)

[Claims] 1. N signal lines X _1, X _{2 ,} .. X _n, .. on a substrate.
X _N and M signal lines Y _1, Y _2, ..Y _m, ..
Y _M in a matrix form, at least two N-channel type thin film transistors and at least two P-channel type thin film transistors in the intersection area of each matrix, and a pixel Z provided in the intersection area of each signal line. _, Z ₁₂ , ... Z _mn , ... Z _MN, and the first N
The input / output ends of the channel type thin film transistor and the first P-channel type thin film transistor are connected, this is connected to the pixel electrode, and the other input / output ends are respectively connected to the input / output end of the second P-channel type thin film transistor, 2 is connected to the input / output terminal of the N-channel type thin film transistor, and the other input / output terminal of the second P-channel type thin film transistor is connected to the other of the signal lines Y _1, Y _2, ..Y _m, ..Y _M connected to one signal line Y _m, the other input terminal of the second N-channel thin film transistor, provided next to the signal line Y _m, the signal lines Y _1, Y _2, ..Y _{m ,} .. Y _M one signal line Y _{m + 1}
Of the signal lines X _1, X _2, ..X _n, ..X _N of the first P-channel type thin film transistor and the first N-channel type thin film transistor are commonly connected. The gate electrode of the second P-channel type thin film transistor is connected to the signal line Y _{m + 1,} and the gate electrode of the second N-channel type thin film transistor is connected to the signal line Y _m . In the electro-optical device, in the pulse applied to the arbitrary signal line Y _m , the i-th and (i
The image display method of the electro-optical device, wherein the interval of the +1) th pulse is represented by 2 ^i-1 T ₁ (i is a finite natural number and T ₁ is a constant).