JP3380513B2 - Display device, television, liquid crystal display device, and projection display device - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image display method in a liquid crystal electro-optical device using a thin film transistor (hereinafter referred to as a TFT) as a switching element for driving, and in particular, a gradation display for obtaining an intermediate color tone or gradation expression. It is about the method. The present invention particularly relates to so-called fully digital gradation display, which performs gradation display without applying any analog signal from the outside to the active element.

[0002]

2. Description of the Related Art Due to its material properties, liquid crystal compositions have different permittivities in the horizontal and vertical directions with respect to the molecular axis, so that they can be aligned horizontally or vertically with respect to external electrolysis. It can be done easily. The liquid crystal electro-optical device utilizes the anisotropy of the dielectric constant to control the amount of transmitted light or the amount of scattered light, thereby performing ON / OFF, that is, bright / dark display. Liquid crystal materials include TN (Twisted Nematic) liquid crystal, STN (Super
Materials called twisted nematic) liquid crystal, ferroelectric liquid crystal, polymer liquid crystal, or dispersion type liquid crystal are known. It is known that liquid crystal does not respond to an external voltage in an infinitely short time, but it takes a certain time to respond. The value is unique to each liquid crystal material. In the case of TN liquid crystal, it is several tens of msec, ST
In the case of N liquid crystal, it is several 100 msec, in the case of ferroelectric liquid crystal, it is several 10 μsec, and in the case of dispersion type or polymer liquid crystal, it is several 10 msec.

Among electro-optical devices using liquid crystals, the one which can obtain the most excellent image quality is one using the active matrix system. In a conventional active matrix type liquid crystal electro-optical device, a thin film transistor (TFT) is used as an active element, an amorphous or polycrystalline semiconductor is used for the TFT, and P is used for one pixel.
The TFT of only one of the N type and the N type was used. That is, in general, N-channel TFT
(Referred to as NTFT) is connected in series to the pixel. Then, a signal voltage is applied to the signal lines of the matrix, and when signals are applied from both sides to the TFTs provided at the orthogonal positions of the respective signal lines, the TFTs are turned on. It was to control OFF individually. By controlling the pixels by such a method, a liquid crystal electro-optical device having a large contrast can be realized.

[0004]

However, in such an active matrix system, it is extremely difficult to perform gradation display such as brightness and color tone. Conventionally, a method of utilizing the fact that the light transmittance of the liquid crystal changes depending on the magnitude of the applied voltage has been studied for gradation display. This is, for example, the source of the TFT in the matrix
By supplying an appropriate voltage from the peripheral circuit between the drains and applying a signal voltage to the gate electrode in that state,
It was intended to apply a voltage of that magnitude to the liquid crystal pixels.

However, in such a method, the voltage applied to the liquid crystal pixel actually varies from pixel to pixel by at least several percent due to, for example, the non-uniformity of the TFT and the non-uniformity of the matrix wiring. Oops. On the other hand, for example, the voltage dependence of the light transmittance of liquid crystal is extremely non-linear, and the light transmittance changes abruptly at a certain voltage. It could be significantly different. Therefore, actually, it was a limit to achieve 16 gradations.

The difficulty of gradation display is extremely disadvantageous in that the liquid crystal display device competes with the CRT (cathode ray tube) which is a conventional general display device.

An object of the present invention is to propose a completely new method for realizing gradation display which has been difficult in the past.

[0008]

As described above, it is possible to control the light transmissivity of the liquid crystal by controlling the voltage applied to the liquid crystal in an analog manner. It has been found that the gradation can be visually obtained by controlling the time when voltage is applied to the liquid crystal.

For example, in the case of using TN (twisted nematic) liquid crystal which is a typical liquid crystal material,
For example, in FIG. 1A, it is found that A is brighter when comparing the case of applying the rectangular pulse as shown by A and the case of applying the rectangular pulse as shown by C. . Here, the pulse cycle was 1 msec. As a result, A was the brightest, followed by B, C, and D in that order. This is totally unexpected. This is because in the above-mentioned normal TN liquid crystal material, 1 ms
The time ec is too short, and the TN liquid crystal does not react in such a short time. Therefore, in any case, it should be impossible for the liquid crystal to realize the ON state. However, in reality, the liquid crystal could achieve an intermediate density.

The specific principle is not yet known in detail. However, the inventors of the present invention have found out that gradation expression is possible by utilizing this phenomenon. That is, it is exactly a feature of the present invention that the intermediate brightness is realized by digital control by controlling the pulse width when the pulse is applied to the liquid crystal material in a cycle such that the liquid crystal material does not react. It is a thing. As a result of studies by the present inventors, it was found that the pulse period for obtaining such an intermediate concentration needs to be 10 msec or less in the case of TN liquid crystal.

Here, the meaning of the term pulse period will be clarified. That is, in this case,
A plurality of pulses are continuously applied to the liquid crystal, and the pulse cycle in this case means the time from the start of one pulse to the start of the next pulse.
Therefore, it is the reciprocal of the pulse repetition frequency. The pulse width refers to the time during which the pulse is in the voltage state. Therefore, in FIG. 1, for example, in the case of a pulse train of C, T is the pulse period and τ is the pulse width.

Similar effects were found in STN liquid crystals, ferroelectric liquid crystals, and polymer liquid crystals or dispersion liquid crystals. In each case, it was revealed that an intermediate color tone can be obtained by applying a pulse having a period shorter than the response time. That is, S
For TN liquid crystal, 100 msec or less, preferably 10 msec or less, and 10 μs for ferroelectric liquid crystal.
Gradation display was obtained by applying a pulse with a period of ec or less, preferably 1 μsec or less, a polymer liquid crystal or dispersion type liquid crystal of 10 msec or less, and preferably 1 msec or less.

Normally, in the case of images on a television or the like, it is 30 per second.
A still image is fed one after another to form a moving image. Therefore, the duration of one still image is about 30 msec.
Is. This time is too early for human eyes,
The time is literally "still in the eye", and as a result, still images cannot be visually identified one by one. In any case, in order to obtain a normal moving image, one still image cannot be continued for 100 msec or longer even if it is long.

If gradation display of 256 gradations is performed using the present invention, for example, if T = 3 msec,
It is necessary to adopt a pulse voltage application method capable of dividing this 3 msec time into at least 256 as a method for applying a voltage to the pixel. That is, the shortest is 3 msec /
It is necessary to construct a circuit in which a pulsed voltage of 256 = 11.7 μsec is applied to the pixel. Actually, as shown in FIG. 3, the duty ratio τ / T of the pulse and the light transmissivity of the liquid crystal pixel are in a non-linear relationship, and in order to obtain 256 gradations, the duty ratio of the pulse is further changed. Fine control is required.

Moreover, when actually displaying an image, other pixels must be taken into consideration. In an actual image display device, there are as many as 400 lines. That is,
As will be described later, the matrix has 10 active elements.
An extremely short response time of 0 nsec is required. Therefore, an example of a circuit having such a short time response is shown in FIG.
This will be described below.

FIG. 4 shows an example of an active matrix circuit of a liquid crystal display device necessary for implementing the present invention. In the present invention, since the active element is required to respond in a short time of 100 nsec or less, it is necessary to build a circuit that operates at high speed. For that purpose, it is necessary to use a modified buffer type circuit configured so that the NTFT and the PTFT operate complementarily as shown in FIG. 4, instead of performing switching only by the NTFT or the PTFT as in the conventional case. is necessary.

In this example, an example of an N × M matrix is shown, but in order to avoid complexity, n of them is used.
Only the vicinity of row m column is shown. If you expand the same thing up, down, left and right, you can get the perfect one.

In FIG. 4, four modified buffer circuits are depicted. Each modified buffer circuit is composed of at least two NTFTs and at least two PTFTs.
The number of TFTs may be further increased in case there is a defect. In this circuit, first, the gate electrodes of a set of NTFT and PTFT in the central portion are connected, and further connected to the signal line X _n , and one of the source and drain of the NTFT and PTFT is connected to each other, which is the pixel. It is connected to the Z _{n, m} electrode. This state is the same as in a normal complementary field effect element (CMOS). This NT
The other source or drain of the FT and PTFT is connected to the source or drain of the second PTFT or NTFT, respectively. Also, this second PT
The other sources or drains of the FT and NTFT are connected to the signal lines Y _m and Y _{m + 1} , respectively. Further, the gate electrodes of the second PTFT and NTFT are connected to the signal lines Y _{m + 1} and Y _m , respectively. Below,
Signal lines X _1, X _2, a _.. X _N, collectively, or individually X
Signal lines Y _1, Y _{2, ...,} Y _M are collectively or individually referred to as Y lines. Also, in the figure, a capacitor is artificially inserted in parallel with my capacitor. The capacitor inserted at this time has a function of suppressing the voltage of the pixel from dropping due to the natural discharge of the pixel. Since the effective speed of the voltage of the pixel is determined by the variation of the pixel, the deterioration of the image quality is caused particularly in the invention for performing the gradation display with the voltage applied to the pixel being constant as in the present invention. It is an invitation. However, by inserting a capacitor in parallel with the pixel like this,
The voltage effect due to pixel variation can be significantly suppressed, and high image quality can be obtained.

Next, an operation example of a circuit using such a circuit will be described with reference to FIGS. 1 (b) and 2. This matrix circuit needs to operate so as to apply a pulsed voltage to the liquid crystal cell as shown in FIG. Therefore, an outline of the signal voltage applied to the X-ray and the Y-ray to generate such a pulse is shown in FIG. As an example, consider a 400 × 640 matrix.

The signal applied to the X-ray is represented by V (X _n ), for example, in the case of the X _n line, which is actually 256 in a group of pulses repeated in the period T. Pulse (hereinafter referred to as sub-pulse) is included,
Further, each of the 256 sub-pulses has 400
It can be seen that it is composed of a pulse train containing individual elements. Here, the number 400 is the number of rows in the matrix. Therefore, when the minimum unit of the pulse applied to the X-ray is T = 3 msec, it is 29 nsec.

On the other hand, for the Y line, during the time T / 256,
V (Y ₁ ), V (Y _m ), V (Y _{m + 1} ), V (Y
Pulses such as those indicated by ₄₀₀ ) are applied at different timings. This pulse needs to be shorter than the minimum unit pulse of the pulse applied to the X-ray. Eventually, during time T, each Y line is pulsed 256 times.

Next, the operation of the actual circuit will be described with reference to FIG.
explain. First, the first sub-pulse is applied to each X-ray
Is applied. Naturally, these subpulses
Different for each X-ray. On the other hand, for the Y line, as described above
And the pulse is Y first₁, Then Y₂And so on
It is applied. First, the pulse is Y₁When applied to
think of. At this time, the pixel Z_1,1Connected to the
The active element is turned on. That is, Y₁Is the voltage
State and Y₂Is not in the voltage state, the pixel
Of the four TFTs of the active element, the upper NTFT and the lower
PTFT is turned on and the central buffer operates
Is ready to go. And the buffer input X₁There is no electricity
Since the pressure is applied, the output is in the same voltage state as the input.
Become. And this voltage state is Y₁The pulse of
Continue, then Y again₁Hold until pulse is applied to
To continue. Then Y₂Voltage is applied to the
When pixel Z_1,2No voltage is applied to it. You
That is, buffer input X ₁No voltage is applied to
Because it is. As described above, voltage is applied to each pixel.
Or not. Z_{1, m}And Z_1,400Is the voltage
It becomes a state. Z_{1, m + 1}Does not enter the voltage state.

Consider the case where the pulses are sequentially applied in this manner and applied to Y _m . Now, if attention is paid to the four pixels Z _{n, m} , Z _{n, m + 1} , Z _{n + 1, m} , and Z _{n + 1, m + 1} , the pixels of X _n and X _{n + 1} It suffices to focus on the m-th and (m + 1) -th sub-pulses of 1. Since the m-th voltage state of both X _n and X _{n + 1} is the pixel Z _{n, m} , Z _{n +
1, m} becomes voltage (charge) state. Then, a pulse is applied to Y _{m + 1} . Since the (m + 1) th voltage state of both X _n and X _{n + 1} is the voltage state, the pixels Z _{n, m + 1} and Z _{n + 1, m + 1} are also charged in this case.

Next, although not shown in the figure, it is assumed that the second sub-pulse comes. At this time, if the m-th and (m + 1) -th voltage states of both X _n and X _{n + 1} are voltage states, the charged state is not lost, and the above four pixels continue to be in the voltage state. Then, until the (h-1) th sub-pulse,
It is assumed that the voltage state of all four pixels has continued.

Next, it is assumed that the sub-pulse advances and the h-th sub-pulse comes. In the figure, m to avoid complexity
The other than the 1st and (m + 1) th are omitted. At this time,
Since the m-th voltage state of both X _n and X _{n + 1} is the pixel Z
_{n, m} and Z _{n + 1, m} continue the voltage state. However, X _{n + 1}
Since the (m + 1) th pixel is not in the voltage state, the pixel Z _{n + 1,}
Although the voltage state of _m continues, the output of the active element of the pixel Z _{n + 1, m + 1} is not in the voltage state, the accumulated charge is discharged, and the voltage state is interrupted.

Furthermore, when the i-th sub-pulse arrives, the (m + 1) th X _n is no longer in the voltage state, so that the charged state of Z _{n, m + 1} is released. Hereinafter, in the j-th and k-th sub-pulses, X _{n + 1} and X _n , respectively.
The m-th pixel in the pixel is no longer in the voltage state, and the pixels Z _{n, m} and Z _{n + 1, m}
Charging states are interrupted during the kth and jth sub-pulses, respectively. Through such a process, the time of the voltage state can be digitally controlled for each pixel as shown by V (Z) in FIG.

By repeating such an operation, the width of the voltage pulse applied to each pixel can be arbitrarily controlled as shown in FIG.

As is apparent from the above description, in carrying out the present invention, the above sub-pulses do not have to be clearly defined pulse-like. In order to simplify the explanation, the concept of a sub-pulse has been introduced, but it is clear that the present invention can be carried out even if the signal between the sub-pulses is not clear and there is almost no boundary as a signal. is there. Further, the zero level and the voltage level of the signal are clarified to make the explanation easy to understand, but this is only the problem of being below or above the threshold voltage of the liquid crystal or TFT. It does not have to be zero. Further, since the voltage is a relative physical quantity with reference to the potential at an arbitrary point, it will be apparent that the pulses may have opposite polarities in the above examples. Furthermore, an appropriate offset voltage may be applied to the counter electrode of the pixel. Especially in the case of ferroelectric liquid crystal,
Since the liquid crystal is switched depending on the direction of the voltage applied to the liquid crystal, the voltage ON / OFF as described above is performed.
When it is OFF, the liquid crystal cannot be controlled. In such cases,
By applying an appropriate bias voltage to the counter electrode, it is possible to reverse the voltage applied to the liquid crystal as a result. Further, in the above example, the method of scanning one line at a time is shown. However, for example, the scanning is first performed as Y _1, Y _3, Y _{5, ...} And then Y _2, Y _4, Y _{6 is} scanned and so on _.., of course methods it is possible so-called interlaced scanning.

[0029]

[Embodiment] [Embodiment 1] In this embodiment, a wall-mounted television is manufactured using a liquid crystal display device having a circuit configuration as shown in FIG. Also TF at that time
T is polycrystalline silicon using laser annealing.

The actual arrangement of electrodes and the like corresponding to this circuit structure is shown in FIG. 5 for one pixel. First, a method for manufacturing a liquid crystal panel used in this example will be described with reference to FIGS. In order to carry out the present invention, two NTFTs and two PTFTs are required for one pixel.
Although a total of four TFTs are shown in the figure, for simplification, the number is attached to only one of the NTFT and the PTFT. Figure 6
In (A), a silicon oxide film as a blocking layer 51 is formed on a glass 50, such as quartz glass, which can withstand a heat treatment at 700 ° C. or less, for example, about 600 ° C.
It is made to a thickness of 0Å. The process conditions were an atmosphere of 100% oxygen, a film forming temperature of 150 ° C., an output of 400 to 800 W, and a pressure of 0.5 Pa. The film formation rate using quartz or single crystal silicon for the target was 30 to 100 Å / min.

A silicon film 52 was formed on this by a plasma CVD method. The film forming temperature is 250 ° C. to 35
The temperature is set to 0 ° C., and in this embodiment, the temperature is set to 320 ° C. and monosilane (SiH
₄ ) was used. Not only monosilane (SiH ₄ ) but also disilane (Si ₂
H ₆ ) Alternatively, trisilane (Si ₃ H ₈ ) may be used. These were introduced into the PCVD device at a pressure of 3 Pa, and 13.56M
A high frequency power of Hz was applied to form a film. At this time, the high frequency power is suitably 0.02 to 0.10 W / cm ² , and in this example, 0.055 W / cm ² was used. The flow rate of monosilane (SiH ₄ ) was 20 SCCM, and the film formation rate at that time was about 120 Å / min. In order to control the threshold voltage (Vth) of the PTFT and the NTFT to be approximately the same, boron is used in an amount of 1 × 10 ¹⁵ to 1 × 10 ¹⁸ cm by using diborane.
^-3 may be added during film formation. Further, not only the plasma CVD but also the sputtering method or the low pressure CVD method may be used for forming the silicon layer to be the channel region of the TFT. The method will be briefly described below.

When the sputtering method is used, the back pressure before the sputtering is set to 1 × 10 ^-5 Pa or less, the single crystal silicon is used as the target, and the atmosphere is mixed with 20% to 80% of hydrogen in argon. For example, argon is 20% and hydrogen is 80%.
The film forming temperature was 150 ° C., the frequency was 13.56 MHz, the sputter output was 400 to 800 W, and the pressure was 0.5 Pa.

When formed by the reduced pressure vapor phase method, the temperature is 450 to 550 ° C., which is 100 to 200 ° C. lower than the crystallization temperature, for example, 5
Disilane (Si ₂ H ₆ ) or trisilane (Si ₃ H ₈ ) was supplied to a CVD apparatus at 30 ° C. to form a film. The reactor pressure is 30 ~
It was set to 300 Pa. The film forming rate was 50 to 250 Å / min. In order to control the threshold voltage (Vth) of the PTFT and that of the NTFT to be approximately the same, boron may be added during film formation using diborane at a concentration of 1 × 10 ¹⁵ to 1 × 10 ¹⁸ cm ^-3. .

The coatings formed by these methods are
It is preferable that oxygen is 5 × 10 ²¹ cm ⁻³ or less. In order to promote crystallization, the oxygen concentration is 7 × 10 ¹⁹ cm ^-3 or less,
It is preferable that the size is 1 × 10 ¹⁹ cm ^-3 or less,
If the amount is too small, the leak current in the off state increases due to the backlight, so this concentration was selected. If the oxygen concentration is high, it is difficult to crystallize, and the laser annealing temperature must be high or the laser annealing time must be long. Hydrogen is 4 × 10 ²⁰ cm ^-3 and silicon is 4 × 10 ²²
It was 1 atom% when compared as cm ^-3 .

In order to further promote crystallization of the source and the drain, the oxygen concentration is set to 7 × 10 ¹⁹ cm ^-3 or less, preferably 1 × 10 ¹⁹ cm ^-3 or less, and the TF constituting the pixel is formed.
Oxygen may be added only to the channel forming region of T by the ion implantation method so as to have a concentration of 5 × 10 ^{20 to} 5 × 10 ²¹ cm ⁻³ .
By the above method, an amorphous silicon film is formed into 500
The film was formed to a thickness of ˜5000 Å, 1000 Å in this example.

After that, the photoresist 53 is used as a mask P1.
Was used to form a pattern in which only the source / drain regions were opened. A silicon film 54, which will be an n-type active layer, was formed thereon by a plasma CVD method. Film formation temperature is 250 ° C
The temperature is set to 320 ° C. in this embodiment, and monosilane (SiH ₄ ) and monosilane-based phosphine (P
H ₃ ) with 3% concentration was used. These were introduced into the PCVD apparatus at a pressure of 5 Pa, and high frequency power of 13.56 MHz was applied to form a film. At this time, the high frequency power is 0.05 to
0.20 W / cm ² is suitable, and is 0.1 in this embodiment.
20 W / cm ² was used.

The specific conductivity of the n-type silicon layer produced by this method was about 2 × 10 ^-1 [Ωcm ^-1 ]. The film thickness was 50Å. After that, the lift-off method is used to remove the resist 53, and the source / drain regions 5 are removed.
5, 56 were formed.

A p-type active layer was formed using the same process. The gas introduced at this time was a monosilane (SiH ₄ ) and monosilane-based diborane (B ₂ H ₆ ) concentration of 5%. These were introduced into a PCVD device at a pressure of 4 Pa, and high frequency power of 13.56 MHz was applied to form a film.
At this time, the high-frequency power is suitably 0.05~0.20W / cm ^2, in this embodiment using 0.120W / cm ^2. The specific conductivity of the p-type silicon layer produced by this method was about 5 × 10 ^-2 [Ωcm ^-1 ]. The film thickness was 50Å. After that, the source / drain regions 59 and 60 were formed by using the lift-off method similarly to the N-type region.
Then, the silicon film 52 was removed by etching using the mask P3 to form an N-channel type thin film transistor island region 63 and a P-channel type thin film transistor island region 64.

After that, the source / drain / channel regions were laser-annealed using a XeCl excimer laser, and at the same time, laser doping was performed on the active layer. The laser energy at this time has a threshold energy of 130 mJ / cm ² , and 220 for melting the entire film thickness.
mJ / cm ² is required. However, 220m from the beginning
When the energy of J / cm ² or more is applied, hydrogen contained in the film is rapidly released, so that the film is broken. Therefore, it is necessary to first drive out hydrogen with low energy and then melt it. In this embodiment, first 150 m
After ejecting hydrogen at J / cm ² , 230mJ
Crystallization was performed at / cm ² .

On this, a silicon oxide film was formed as a gate insulating film to a thickness of 500 to 2000Å, for example 1000Å. This was performed under the same conditions as the production of the silicon oxide film as the blocking layer. During this film formation, a small amount of fluorine may be added to immobilize sodium ions.

Thereafter, phosphorus is added to the upper side in an amount of 1 to 5 × 10 ²¹
A silicon film having a concentration of cm ⁻³ or this silicon film and a multilayer film of molybdenum (Mo), tungsten (W), MoSi ₂ or WSi ₂ was formed on the silicon film. This was patterned with a fourth photomask P4 to obtain FIG. 6 (D). NT
Gate electrode 66 for FT, gate electrode 67 for PTFT
Was formed. For example, the channel length is 7 μm, the gate electrode is 0.2 μm of phosphorus-doped silicon, and molybdenum is 0.3 μm thick thereon. At the same time, as shown in FIG. 7A, the gate wiring and the wiring 68 arranged in parallel therewith were also patterned.

When aluminum (Al) is used as the gate electrode material, the self-alignment method can be applied by patterning this with the fourth photomask P4 and then anodizing the surface. Since the source / drain contact holes can be formed at positions closer to the gate, the characteristics of the TFT can be further improved by reducing the mobility and the threshold voltage.

In this way, a C / TFT can be manufactured without applying a temperature above 400 ° C. in all steps. Therefore, an expensive substrate such as quartz does not have to be used as the substrate material, and it can be said that the process is extremely suitable for the large-screen liquid crystal display device of the present invention.

In FIG. 6E, the inter-layer insulator 69 was formed as a silicon oxide film by the above-mentioned sputtering method. This silicon oxide film is formed by LPCVD method, photo CVD method.
Method, atmospheric pressure CVD method may be used. For example, 0.2-0.
Formed to a thickness of 6 μm, and then a fifth photomask P
5 was used to form the window 79 for the electrode. After that, aluminum was further formed on the entire surface by a sputtering method to a thickness of 0.3 μm, and a lead 74 and contacts 73 and 75 were formed using a sixth photomask P6. Thus, FIG. 6E and FIG. 7B were obtained. After that, an organic resin 77 for flattening the surface, for example, a light-transmissive polyimide resin is applied and formed, and electrode holes are formed again by the seventh photomask P.
I went to 7. Further, ITO (Indium Tin Oxide) was formed on the whole of these by a sputtering method to a thickness of 0.1 μm, and the pixel electrode 71 was formed using the eighth photomask P8. This ITO film is formed at room temperature to 150 ° C.
It was accomplished by oxygen at 400 ° C or by annealing in air.

Thus, FIG. 6 (F) and FIG. 7 (C) were obtained. A cross-sectional view taken along the line AA ′ of FIG. 7C is shown in FIG. Actually, a counter electrode is provided on top of this with a liquid crystal material interposed therebetween, and as shown in the figure, a capacitance is generated between the counter electrode and the electrode 71. At the same time, electrostatic capacitance is generated between the wiring 68 and the electrode 71. Then, by keeping the wiring 68 at the same potential as the counter electrode, as shown in FIG. 4, a circuit in which a capacitor is inserted in parallel with the liquid crystal pixel is configured. In particular, by arranging as in this embodiment, since the wiring 68 is parallel to the gate wiring 65, the parasitic capacitance between the two wirings is small, and therefore, there is an effect of reducing the attenuation or delay of the signal transmitted through the gate wiring.

In addition, the wiring 68 formed in this way
When used by being grounded, can be used as a ground line of a protection circuit provided at the end of each matrix. As shown in FIG. 10, the protection circuit is provided between a peripheral drive circuit and a pixel, and is a circuit as shown in FIGS. 11 and 12. In both cases, when an excessive voltage is applied to the wiring of the pixel, it is turned on and has the action of removing the voltage. These protection circuits are constructed using a doped or undoped semiconductor material such as silicon, a transparent conductive material such as ITO, or a normal wiring material. Therefore, the pixel circuits can be formed at the same time when they are formed.

This means that, for example, each protection circuit shown in FIG. 11 has an NTFT, a PTFT, or a C in which they are combined.
It will be clear from the fact that it is composed of / TFT. Although the protection circuit of FIG. 12 does not use a TFT, the diode is composed of, for example, a PIN junction, and the diode which attaches particular importance to the Zener characteristic is N.
It is obvious that it has a structure such as IN, PIP, NPN, or PNP, and it can be manufactured by applying the manufacturing method shown in this embodiment without needing to describe it one by one.

The electric characteristics of the TFT thus obtained are PTFT and have a mobility of 40 (cm ² / Vs) and Vth.
Is -5.9 (V), the mobility is 80 (cm ² / V with NTFT)
s) and Vth were 5.0 (V).

It was possible to obtain one substrate for a liquid crystal electro-optical device manufactured according to the above method. FIG. 5 shows how electrodes and the like of this liquid crystal display device are arranged.
Complementary TFT constituting a deformation buffer according to the present invention
(C / TFT) is provided between the signal lines Y ₁ and Y ₂ and between the signal lines Y ₂ and Y ₃ in parallel with the signal lines X ₁ and X ₂ . A matrix structure using such C / TFT is provided. By repeating this structure horizontally and vertically, a liquid crystal display device with large pixels of 640 × 480 and 1280 × 960 can be obtained. In this embodiment, 19
It was set to 20 × 400. Thus, the first substrate was obtained.

A method of manufacturing the other substrate is shown in FIG. A polyimide resin in which a black pigment is mixed with polyimide is formed on a glass substrate to a thickness of 1 μm by a spin coating method,
Black stripe 8 using the ninth photomask P9
1 was produced. Then, a polyimide resin mixed with a red pigment is formed into a film having a thickness of 1 μm by a spin coating method,
Red filter 8 using the tenth photomask P10
3 was produced. Similarly, using the masks P11 and P12, a green filter 85 and a blue filter 86 were produced. During manufacture of these filters, each filter was baked at 350 ° C. in nitrogen for 60 minutes. After that, the leveling layer 89 was made of transparent polyimide by using the spin coating method.

After that, ITO (Indium Tin Oxide) was formed on the whole of the above to a thickness of 0.1 μm by the sputtering method, and the common electrode 90 was formed using the tenth photomask P10. This ITO film is formed at room temperature to 150 ° C.
The second substrate was obtained by the conditions of 0 to 300 ° C. oxygen or annealing in air.

A polyimide precursor was printed on the substrate by the offset method, and baked at 350 ° C. for 1 hour in a non-oxidizing atmosphere such as nitrogen. Then, a known rubbing method was used to modify the surface of the polyimide, and a means for orienting liquid crystal molecules in a certain direction was provided at least in the initial stage.

Then, the nematic liquid crystal composition was sandwiched between the first substrate and the second substrate, and the periphery was fixed with an epoxy adhesive. A TAB-shaped drive IC, a PCB having a common signal and a potential wiring were connected to the leads on the substrate, and a polarizing plate was attached to the outside to obtain a transmissive liquid crystal electro-optical device. This was connected to a rear lighting device in which three cold cathode tubes were arranged, and a tuner for receiving TV radio waves, to complete a wall-mounted TV. Compared with the conventional CRT type TV, the device has a planar shape, so that it can be installed on a wall or the like. The operation of this liquid crystal television was confirmed by applying a signal substantially equivalent to that shown in FIGS. 1 and 2 to the liquid crystal pixel.

[Embodiment 2] In this embodiment, a wall-mounted television is manufactured using a liquid crystal display device having a circuit configuration as shown in FIG. 4, which will be described. Also T at that time
FT was polycrystalline silicon using laser annealing.

In the following, a method of manufacturing the TFT portion will be described with reference to FIG. In FIG. 9 (A), it is less expensive than quartz glass such as 700 ° C. or less, for example, about 600 ° C.
Magnetron RF on glass 100 that can withstand the heat treatment of
(High frequency) Blocking layer 101 using a sputtering method
To form a silicon oxide film having a thickness of 1000 to 3000 Å. The process conditions were an atmosphere of 100% oxygen, a film forming temperature of 15 ° C., an output of 400 to 800 W, and a pressure of 0.5 Pa. The film formation rate using quartz or single crystal silicon for the target was 30 to 100 Å / min.

A silicon film 102 was formed on this by a plasma CVD method. Film formation temperature is 250 ° C to 3
It is carried out at 50 ° C., and in this embodiment 320 ° C., and monosilane (S
iH ₄ ) was used. Not only monosilane (SiH ₄ ) but also disilane (S
i ₂ H ₆ ) or trisilane (Si ₃ H ₈ ) may be used. These were introduced into the PCVD device at a pressure of 3 Pa, and 13.56
A high frequency power of MHz was applied to form a film. At this time, the high frequency power is suitably 0.02 to 0.10 W / cm ² , and in this example, 0.055 W / cm ² was used. The flow rate of monosilane (SiH ₄ ) was 20 SCCM, and the film formation rate at that time was about 120 Å / min. In order to control the threshold voltage (Vth) of the PTFT and the NTFT to be approximately the same, boron is used in an amount of 1 × 10 ¹⁵ to 1 × 10 ¹⁸ by using diborane.
It may be added as a concentration of cm ⁻³ during film formation. Also TFT
In addition to the plasma CVD, a sputtering method or a low pressure CVD method may be used for forming the silicon layer to be the channel region of the above. The method will be briefly described below.

In the case of the sputtering method, the back pressure before the sputtering was set to 1 × 10 ^-5 Pa or less, the single crystal silicon was used as the target, and the atmosphere was mixed with 20% to 80% of hydrogen in argon. For example, argon is 20% and hydrogen is 80%.
The film forming temperature was 150 ° C., the frequency was 13.56 MHz, the sputter output was 400 to 800 W, and the pressure was 0.5 Pa.

When forming by the reduced pressure vapor phase method, it is 450 to 550 ° C., which is 100 to 200 ° C. lower than the crystallization temperature, for example, 5
Disilane (Si ₂ H ₆ ) or trisilane (Si ₃ H ₈ ) was supplied to a CVD apparatus at 30 ° C. to form a film. The reactor pressure is 30 ~
It was set to 300 Pa. The film forming rate was 50 to 250 Å / min. In order to control the threshold voltage (Vth) of the PTFT and that of the NTFT to be approximately the same, boron may be added during film formation using diborane at a concentration of 1 × 10 ¹⁵ to 1 × 10 ¹⁸ cm ^-3. .

The film formed by these methods is
It is preferable that oxygen is 5 × 10 ²¹ cm ⁻³ or less. In order to promote crystallization, the oxygen concentration is 7 × 10 ¹⁹ cm ^-3 or less,
It is preferable that the size is 1 × 10 ¹⁹ cm ^-3 or less,
If the amount is too small, the leak current in the off state increases due to the backlight, so this concentration was selected. If the oxygen concentration is high, it is difficult to crystallize, and the laser annealing temperature must be high or the laser annealing time must be long. Hydrogen is 4 × 10 ²⁰ cm ^-3 and silicon is 4 × 10 ²²
It was 1 atom% when compared as cm ^-3 .

In order to further promote crystallization of the source and drain, the oxygen concentration is set to 7 × 10 ¹⁹ cm ^-3 or less, preferably 1 × 10 ¹⁹ cm ^-3 or less, and the TF for forming a pixel is set.
Oxygen may be added only to the channel forming region of T by the ion implantation method so as to have a concentration of 5 × 10 ^{20 to} 5 × 10 ²¹ cm ⁻³ .
By the above method, an amorphous silicon film is formed into 500
The film was formed to a thickness of ˜5000 Å, 1000 Å in this example.

Then, the photoresist 103 is used as a mask P.
1 should be used as the source / drain region of NTFT
A pattern was formed in which only the area was opened. And Regis
Ion implantation of phosphorus ions using mask 103 as mask
From 2 x 10¹⁴~ 5 x 10 ¹⁶cm^-2, Preferably 2x
10¹⁶cm^-2Just implant and form the n-type impurity region 104.
I made it. After that, the resist 103 was removed.

Similarly, a resist 105 was applied, and a mask P2 was used to form a pattern in which only the regions to be the source / drain regions of the PTFT were opened. Then, using the resist 105 as a mask, the p-type impurity region 106 is formed.
Was formed. As the impurities, boroso is used, and also by the ion implantation method, 2 × 10 ^{14 to} 5 × 10 ¹⁶ cm ⁻³ ,
Impurities were introduced preferably by 2 × 10 ¹⁶ cm ⁻³ .
Thus, FIG. 9B was obtained.

After that, a thickness of 50 to 3 is formed on the silicon film 102.
00 nm, for example, 100 nm of silicon oxide film 107
Was formed by the RF sputtering method described above. And
Source / drain / channel regions are crystallized by laser annealing using a XeCl excimer laser.
Activated. The laser energy at this time has a threshold energy of 130 mJ / cm ² , and 220 mJ / cm ² is required for melting the entire film thickness. However, when the energy of 220 mJ / cm ² or more is applied from the beginning, the hydrogen contained in the film is rapidly released, so that the film is broken. Therefore, it is necessary to first drive out hydrogen with low energy and then melt it. In this embodiment, first 1
After expulsion of hydrogen at 50 mJ / cm ² , 23
Crystallization was performed at 0 mJ / cm ² . Further, the silicon oxide film 107 was removed after the laser annealing was completed.

After that, an island-shaped NTFT region 111 and a PTFT region 112 were formed by a photomask P3. A silicon oxide film 108 is formed thereon as a gate insulating film with a thickness of 500 to 2000Å, for example, 1000Å. This was performed under the same conditions as the production of the silicon oxide film as the blocking layer. During this film formation, a small amount of fluorine may be added to immobilize sodium ions.

Then, phosphorus is added to the upper side in an amount of 1 to 5 × 10 ²¹ cm.
^-3 concentration silicon film or this silicon film with molybdenum (Mo), tungsten (W), MoSi ₂ or
A multilayer film with WSi ₂ was formed. This was patterned with a fourth photomask P4 to obtain FIG. 6 (D). A gate electrode 109 for NTFT and a gate electrode 110 for PTFT were formed. For example, the channel length is 7 μm, the gate electrode is 0.2 μm of phosphorus-doped silicon, and molybdenum is 0.3 μm thick thereon. Although not shown in the drawing, a gate wiring and a wiring parallel to the gate wiring were formed as in the case of the first embodiment.

In addition to the above materials, for example, aluminum (Al) can be used as the material of this wiring. When aluminum is used, the self-alignment method can be applied by patterning this with the fourth photomask P4 and then anodizing the surface, so that the contact holes of the source / drain are closer to the gate. Since it can be formed at a position, the characteristics of the TFT can be further improved by reducing the mobility and the threshold voltage.

In this way, a C / TFT can be manufactured without applying a temperature above 400 ° C. in all steps. Therefore, an expensive substrate such as quartz does not have to be used as the substrate material, and it can be said that the process is extremely suitable for the large-screen liquid crystal display device of the present invention.

In FIG. 9E, the inter-layer insulator 113 was formed as a silicon oxide film by the above-mentioned sputtering method. This silicon oxide film is formed by LPCVD method, photo CVD method.
Method, atmospheric pressure CVD method may be used. For example, 0.2-0.
Formed to a thickness of 6 μm, and then a fifth photomask P
5 was used to form the window 117 for the electrode.

The electrical characteristics of the obtained TFT are PTFT.
The mobility is 35 (cm ² / Vs), Vth is -5.9 (V),
Mobility is 90 (cm ² / Vs) and Vth is 4.8 with NTFT
(V).

It was possible to obtain one substrate for a liquid crystal electro-optical device manufactured according to the method as described above. Since the method for manufacturing the other substrate is the same as that in the first embodiment, it will be omitted.
Then, the nematic liquid crystal composition was sandwiched between the first substrate and the second substrate, and the periphery was fixed with an epoxy adhesive. A TAB-shaped drive IC, a PCB having a common signal and a potential wiring were connected to the leads on the substrate, and a polarizing plate was attached to the outside to obtain a transmissive liquid crystal electro-optical device. This was connected to a rear lighting device in which three cold cathode tubes were arranged, and a tuner for receiving TV radio waves, to complete a wall-mounted TV. Compared with the conventional CRT type TV, the device has a planar shape, so that it can be installed on a wall or the like. The operation of this liquid crystal television was confirmed by applying a signal substantially equivalent to that shown in FIGS. 1 and 2 to the liquid crystal pixel.

[0071]

The present invention is characterized in that digital gradation display is performed in contrast to conventional analog gradation display. As an effect, if a liquid crystal electro-optical device having a number of pixels of 640 × 400 dots is assumed, it is very difficult to manufacture the characteristics of all 256,000 TFTs in total without variations. In consideration of mass productivity and yield, 16 gradation display is considered to be the limit, whereas as in the present invention, gradation display is performed by purely digital control without adding any analog signal. By doing so, gradation display of 256 gradations or more became possible. Since it is a completely digital display, T
The gradation ambiguity due to the variation in FT characteristics is completely eliminated, and therefore, even if there is a slight variation in TFT, extremely uniform gradation display was possible. Therefore, in the past, the yield was extremely poor in order to obtain a TFT with little variation, but the yield of the TFT was not so much a problem according to the present invention, so that the yield of the liquid crystal device was improved and the manufacturing cost was significantly suppressed. I was able to.

For example, 256,0 of 640 × 400 dots
When normal analog gradation display is performed on a liquid crystal electro-optical device in which 00 sets of TFTs are formed in a 300 mm square,
Since there is about ± 10% variation in TFT characteristics, 1
6 gradation display was the limit. However, when the digital gray scale display according to the present invention is performed, it is possible to display up to 256 gray scales because it is hardly affected by the characteristic variation of the TFT element, and the color display is 16,777,2.
A wide variety of 16 colors and subtle colors can be displayed. When displaying software such as a television image, for example, even "rocks" of the same color have slightly different shades due to their fine depressions. If you try to display something close to the natural color,
16 gradations are difficult. The gradation display according to the present invention makes it possible to impart these minute color tone changes.

In the embodiment of the present invention, T using silicon is used.
I explained mainly about FT, but T using germanium
FT can be used as well. In particular, single crystal germanium has an electron mobility of 3600 cm ² / Vs and a hole mobility of 1800 cm ² / Vs, which is the value of single crystal silicon (electron mobility is 1350 cm ² / Vs, hole mobility is 480 c).
Since it exceeds the characteristic of m ² / Vs), it is an extremely excellent material for carrying out the present invention which requires high-speed operation. Further, germanium has a lower transition temperature from an amorphous state to a crystalline state than silicon, and is suitable for a low temperature process. Further, the nucleus generation rate during crystal growth is small, and therefore, generally, large crystals are obtained when polycrystal growth is performed. Thus, germanium has characteristics comparable to those of silicon.

In order to explain the technical idea of the present invention, an electro-optical device using liquid crystal, particularly a display device has been described as an example. However, in order to apply the idea of the present invention, no display device is used. However, it may be a so-called projection type television, other optical switch, or optical shutter. Further, the electro-optical material is not limited to liquid crystal, and it will be apparent that the present invention can be applied as long as the optical characteristics change due to electrical influences such as electric field and voltage.

[Brief description of drawings]

FIG. 1 shows an example of drive waveforms according to the present invention.

FIG. 2 shows an example of drive waveforms according to the present invention.

FIG. 3 shows an example of gradation display characteristics of a liquid crystal according to the present invention.

FIG. 4 shows an example of a matrix configuration according to the present invention.

FIG. 5 shows a planar structure of a device according to an example.

FIG. 6 shows a process of a TFT according to an example.

FIG. 7 shows a process of a TFT according to an example.

FIG. 8 shows a process of a color filter according to an example.

FIG. 9 shows a process of a TFT according to an example.

FIG. 10 shows a connection example of a protection circuit.

FIG. 11 shows an example of a protection circuit.

FIG. 12 shows an example of a protection circuit.

─────────────────────────────────────────────────── ─── Continuation of front page (56) Reference JP-A-63-133124 (JP, A) JP-A-2-174270 (JP, A) JP-A-60-86587 (JP, A) JP-A-63- 220289 (JP, A) JP-A-3-132723 (JP, A) JP-A-59-50559 (JP, A) (58) Fields investigated (Int.Cl. ⁷ , DB name) G02F 1/1368

Claims (24)

(57) [Claims] 1. A display device including a display portion and a protection circuit, wherein the protection circuit includes a first resistor, a second resistor and a thin film transistor, and one of a source and a drain of the thin film transistor is the first resistor. Is electrically connected to the gate of the thin film transistor via the first resistor and the second resistor, and is electrically connected to the display unit via the first resistor and the second resistor. The display device, wherein the resistor or the thin film transistor includes ITO. 2. A display device including a display unit and a protection circuit, wherein the protection circuit is electrically connected to the display unit, and the protection circuit includes a first resistor, a second resistor and a thin film transistor, One of a source and a drain of the thin film transistor is electrically connected to the gate of the thin film transistor through the first resistor, and the thin film transistor is electrically connected to the display unit through the first resistor and the second resistor. connected to said first resistor, said second resistor or said thin trunk <br/> register, the display device characterized by including ITO. 3. The display device according to claim 1, wherein the other of the source and the drain of the thin film transistor is grounded. 4. A display device including a display portion and a protection circuit, wherein the protection circuit includes a first resistor, a second resistor, an N-channel type thin film transistor and a P-channel type thin film transistor, P-channel thin film transistor is electrically connected to the gate electrode of the N-channel type thin film transistor and the P-channel thin film transistor through one said first resistance of the source and drain, respectively Rutotomoni, said first resistor及
And is electrically connected to the display unit via the second resistor.
The display device , wherein the first resistor, the second resistor, the N-channel type thin film transistor, or the P-channel type thin film transistor includes ITO. 5. A display device including a display unit and a protection circuit, wherein the protection circuit is electrically connected to the display unit , and the protection circuit includes a first resistor, a second resistor, an N-channel thin film transistor, and A P-channel thin film transistor is included, and one of a source and a drain of the N-channel thin film transistor and the P-channel thin film transistor is a gate electrode of the N-channel thin film transistor and the P-channel thin film transistor via the first resistor. electrically connected to Rutotomoni, said first resistor及
And is electrically connected to the display unit via the second resistor.
The display device , wherein the first resistor, the second resistor, the N-channel type thin film transistor, or the P-channel type thin film transistor includes ITO. 6. The display device according to claim 4, wherein the other of the source and the drain of the N-channel type thin film transistor and the P-channel type thin film transistor is grounded. 7. A television including a display portion and a protection circuit, wherein the protection circuit includes a first resistor, a second resistor, and a thin film transistor, and one of a source and a drain of the thin film transistor includes the first resistor. Is electrically connected to the gate of the thin film transistor via the first resistor and the second resistor, and is electrically connected to the display unit via the first resistor and the second resistor, the first resistor and the second resistor. or the thin film Tran <br/> register is television which comprises the ITO. 8. A television including a display unit and a protection circuit, wherein the protection circuit is electrically connected to the display unit, the protection circuit includes a first resistor, a second resistor and a thin film transistor, and the thin film transistor. Has one of a source and a drain electrically connected to the gate of the thin film transistor through the first resistor and electrically connected to the display unit through the first resistor and the second resistor. is connected, said first resistor, said second resistor or said thin trunk <br/> register is television which comprises the ITO. 9. The television according to claim 7 or 8, wherein the other of the source and the drain of the thin film transistor is grounded. 10. A television including a display unit and a protection circuit, wherein the protection circuit includes a first resistor, a second resistor, an N-channel thin film transistor and a P-channel thin film transistor, and the N-channel thin film transistor and the P-channel thin film transistor. channel thin film transistor is electrically connected to the gate electrode of the N-channel type thin film transistor and the P-channel thin film transistor through one said first resistance of the source and drain, respectively Rutotomoni, said first resistor及
And is electrically connected to the display unit via the second resistor.
The television , wherein the first resistor, the second resistor, the N-channel type thin film transistor, or the P-channel type thin film transistor includes ITO. 11. A television including a display unit and a protection circuit, wherein the protection circuit is electrically connected to the display unit , and the protection circuit includes a first resistor, a second resistor, an N-channel thin film transistor, and a P-type thin film transistor. A channel type thin film transistor is included, and one of a source and a drain of the N channel type thin film transistor and the P channel type thin film transistor is electrically connected to a gate electrode of the N channel type thin film transistor and the P channel type thin film transistor through the first resistor. connected to Rutotomoni, said first resistor及
And is electrically connected to the display unit via the second resistor.
The television , wherein the first resistor, the second resistor, the N-channel type thin film transistor, or the P-channel type thin film transistor includes ITO. 12. The television according to claim 10, wherein the other of the source and the drain of the N-channel type thin film transistor and the P-channel type thin film transistor is grounded. 13. A liquid crystal display device including a display portion and a protection circuit, wherein the protection circuit includes a first resistor, a second resistor and a thin film transistor, and one of a source and a drain of the thin film transistor is the first resistor. Electrically connected to the gate of the thin film transistor via a resistor and electrically connected to the display unit via the first resistor and the second resistor, the first resistor and the second resistor 2. The liquid crystal display device according to claim 1, wherein the resistor or the thin film transistor includes ITO. 14. A liquid crystal display device including a display unit and a protection circuit, wherein the protection circuit is electrically connected to the display unit, and the protection circuit includes a first resistor, a second resistor and a thin film transistor. One of a source and a drain of the thin film transistor is electrically connected to the gate of the thin film transistor through the first resistor, and the thin film transistor is electrically connected to the display unit through the first resistor and the second resistor. are connected, said first resistor, said second resistor or said thin trunk <br/> register, the liquid crystal display device which comprises a ITO. 15. The liquid crystal display device according to claim 13, wherein the other of the source and the drain of the thin film transistor is grounded. 16. A liquid crystal display device including a display portion and a protection circuit, wherein the protection circuit includes a first resistor, a second resistor, an N-channel thin film transistor and a P-channel thin film transistor, the P-channel thin film transistor is electrically connected to the gate electrode of one of a source and a drain respectively through the first resistor said N-channel type thin film transistor and the P-channel type thin film transistor Rutotomoni, the first resistor Over
And is electrically connected to the display unit via the second resistor.
Is the first resistor, the second resistor, the N-channel type TFT or the P channel type thin film transistor, a liquid crystal display device which comprises a ITO. 17. A liquid crystal display device including a display unit and a protection circuit, wherein the protection circuit is electrically connected to the display unit , and the protection circuit includes a first resistor, a second resistor, and an N-channel thin film transistor. And a P-channel thin film transistor, wherein each of the N-channel thin film transistor and the P-channel thin film transistor has one of a source and a drain via the first resistor, and the gate electrode of the N-channel thin film transistor and the P-channel thin film transistor. It is electrically connected to Rutotomoni, the first resistor及
And is electrically connected to the display unit via the second resistor.
Is the first resistor, the second resistor, the N-channel type TFT or the P channel type thin film transistor, a liquid crystal display device which comprises a ITO. 18. The liquid crystal display device according to claim 16, wherein the other of the source and the drain of the N-channel type thin film transistor and the P-channel type thin film transistor is grounded. 19. A projection type display device including a display portion and a protection circuit, wherein the protection circuit includes a first resistor, a second resistor and a thin film transistor, and one of a source and a drain of the thin film transistor is the first resistor. Is electrically connected to the gate of the thin film transistor via the resistor, and is electrically connected to the display unit via the first resistor and the second resistor. 2. The projection display device according to claim 2, wherein the resistor 2 or the thin film transistor includes ITO. 20. A projection type display device including a display unit and a protection circuit, wherein the protection circuit is electrically connected to the display unit, and the protection circuit includes a first resistor, a second resistor and a thin film transistor. In the thin film transistor, one of a source and a drain is electrically connected to the gate of the thin film transistor via the first resistor, and the thin film transistor is connected to the display unit via the first resistor and the second resistor. are electrically connected, said first resistor, said second resistor or said thin trunk <br/> register is a projection type display apparatus characterized by comprising ITO. 21. The projection type display device according to claim 19 or 20, wherein the other of the source and the drain of the thin film transistor is grounded. 22. A projection type display device including a display portion and a protection circuit, wherein the protection circuit includes a first resistor, a second resistor, an N-channel thin film transistor and a P-channel thin film transistor, and the N-channel thin film transistor. and the P-channel thin film transistor is electrically connected to the gate electrode of the N-channel type thin film transistor and the P-channel thin film transistor through one said first resistance of the source and drain, respectively Rutotomoni, the first Resistance
And is electrically connected to the display unit via the second resistor.
The projection type display device , wherein the first resistor, the second resistor, the N-channel type thin film transistor or the P-channel type thin film transistor includes ITO. 23. A projection type display device including a display section and a protection circuit, wherein the protection circuit is electrically connected to the display section , and the protection circuit has a first resistance, a second resistance and an N-channel type. A thin film transistor and a p-channel thin film transistor, wherein the n-channel thin film transistor and the p-channel thin film transistor have one of a source and a drain through the first resistor and a gate of the n-channel thin film transistor and the p-channel thin film transistor, respectively. It is electrically connected to the electrode Rutotomoni, the first resistor及
And is electrically connected to the display unit via the second resistor.
The projection type display device , wherein the first resistor, the second resistor, the N-channel type thin film transistor or the P-channel type thin film transistor includes ITO. 24. The projection type display device according to claim 22, wherein the other of the source and the drain of the N-channel type thin film transistor and the P-channel type thin film transistor is grounded.