JP2000199918A - Electro-optical device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To enable digital gradation display by forming protective circuits with ITO on a first substrate. SOLUTION: A nematic liquid crystal compsn. is held between a first substrate and a second substrate and is fixed to the peripheral part with an epoxy adhesive. Leads on the substrate are connected to PCBs, having TAB type driving ICs and common signal potential wirings, and a polarizing plate is adhered to the outer side of the substrate to obtain a transmission-type liquid crystal electro-optical device. Protective circuits are disposed between the peripheral drive circuits and pixels. When an excess voltage is applied on the wirings of pixels, the respective protective circuits are turned on to function to eliminate the voltage. The protective circuits consist of a doped or undoped semiconductor material, such as silicon, transparent conductive material such as ITO or normal wiring materials. Therefore, the protective circuits can be formed at a same time, when the pixel circuits are formed.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of displaying an image in a liquid crystal electro-optical device using a thin film transistor (hereinafter referred to as a TFT) as a driving switching element. It relates to a display method. The present invention particularly relates to a so-called full digital gradation display for performing gradation display without applying any analog signal to an active element from the outside.

[0002]

2. Description of the Related Art Liquid crystal compositions have different dielectric constants in the horizontal and vertical directions with respect to the molecular axis due to their material properties. Can be easily done. The liquid crystal electro-optical device displays ON / OFF, that is, displays light and dark, by controlling the amount of transmitted light or the amount of scattering of light using the anisotropic generation of the dielectric constant. As a liquid crystal material, a material called a TN (twinstead nematic) liquid crystal, an STN (super twinstead nematic) liquid crystal, a ferroelectric liquid crystal, a polymer liquid crystal, or a dispersion liquid crystal is known. It is known that a liquid crystal does not respond to an external voltage in an infinitely short time, but takes a certain time to respond. The value is specific to each liquid crystal material.
c, It takes several hundred msec for STN liquid crystal, several tens μsec for ferroelectric liquid crystal, and several tens msec for dispersion or polymer liquid crystal.

[0003] Among electro-optical devices using liquid crystals, the one that can obtain the best image quality is the one using the active matrix system. In a conventional active matrix type liquid crystal electro-optical device, a thin film transistor (TFT) is used as an active element, an amorphous or polycrystalline semiconductor is used for the TFT, and P
In this case, a TFT of only one of the N-type and the N-type was used. That is, in general, an N-channel TFT
(Referred to as NTFT) is connected in series to the pixel. Then, a signal voltage is applied to the signal lines of the matrix, and when signals are applied from both sides to the TFTs provided at the orthogonal portions of the respective signal lines, the ON / OFF state of the liquid crystal pixels is utilized by utilizing the fact that the TFTs are turned ON. OFF was individually controlled. By controlling the pixels by such a method, a liquid crystal electro-optical device having a high contrast can be realized.

[0004]

However, in such an active matrix system, it is extremely difficult to perform gradation display such as light and dark and color tone. Conventionally, for gray scale display, a method has been studied which utilizes the fact that the light transmittance of a liquid crystal changes depending on the magnitude of an applied voltage. This is, for example, the source of the TFT in the matrix.
By supplying an appropriate voltage from the peripheral circuit between the drains and applying a signal voltage to the gate electrode in that state,
It is intended to apply a voltage of that magnitude to the liquid crystal pixels.

However, in such a method, for example, due to the inhomogeneity of the TFT and the inhomogeneity of the matrix wiring, the voltage actually applied to the liquid crystal pixels differs by at least several% depending on each pixel. Oops. On the other hand, for example, the voltage dependence of the light transmittance of the liquid crystal is extremely non-linear, and the light transmittance changes rapidly at a specific voltage. In some cases it was significantly different. Therefore, in practice, achieving 16 gradations has been the limit.

[0006] As described above, the difficulty of gradation display is extremely disadvantageous in that the liquid crystal display device competes with a conventional general display device such as a cathode ray tube (CRT).

An object of the present invention is to propose a completely new method for realizing a gradation display which has been difficult in the past.

[0008]

Means for Solving the Problems As described above, it is possible to control the light transmittance of the liquid crystal by controlling the voltage applied to the liquid crystal in an analog manner. It has been found that gradation can be visually obtained by controlling the time during which voltage is applied to the liquid crystal.

For example, when a TN (twisted nematic) liquid crystal, which is a typical liquid crystal material, is used,
For example, in FIG. 1A, when comparing a case where a rectangular pulse as shown by A is applied with a case where a rectangular pulse as shown by C is applied, it is found that A is brighter. . Here, the pulse period was 1 msec. As a result, A was the brightest, and then B, C, and D in that order. This is completely unexpected. This is because in the above-mentioned ordinary TN liquid crystal material, 1 ms
The time ec is too short, and the TN liquid crystal does not react in such a short time. Therefore, in any case, it is impossible to realize the ON state of the liquid crystal. However, in reality, the liquid crystal was able to realize an intermediate density.

The specific principle is not yet known in detail. However, the present inventors have found that gradation expression can be performed using this phenomenon. That is, by applying a pulse to the liquid crystal material at a period such that the liquid crystal material does not react, by controlling the pulse width, an intermediate brightness is realized by digital control, which is exactly the feature of the present invention. Things. As a result of the study of the present inventors, it has been found that the pulse period for obtaining such an intermediate density needs to be 10 msec or less in the case of a TN liquid crystal.

Here, the meaning of the term pulse period will be clarified. That is, in this case,
A plurality of pulses are continuously applied to the liquid crystal. In this case, the pulse cycle refers to the time from the start of one pulse to the start of the next pulse.
Therefore, it is the reciprocal of the pulse repetition frequency.

The pulse width refers to the time during which a pulse is in a voltage state. Therefore, in FIG. 1, for example, in the case of a pulse train of C, T is the pulse period, and τ is the pulse width.

A similar effect was observed in the STN liquid crystal, the ferroelectric liquid crystal, and the polymer liquid crystal or the dispersion type liquid crystal. In each case, it became clear that an intermediate color tone can be obtained by applying a pulse having a period shorter than the response time. That is, S
100 msec or less, preferably 10 msec or less for a TN liquid crystal, and 10 μs or less for a ferroelectric liquid crystal.
A gradation display was obtained by applying a pulse having a cycle of ec or less, preferably 1 μsec or less, and a polymer liquid crystal or dispersion type liquid crystal having a cycle of 10 msec or less, preferably 1 msec or less.

Normally, in an image of a television or the like, 30 times per second is required.
The still images are sequentially fed out to form a moving image. Therefore, the duration of one still image is about 30 msec.
It is. This time is too early for the human eye,
It is literally “not to be caught”, and as a result, still images cannot be visually identified one by one. In any case, in order to obtain a normal moving image, one still image cannot be continued for 100 msec or longer at the longest.

If 256 gradations are to be displayed using the present invention, for example, if T = 3 msec,
It is necessary to adopt a pulse voltage application method capable of dividing the time of 3 msec by at least 256 as a method of applying a voltage to a pixel. That is, at least 3 msec /
It is necessary to form a circuit in which a pulse voltage of 256 = 11.7 μsec is applied to the pixel. Actually, as shown in FIG. 3, the duty ratio τ / T of the pulse and the light transmittance of the liquid crystal pixel are in a non-linear relationship. In order to obtain 256 gradations, the duty ratio of the pulse must be further reduced. Fine control is necessary.

In addition, when actual image display is performed, other pixels must be considered. In an actual image display device, for example, there are as many as 400 rows. That is,
As will be described later, the number of active elements in the matrix is 10
An extremely short response of 0 nsec is required. Therefore, an example of a circuit having such a short-time response is shown in FIG.
Hereinafter, the description will be made.

FIG. 4 shows an example of an active matrix circuit of a liquid crystal display device necessary for implementing the present invention. In the present invention, since the active element is required to respond in a short time of 100 nsec or less, it is necessary to form a circuit that operates at high speed. For this purpose, a modified transfer gate type circuit in which the NTFT and the PTFT operate in a complementary manner as shown in FIG. It is necessary to use

In this example, an example of an N × M matrix is shown. However, in order to reduce complexity, n
Only the vicinity of the row m column is shown. If you expand the same thing up, down, left and right, you will get a complete one.

FIG. 4 shows four modified transfer gates. The source of each modified transfer gate is connected to _Ym or Ym _{+ 1} (hereinafter collectively referred to as Y line). The gate of each modified transfer gate is connected to _Xn or _{Xn + 1} (hereinafter collectively referred to as X-rays). In addition, each deformation transfer
The gate drains the liquid crystal pixels Zn _{, m} , Zn _{, m + 1} , Z
_{n + 1, m} and Z _{n + 1, m + 1} . In the modified transfer gate, the NTFT and PTFT are symmetrical, so their positions may be interchanged. In the figure, a capacitor is artificially inserted in parallel with the capacitor of the pixel. The capacitor inserted at this time has an effect of suppressing a decrease in the voltage of the pixel due to spontaneous discharge of the pixel. The variation in the voltage effect of the pixel depends on the variation of the pixel. In particular, in the invention as described in the present invention in which gradation display is performed with a constant voltage applied to a pixel, the image quality is reduced. However, by inserting the capacitor in parallel with the pixel as described above, the voltage effect due to the variation of the pixel can be significantly suppressed, and high image quality can be obtained.

Next, an example of the operation of the circuit when such a circuit is used will be described with reference to FIGS. This matrix circuit needs to operate so as to apply a pulsed voltage as shown in FIG. 1A to the liquid crystal cell. FIG. 1B shows an outline of the signal voltages applied to the X-rays and the Y-lines to generate such a pulse. As an example, consider a 400 × 640 matrix.

The signal applied to the Y line is represented by V (Y _m ) in the case of the Y _m line, for example, which is actually 256 out of a group of pulses repeated in the cycle T. Pulse (hereinafter referred to as sub-pulse),
Further, each of the 256 sub-pulses is 400
It can be seen that the pulse train is composed of a pulse train including a number of elements. Here, the number 400 is the number of rows in the matrix. Therefore, if the minimum unit of the pulse applied to the Y line is T = 3 msec, it is 29 nsec.

On the other hand, during the time T / 256,
V (X ₁ ), V (X _n ), V (X _{n + 1} ), V (X
₄₀₀ ), a pulse whose polarity is inverted at least once (hereinafter referred to as a bipolar pulse) is applied with a staggered timing. bipolar·
The pulse needs to be even shorter than the minimum unit pulse of the pulse applied to the Y line. Eventually, during time T, 256 bipolar pulses are applied to each X-ray.

Next, the operation of the actual circuit will be described with reference to FIG. First, a first sub-pulse is applied to each Y line. Of course, these sub-pulses are different for each Y line. On the other hand, as described above, the bipolar pulse is applied to the X-ray in order of X ₁ and then X ₂ . First, consider the case where the bipolar pulse is applied to the X _1. At this time, the pixel Z
_The active element connected to _1,1 is turned on. Then, Y line connected to the active element because it is when a voltage is applied, pixel Z ₁₁ is charged. Then, since the bipolar pulse is cut off before the voltage of the Y line becomes zero, electric charges are left in the pixels Z _{1, 1} and the voltage state is maintained. Similarly, Z1 _{, m} , Z1 _{, m + 1,} and _Z1,400 are in a voltage state.

In this way, consider the case where bipolar pulses are applied one after another and applied to _Xn .
Now, four pixels Zn _{, m} , Zn _{, m + 1} , Zn _{+ 1, m} , Z
if has focused on _{n + 1, m + 1,} may be of interest to the n-th and (n + 1) th first sub-pulse of Y _m and Y _{m + 1.} Since both Y _m and Y _{m + 1} have the n-th pulse, the pixels Zn _{, m} and Zn _{, m + 1} are in a voltage state. Then
A bipolar pulse is applied to X _{n + 1} . Y _{m is} also Y
_{Since m + 1} also has the (n + 1) th pulse, the pixels Zn _{+ 1, m} and Zn _{+ 1, m + 1} are charged in this case as well.

Next, although omitted in the drawing, it is assumed that a second sub-pulse has arrived. At this time, if there are n-th and (n + 1) -th pulses in both Y _m and Y _{m + 1} , the charged state is not lost, and the four pixels continue to be in the voltage state. Thereafter, it is assumed that the voltage state of all four pixels continues until the (h-1) th sub-pulse.

Next, it is assumed that the sub-pulse advances and the h-th sub-pulse arrives. In the figure, to avoid complexity, n
Pulses other than the (th) and (n + 1) th pulses are omitted. At this time, since there are n-th pulses in both Y _m and Y _{m + 1} ,
The pixels Zn _{, m} and Zn _{, m + 1} remain in the voltage state. But,
Since the (n + 1) -th pulse was not present in Y _{m + 1} , the pixel Z _{n + 1, m} continues the voltage state, but the pixel Z _{n + 1, m
In the case of n + 1 and m + 1} , the gate of the active element is in the ON state, and since no voltage is supplied from the outside, the stored charge is released and the voltage state is interrupted.

Furthermore, when the sub-pulses of the i came, because (n + 1) th voltage pulse of Y _m is zero, the state of charge of Z n _{+ 1, m} is released. Hereinafter, the j-th
And the k th sub-pulse, Y _{m + 1} ,
Since the n-th signal of Y _m was zero, the pixels Zn _{, m} ,
The state of charge of Zn _{, m + 1} is interrupted during the k-th and j-th sub-pulses, respectively. Through such a process, the time of the voltage state can be digitally controlled for each pixel as shown by V (Z) in FIG. By repeating such an operation, the width of the voltage pulse applied to each pixel can be arbitrarily controlled as shown in FIG.

As is apparent from the above description, in practicing the present invention, the sub-pulses as described above do not have to be clearly defined pulse-like. For the sake of simplicity, the concept of sub-pulses has been introduced. In particular, it is apparent that the present invention can be implemented even if the sub-pulses are not clear and the signals have almost no boundaries. is there. Similarly, a large number of pulses included in the sub-pulse need not be independent pulses, and may be a series of ON / OFF signals. Furthermore, for simplicity of explanation, the zero level and voltage level of the signal have been clarified, but since this is only a matter of being below or above the threshold voltage of the liquid crystal, it is absolutely necessary. It does not need to be zero.

[0029]

[Embodiment 1] In this embodiment, a wall-mounted television was manufactured using a liquid crystal display device having a circuit configuration as shown in FIG. The TF at that time
T is polycrystalline silicon using laser annealing.

FIG. 5 shows an actual arrangement of electrodes and the like corresponding to this circuit configuration for one pixel. First, a method for manufacturing a liquid crystal panel used in this embodiment will be described with reference to FIGS. In FIG. 6A, a magnetron RF (high frequency) is placed on a glass 50, such as quartz glass, which can withstand an inexpensive heat treatment at 700 ° C. or less, for example, about 600 ° C.
A silicon oxide film as the blocking layer 51 is formed to a thickness of 1000 to 3000 ° by using a sputtering method. The process conditions are 100% oxygen atmosphere, film formation temperature 15 ° C, output 4
The pressure was set to 00 to 800 W and the pressure to 0.5 Pa. The deposition rate using quartz or single crystal silicon as the target is 30 to 1
00 ° / min.

A silicon film 52 was formed thereon by a plasma CVD method. The film formation temperature is from 250 ° C to 35
In this example, the temperature was set to 320 ° C., and monosilane (SiH
₄ ) was used. Not only monosilane (SiH ₄ ) but also disilane (Si ₂
H ₆ ) Alternatively, trisilane (Si ₃ H ₈ ) may be used. These were introduced into the PCVD apparatus at a pressure of 3 Pa, and 13.56 M
The film was formed by applying a high frequency power of Hz. At this time, an appropriate high frequency power is 0.02 to 0.10 W / cm ² , and in this example, 0.055 W / cm ² was used. The flow rate of monosilane (SiH ₄ ) was set to 20 SCCM, and the deposition rate at that time was about 120 ° / min. In order to control the threshold voltage (Vth) of the PTFT and the NTFT to be substantially the same, boron is used in a concentration of 1 × 10 ¹⁵ to 1 × 10 ¹⁸ cm using diborane.
^-3 may be added during film formation. In addition, not only the plasma CVD but also a sputtering method and a low pressure CVD method may be used for forming the silicon layer to be a channel region of the TFT, and the method will be briefly described below.

When the sputtering method is used, the back pressure before the sputtering is set to 1 × 10 ⁻⁵ Pa or less, and single crystal silicon is used as a target in an atmosphere in which hydrogen is mixed with 20 to 80% of argon. For example, argon was 20% and hydrogen was 80%.
The film formation temperature was 150 ° C., the frequency was 13.56 MHz, the sputter output was 400 to 800 W, and the pressure was 0.5 Pa.

When the film is formed by the reduced pressure gas phase method, the temperature is 450 to 550 ° C. lower than the crystallization temperature by 100 to 200 ° C.
Disilane (Si ₂ H ₆ ) or trisilane (Si ₃ H ₈ ) was supplied to the CVD apparatus at 30 ° C. to form a film. The reactor pressure is 30 ~
It was set to 300 Pa. The deposition rate was 50-250 ° / min. Suresshuho the PTFT and NTFT - for controlling field voltage (Vth) in substantially the same, boron may be added during deposition as the concentration of ^{1 × 10 15 ~1 × 10 18} cm -3 by using diborane .

The coatings formed by these methods are:
It is preferable that oxygen is 5 × 10 ²¹ cm ⁻³ or less. In order to promote crystallization, the oxygen concentration should be 7 × 10 ¹⁹ cm ⁻³ or less,
Preferably, it is desirable to be 1 × 10 ¹⁹ cm ⁻³ or less,
If the amount is too small, the leakage current in the off state increases due to the backlight, so this concentration was selected. If the oxygen concentration is high, crystallization is difficult, and the laser annealing temperature must be increased or the laser annealing time must be increased. Hydrogen is 4 × 10 ²⁰ cm ⁻³ and silicon 4 × 10 ²²
When compared with cm ^-3 , it was 1 atomic%.

In order to further promote crystallization of the source and the drain, the oxygen concentration is set to 7 × 10 ¹⁹ cm ⁻³ or less, preferably 1 × 10 ¹⁹ cm ⁻³ or less,
Oxygen may be added only to the T channel formation region by ion implantation so as to have a concentration of 5 × 10 ^{20 to} 5 × 10 ²¹ cm ⁻³ .

According to the above method, an amorphous silicon film was formed to a thickness of 500 to 5000 Å, in this embodiment, 1000 Å. Thereafter, a pattern in which only the source / drain regions were opened in the photoresist 53 using the mask P1 was formed. A silicon film 54 serving as an n-type active layer was formed thereon by a plasma CVD method. Film formation temperature is 25
The temperature was set at 0 ° C. to 350 ° C. In this example, the temperature was set to 320 ° C., and monosilane (SiH ₄ ) and monosilane-based phosphine (PH ₃ ) having a concentration of 3% were used. These were introduced into the PCVD apparatus at a pressure of 5 Pa, and high-frequency power of 13.56 MHz was applied to form a film. At this time, the high frequency power is 0.0
5 to 0.20 W / cm ² is appropriate, and in this example, 0.120 W / cm ² was used.

The specific conductivity of the n-type silicon layer formed by this method was about 2 × 10 ⁻¹ [Ωcm ⁻¹ ]. The film thickness was 50 °. Thereafter, the resist 53 is removed by a lift-off method, and the source / drain region 5 is removed.
5, 56 were formed. Further, a p-type active layer was formed using the same process. The gas introduced at this time was monosilane (SiH ₄ ) and monosilane-based diborane (B ₂ H ₆ ) 5.
% Concentration was used. These are placed in a PCVD system in 4P
The film was introduced at a pressure of a, and a high frequency power of 13.56 MHz was applied to form a film. At this time, the high frequency power is 0.05 to 0.
20 W / cm ² is appropriate, and in this embodiment, 0.120
W / cm ² was used. P created by this method
The specific conductivity of the mold silicon layer was about 5 × 10 ^-2 [Ωcm ^-1 ]. The film thickness was 50 °. Thus, FIG.
I got

Thereafter, source / drain regions 59 and 60 were formed by the lift-off method as in the case of the N-type region. Thereafter, the silicon film 52 is etched away using the mask P3, and the island region 6 for the N-channel thin film transistor is removed.
3 and island region 6 for P-channel type thin film transistor
4 was formed.

Thereafter, as shown in FIG.
Using an excimer laser, laser doping was performed on the active layer at the same time as laser annealing of the source, drain, and channel regions. At this time, the threshold energy of the laser energy is 130 mJ / cm ² , and 220 mJ / cm ² is required to melt the entire film thickness. However, when an energy of 220 mJ / cm ² or more is irradiated from the beginning, hydrogen contained in the film is rapidly released, and the film is destroyed. For this purpose, it is necessary to first displace hydrogen and then melt it with low energy. After performing the flush hydrogen in the first 150 mJ / cm ² in the present embodiment was subjected to crystallization at 230 mJ / cm ^2.

On this, a silicon oxide film was formed as a gate insulating film to a thickness of 500 to 2000 {for example, 1000}. This was made under the same conditions as those for forming the silicon oxide film as the blocking layer. During the film formation, a small amount of fluorine may be added to fix the sodium ions.

Thereafter, 1 to 5 × 10 ²¹ cm of phosphorus is placed on the upper side.
^-3 silicon film or molybdenum (Mo), tungsten (W), MoSi ₂ or
A multilayer film with WSi ₂ was formed. This was patterned using a fourth photomask P4 to obtain FIG. NTFT
A gate electrode 66 for PTFT and a gate electrode 67 for PTFT were formed. For example, a channel length of 7 μm, 0.2 μm of silicon as a gate electrode, and 0.1 μm of molybdenum thereon.
It was formed to a thickness of 3 μm.

At the same time, as shown in FIG. 7D ', the gate wiring 65 and the wiring 68 arranged in parallel with the gate wiring 65 were also patterned.

Further, as the gate electrode material, for example, aluminum (Al) can be used in addition to the above materials. When aluminum is used, after patterning it with a fourth photomask P4 and then anodizing the surface thereof, the self-alignment method can be applied. Can be formed at a position close to the above, so that the characteristics of the TFT can be further improved from the reduction of the mobility and the threshold voltage.

Thus, a C / TFT can be manufactured without applying a temperature to 400 ° C. or more in all steps. Therefore, it is not necessary to use an expensive substrate such as quartz as a substrate material, and it can be said that the process is very suitable for the large-screen liquid crystal display device of the present invention.

Further, a silicon oxide film was formed on the interlayer insulator 69 by the above-mentioned sputtering method. This silicon oxide film may be formed by an LPCVD method, a photo CVD method, or a normal pressure CVD method. For example, it was formed to a thickness of 0.2 to 0.6 μm, and then a window 79 for an electrode was formed using the fifth photomask P5. Thereafter, aluminum was further formed on the entire surface to a thickness of 0.3 μm by a sputtering method, and leads 74 and contacts 73 and 75 were formed using a sixth photomask P6. Thus, FIG. 6E and FIG. 7E ′ are obtained.

Thereafter, the surface was coated with an organic resin 77 for flattening, for example, a translucent polyimide resin, and an electrode hole was formed again using the seventh photomask P7. Further, ITO (indium tin oxide) was formed on the entire surface by sputtering to a thickness of 0.1 μm, and a pixel electrode 71 was formed using an eighth photomask P8. This ITO is between room temperature and 1
Films were formed at 50 ° C. and achieved with oxygen at 200-400 ° C. or annealing in air. Thus, FIG. 6 (F) and FIG. 7 (F ′) are obtained.

FIG. 7 is a sectional view taken along the line AA ′ of FIG.
(G) is shown. Actually, a counter electrode is provided with a liquid crystal material interposed therebetween, and a capacitance is generated between the counter electrode and the electrode 71 as shown in the figure. At the same time, wiring 68
A capacitance also occurs between the electrode and the electrode 71. And wiring 6
By keeping 8 at the same potential as the counter electrode, a circuit in which a capacitor is inserted in parallel with the liquid crystal pixel can be formed as shown in FIG. In particular, by arranging as in the present embodiment, the wiring 68 is parallel to the gate wiring 65, so that the parasitic capacitance between the two wirings is small, and therefore, there is an effect of reducing attenuation and delay of a signal transmitted through the gate wiring.

The wiring 68 thus formed is
Can be used as a ground line of a protection circuit provided at the end of each matrix when used with ground. The protection circuit is provided between a peripheral driving circuit and a pixel as shown in FIG. 10 and refers to a circuit as shown in FIG. 11 and FIG. In any case, when an excessive voltage is applied to the wiring of the pixel, it is turned on, and has a function of removing the voltage. These protection circuits include doped or undoped semiconductor materials such as silicon,
It is configured using a transparent conductive material such as TO or a normal wiring material. Therefore, it can be formed at the same time when the circuit of the pixel is formed.

This means that, for example, each of the protection circuits in FIG.
/ TFT. Further, the protection circuit of FIG. 12 does not use a TFT,
The diode is constituted by, for example, a PIN junction.
It is obvious that it has a structure such as PIP, PNP, or NPN and can be manufactured by using the manufacturing method described in this embodiment without need to explain each time.

The electrical characteristics of the TFT obtained as described above are PTFT with a mobility of 40 (cm ² / Vs) and V
th is -5.9 (V), and the mobility is 80 (cm ² /
Vs) and Vth were 5.0 (V).

The liquid crystal cell manufactured according to the method described above
One substrate for the electro-optical device was obtained. This liquid
FIG. 5 shows the arrangement of the electrodes and the like of the crystal display device.
N-channel thin film transistor and P-channel thin film transistor
Transistor and signal line Y₁And Y _TwoProvided at the intersection with
I have. A matrix configuration using such a C / TFT
I got it. To repeat such a structure left, right, up and down
Larger images such as 640x480 and 1280x960
A liquid crystal display device of the present invention can be obtained. In this embodiment, 1
920 × 400. Thus, the first substrate is obtained.
Was.

FIG. 8 shows a method for manufacturing the other substrate. A polyimide resin obtained by mixing a black pigment with polyimide is formed on a glass substrate to a thickness of 1 μm using a spin coating method,
Black stripe 8 using ninth photomask P9
1 was produced. After that, a film of a polyimide resin mixed with a red pigment was formed to a thickness of 1 μm using a spin coating method,
Red filter 8 using tenth photomask P10
3 was produced. Similarly, a green filter 85 and a blue filter 86 were manufactured using the masks P11 and P12. During the production, each filter was fired at 350 ° C. in nitrogen for 60 minutes. After that, the leveling layer 89 was manufactured using transparent polyimide also by using the spin coating method.

Thereafter, ITO (indium tin oxide) was formed on the entire surface to a thickness of 0.1 μm by sputtering, and a common electrode 90 was formed using a fifth photomask 91. This ITO is deposited at room temperature to 150 ° C.
Fulfilled by oxygen at 300 ° C. or annealing in air,
A second substrate was obtained. A polyimide precursor was printed on the substrate by using an offset method, and baked at 350 ° C. for 1 hour in a non-oxidizing atmosphere such as nitrogen. Thereafter, a known rubbing method was used to modify the surface of the polyimide, and at least initially, a means for aligning liquid crystal molecules in a certain direction was provided.

Thereafter, the nematic liquid crystal composition was sandwiched between the first substrate and the second substrate, and the periphery was fixed with an epoxy adhesive. A drive IC having a TAB shape and a PCB having a common signal and potential wiring were connected to leads on the substrate, and a polarizing plate was attached on the outside to obtain a transmissive liquid crystal electro-optical device. This was connected to a rear lighting device in which three cold cathode tubes were arranged, and a tuner for receiving TV radio waves to complete a wall-mounted TV. Compared to a conventional CRT system television, the device has a flat shape, so that it can be installed on a wall or the like. The operation of this liquid crystal television was confirmed by applying signals substantially equivalent to those shown in FIGS. 1 and 2 to the liquid crystal pixels.

Embodiment 2 In this embodiment, a wall-mounted television is manufactured using a liquid crystal display device having a circuit configuration as shown in FIG. 4, and a description thereof will be given. Also T at that time
FT was polycrystalline silicon using laser annealing.

[0056] The following describes in accordance with FIG. 9, the manufacturing method of a TFT portion. In FIG. 9A, an inexpensive material such as quartz glass is 700 ° C. or less, for example, approximately 600 ° C.
Magnetron RF on glass 100 that can withstand heat treatment
(High frequency) A silicon oxide film as the blocking layer 101 is formed to a thickness of 1000 to 3000 ° by using a sputtering method. Process conditions are 100% oxygen atmosphere, film formation temperature 1
The temperature was 5 ° C., the output was 400 to 800 W, and the pressure was 0.5 Pa.
The film formation rate using quartz or single crystal silicon as a target was 30 to 100 ° / min.

A silicon film 102 was formed thereon by a plasma CVD method. Film formation temperature is 250 ° C-3
In this example, the temperature was set to 320 ° C.
iH ₄ ) was used. Not only monosilane (SiH ₄ ), but disilane (S
i ₂ H ₆ ) Alternatively, trisilane (Si ₃ H ₈ ) may be used. These were introduced into the PCVD apparatus at a pressure of 3 Pa, and 13.56
The film was formed by applying a high frequency power of MHz. At this time, an appropriate high frequency power is 0.02 to 0.10 W / cm ² , and in this example, 0.055 W / cm ² was used. The flow rate of monosilane (SiH ₄ ) was set to 20 SCCM, and the deposition rate at that time was about 120 ° / min. In order to control the threshold voltage (Vth) of the PTFT and the NTFT to be substantially the same, boron is used in a concentration of 1 × 10 ¹⁵ to 1 × 10 ¹⁸ using diborane.
It may be added during film formation as a concentration of cm ^-3 . Also TFT
In addition to the plasma CVD, the silicon layer serving as the channel region may be formed by a sputtering method or a low-pressure CVD method. The method will be briefly described below.

In the case of performing the sputtering method, the back pressure before the sputtering was set to 1 × 10 ⁻⁵ Pa or less, single-crystal silicon was used as a target, and an atmosphere in which 20 to 80% of hydrogen was mixed with argon was used. For example, argon was 20% and hydrogen was 80%.
The film formation temperature was 150 ° C., the frequency was 13.56 MHz, the sputter output was 400 to 800 W, and the pressure was 0.5 Pa.

In the case of forming by a reduced pressure gas phase method, 450 to 550 ° C. lower than the crystallization temperature by 100 to 200 ° C.
Disilane (Si ₂ H ₆ ) or trisilane (Si ₃ H ₈ ) was supplied to the CVD apparatus at 30 ° C. to form a film. The reactor pressure is 30 ~
It was set to 300 Pa. The deposition rate was 50-250 ° / min. Suresshuho the PTFT and NTFT - for controlling field voltage (Vth) in substantially the same, boron may be added during deposition as the concentration of ^{1 × 10 15 ~1 × 10 18} cm -3 by using diborane .

The coatings formed by these methods are:
It is preferable that oxygen is 5 × 10 ²¹ cm ⁻³ or less. In order to promote crystallization, the oxygen concentration should be 7 × 10 ¹⁹ cm ⁻³ or less,
Preferably, it is desirable to be 1 × 10 ¹⁹ cm ⁻³ or less,
If the amount is too small, the leakage current in the off state increases due to the backlight, so this concentration was selected. If the oxygen concentration is high, crystallization is difficult, and the laser annealing temperature must be increased or the laser annealing time must be increased. Hydrogen is 4 × 10 ²⁰ cm ⁻³ and silicon 4 × 10 ²²
When compared with cm ^-3 , it was 1 atomic%.

In order to further promote crystallization of the source and the drain, the oxygen concentration is set to 7 × 10 ¹⁹ cm ⁻³ or less, preferably 1 × 10 ¹⁹ cm ⁻³ or less,
Oxygen may be added only to the T channel formation region by ion implantation so as to have a concentration of 5 × 10 ^{20 to} 5 × 10 ²¹ cm ⁻³ .
According to the above method, the amorphous silicon film is
The film was formed to have a thickness of 5000 to 5000 Å, and 1000 Å in this embodiment.

After that, the photoresist 103 is
Should be used as source / drain region of NTFT using 1
A pattern in which only the region was opened was formed. And Regis
Using ion 103 as an ion implantation method with mask 103
Than 2 × 10¹⁴~ 5 × 10 ¹⁶cm^-2, Preferably 2x
10¹⁶cm^-2Only to form the n-type impurity region 104.
Done. After that, the resist 103 was removed.

Similarly, a resist 105 was applied, and using the mask P2, a pattern was formed in which only the regions to be the source / drain regions of the PTFT were opened. Then, using the resist 105 as a mask, the p-type impurity region 106 is formed.
Was formed. As an impurity, boron is used, and also by ion implantation, 2 × 10 ^{14 to} 5 × 10 ¹⁶ cm ⁻² ,
Preferably, an impurity is introduced only by 2 × 10 ¹⁶ cm ⁻² .
Like this. FIG. 9B is obtained.

After that, a thickness of 50 to 3
00 nm, for example, 100 nm silicon oxide film 107
Was formed by the above-mentioned RF sputtering method. And
Using a XeCl excimer laser, the source, drain and channel regions are crystallized by laser annealing.
Activated. At this time, the threshold energy of the laser energy is 130 mJ / cm ² , and 220 mJ / cm ² is required to melt the entire film thickness. However, when an energy of 220 mJ / cm ² or more is irradiated from the beginning, hydrogen contained in the film is rapidly released, and the film is destroyed. For this purpose, it is necessary to first displace hydrogen and then melt it with low energy. In this embodiment, first
After purging hydrogen at 50 mJ / cm ² , 23
Crystallization was performed at 0 mJ / cm ² . Further, after the end of the laser annealing, the silicon oxide film 107 was removed.

Thereafter, an NTFT region 111 and a PTFT region 112 in the shape of an island were formed using the photomask P3. On this, a silicon oxide film 108 was formed as a gate insulating film to a thickness of 500 to 2000 {for example, 1000}. This was made under the same conditions as those for forming the silicon oxide film as the blocking layer. During the film formation, a small amount of fluorine may be added to fix the sodium ions.

Thereafter, 1 to 5 × 10 ²¹ cm of phosphorus is placed on the upper side.
^-3 silicon film or molybdenum (Mo), tungsten (W), MoSi ₂ or
A multilayer film with WSi ₂ was formed. This was patterned using a fourth photomask P4 to obtain FIG. 9D. A gate electrode 109 for NTFT and a gate electrode 110 for PTFT were formed. For example, a channel length is 7 μm, and a gate electrode is formed of 0.2 μm of phosphorus silicon, and a molybdenum is formed thereon with a thickness of 0.3 μm. Although not shown in the figure, a gate wiring and a wiring parallel to the gate wiring were also formed as in the case of the first embodiment.

As a material for the wiring, for example, aluminum (Al) can be used in addition to the above materials. When aluminum is used, after patterning it with the fourth photomask P4 and then anodizing the surface thereof, the self-alignment method can be applied, so that the source / drain contact holes are closer to the gate. Since the TFT can be formed at a position, the characteristics of the TFT can be further improved by reducing the mobility and the threshold voltage.

Thus, a C / TFT can be manufactured without applying a temperature to 400 ° C. or more in all steps. Therefore, it is not necessary to use an expensive substrate such as quartz as a substrate material, and it can be said that the process is very suitable for the large-screen liquid crystal display device of the present invention.

In FIG. 9E, a silicon oxide film was formed on the interlayer insulator 113 by the above-described sputtering method. This silicon oxide film is formed by LPCVD, optical CVD
Or a normal pressure CVD method. For example, 0.2-0.
6 μm thick, and then a fifth photomask P
5 was used to form a window 117 for an electrode. Thereafter, aluminum is further formed on the entire surface by a sputtering method to a thickness of 0.3 μm, and leads 116 and contacts 114 and 115 are formed using a sixth photomask P6. 119, for example, a translucent polyimide resin was applied and formed, and an electrode hole was formed again using the seventh photomask P7. In addition, these
TO (indium tin oxide) was formed to a thickness of 0.1 μm by a sputtering method, and a pixel electrode 118 was formed using an eighth photomask P8. This ITO film is formed at room temperature to 150 ° C., and oxygen at 200 to 400 ° C. or annealed in air.
Fulfilled by Le.

The electrical characteristics of the obtained TFT are PTFT
And the mobility is 35 (cm ² / Vs), Vth is -5.9 (V),
The mobility of NTFT is 90 (cm ² / Vs) and Vth is 4.8.
(V).

One substrate for a liquid crystal electro-optical device manufactured according to the above method was obtained. The method for fabricating the other substrate is the same as that in the first embodiment, and will not be described.
Thereafter, the nematic liquid crystal composition was sandwiched between the first substrate and the second substrate, and the periphery was fixed with an epoxy adhesive. A drive IC having a TAB shape and a PCB having common signals and potential wiring were connected to leads on the substrate, and a polarizing plate was adhered on the outside to obtain a transmissive liquid crystal electro-optical device. This was connected to a rear lighting device in which three cold cathode tubes were arranged, and a tuner for receiving TV radio waves to complete a wall-mounted TV. Compared to a conventional CRT system television, the device has a flat shape, so that it can be installed on a wall or the like. The operation of this liquid crystal television was confirmed by applying signals substantially equivalent to those shown in FIGS. 1 and 2 to the liquid crystal pixels.

[0072]

The present invention is characterized in that digital gray scale display is performed in contrast to the conventional analog gray scale display. As an effect, assuming a liquid crystal electro-optical device having a number of pixels of 640 × 400 dots, for example, it is very difficult to manufacture all the 256,000 TFTs without variation in characteristics. In consideration of mass productivity and yield, 16-gradation display is considered to be the limit. However, as in the present invention, gradation display is performed purely by digital control without adding analog signals at all. By doing so, gray scale display of 256 gray scale display or more is possible. Since it is a complete digital display,
The ambiguity of the gradation due to the variation in the characteristics of the FT was completely eliminated. Therefore, even if the variation in the TFT was slight, a very uniform gradation display was possible. Therefore, while the yield has been extremely low in the past in order to obtain a TFT with little variation, the present invention has reduced the yield of the TFT so much that the yield of the TFT is improved and the manufacturing cost is significantly reduced. did it.

For example, 256,0 of 640 × 400 dots
When a normal analog gradation display is performed on a liquid crystal electro-optical device in which 00 sets of TFTs are formed in a 300 mm square,
Since there is about ± 10% variation in TFT characteristics,
Six gradation display was the limit. However, when the digital gradation display according to the present invention is performed, the display is hardly affected by the variation in the characteristics of the TFT elements, so that it is possible to display up to 256 gradations.
A variety of 16 colors can be displayed in subtle colors. In the case of displaying software such as television images, for example, even a “rock” made of the same color has a slightly different color due to its minute dents and the like. If you try to display something close to the colors of nature,
Difficulty is required for 16 gradations. With the gradation display according to the present invention, it is possible to impart these minute color changes.

In the embodiment of the present invention, T using silicon is used.
The explanation has been added focusing on FT.
FT can be used as well. In particular, the electron mobility of single crystal germanium is 3600 cm ² / Vs and the hole mobility is 1800 cm ² / Vs, which is the value of single crystal silicon (1350 cm ² / Vs in electron mobility and 480 c in hole mobility).
m ² / Vs), which is an excellent material for implementing the present invention that requires high-speed operation. In addition, germanium has a lower transition temperature from an amorphous state to a crystalline state than silicon, and is suitable for a low-temperature process. In addition, the nucleation rate during crystal growth is low, and therefore, generally, large crystals are obtained when polycrystals are grown. Thus, germanium has characteristics comparable to those of silicon.

[Brief description of the drawings]

FIG. 1 shows a driving waveform according to the present invention.

FIG. 2 shows a driving waveform according to the present invention.

FIG. 3 shows an example of a gradation display characteristic according to the present invention.

FIG. 4 shows an example of a matrix configuration according to the invention.

FIG. 5 shows a planar structure of a device according to an example.

FIG. 6 shows a TFT process according to an embodiment.

FIG. 7 illustrates a TFT process according to an embodiment.

FIG. 8 shows a process of a color filter according to an example.

FIG. 9 shows a TFT process according to an embodiment.

FIG. 10 illustrates a connection example of a protection circuit.

FIG. 11 illustrates an example of a protection circuit.

FIG. 12 illustrates an example of a protection circuit.

Continued on the front page (72) Inventor Yasuhiko Takemura 398 Hase, Atsugi-shi, Kanagawa Inside Semiconductor Energy Research Institute Co., Ltd.

Claims (10)

[Claims] A first circuit having a thin film transistor formed on the first substrate; a pixel circuit having a thin film transistor formed on the first substrate; a lead electrically connected to the pixel circuit; A protection circuit formed on a first substrate, a planarization film formed on the pixel circuit, an ITO formed on the second substrate, and between the first and second substrates A holding liquid crystal composition, and a TAB-shaped driving IC electrically connected to the lead
An electro-optical device comprising: an electro-optical device, wherein the protection circuit includes ITO. 2. A pixel circuit having thin film transistors formed on the first and second substrates having an insulating surface; a pixel circuit having a thin film transistor formed on the first substrate; a lead electrically connected to the pixel circuit; A protection circuit formed on a first substrate, a planarization film formed on the pixel circuit, an ITO formed on the second substrate, and between the first and second substrates A holding liquid crystal composition, and a TAB-shaped driving IC electrically connected to the lead
An electro-optical device, comprising: the protection circuit includes silicon. 3. A pixel circuit having thin film transistors formed on the first and second substrates having an insulating surface; a pixel circuit having a thin film transistor formed on the first substrate; a lead electrically connected to the pixel circuit; A protection circuit formed on a first substrate, a planarization film formed on the pixel circuit, an ITO formed on the second substrate, and between the first and second substrates A holding liquid crystal composition, and a TAB-shaped driving IC electrically connected to the lead
An electro-optical device comprising: the protection circuit includes doped silicon. 4. A pixel circuit having thin film transistors formed on the first and second substrates having an insulating surface; a pixel circuit having a thin film transistor formed on the first substrate; a lead electrically connected to the pixel circuit; A protection circuit formed on a first substrate, a planarization film formed on the pixel circuit, an ITO formed on the second substrate, and between the first and second substrates A holding liquid crystal composition, and a TAB-shaped driving IC electrically connected to the lead
And wherein the protection circuit includes a thin film transistor and ITO, and one of a source and a drain of the thin film transistor is electrically connected to a gate of the thin film transistor. Electro-optical device. 5. A pixel circuit having a thin film transistor formed on the first and second substrates having an insulating surface; a pixel circuit having a thin film transistor formed on the first substrate; a lead electrically connected to the pixel circuit; A protection circuit formed on a first substrate, a planarization film formed on the pixel circuit, an ITO formed on the second substrate, and between the first and second substrates A holding liquid crystal composition, and a TAB-shaped driving IC electrically connected to the lead
Wherein the protection circuit includes an N-channel thin film transistor, a P-channel thin film transistor, and ITO, and one of a source or a drain and a gate of the N-channel thin film transistor is the P-type thin film transistor. One of a source and a drain of the channel-type thin film transistor and a gate thereof are electrically connected, and the other of the source and the drain of the N-channel thin film transistor is electrically connected to the other of the source and the drain of the P-channel thin film transistor An electro-optical device, comprising: 6. A first and second substrate having an insulating surface, a pixel circuit having a thin film transistor formed on the first substrate, a lead electrically connected to the pixel circuit, A protection circuit formed on a first substrate, an organic resin film formed on the pixel circuit, an ITO formed on the second substrate, and between the first and second substrates A holding liquid crystal composition, and a TAB-shaped driving IC electrically connected to the lead
An electro-optical device comprising: an electro-optical device, wherein the protection circuit includes ITO. 7. A first and second substrate having an insulating surface, a pixel circuit having a thin film transistor formed on the first substrate, a lead electrically connected to the pixel circuit, A protection circuit formed on a first substrate, an organic resin film formed on the pixel circuit, an ITO formed on the second substrate, and between the first and second substrates A holding liquid crystal composition, and a TAB-shaped driving IC electrically connected to the lead
An electro-optical device, comprising: the protection circuit includes silicon. 8. A pixel circuit having a thin film transistor formed on the first and second substrates having an insulating surface; a pixel circuit having a thin film transistor formed on the first substrate; a lead electrically connected to the pixel circuit; A protection circuit formed on a first substrate, an organic resin film formed on the pixel circuit, an ITO formed on the second substrate, and between the first and second substrates A holding liquid crystal composition, and a TAB-shaped driving IC electrically connected to the lead
An electro-optical device comprising: the protection circuit includes doped silicon. 9. A pixel circuit having thin film transistors formed on the first and second substrates having an insulating surface; a pixel circuit having a thin film transistor formed on the first substrate; a lead electrically connected to the pixel circuit; A protection circuit formed on a first substrate, an organic resin film formed on the pixel circuit, an ITO formed on the second substrate, and between the first and second substrates A holding liquid crystal composition, and a TAB-shaped driving IC electrically connected to the lead
And wherein the protection circuit includes a thin film transistor and ITO, and one of a source and a drain of the thin film transistor is electrically connected to a gate of the thin film transistor. Electro-optical device. 10. A first and second substrate having an insulating surface; a pixel circuit having a thin film transistor formed on the first substrate; a lead electrically connected to the pixel circuit; A protection circuit formed on a first substrate, an organic resin film formed on the pixel circuit, an ITO formed on the second substrate, and between the first and second substrates A holding liquid crystal composition, and a TAB-shaped driving IC electrically connected to the lead
Wherein the protection circuit includes an N-channel thin film transistor, a P-channel thin film transistor, and ITO, and one of a source or a drain and a gate of the N-channel thin film transistor is the P-type thin film transistor. One of a source and a drain of the channel-type thin film transistor and a gate thereof are electrically connected, and the other of the source and the drain of the N-channel thin film transistor is electrically connected to the other of the source and the drain of the P-channel thin film transistor An electro-optical device, comprising: