JP2754292B2 - Electro-optical device image display method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of displaying an image in a liquid crystal electro-optical device using a thin film transistor (hereinafter referred to as a TFT) as a driving switching element, and particularly to a gradation display for obtaining an intermediate color tone or light and shade. It is about the method. The present invention particularly relates to a so-called full digital gradation display for performing gradation display without applying any analog signal to an active element from the outside.

[0002]

2. Description of the Related Art Liquid crystal compositions have different dielectric constants in the horizontal and vertical directions with respect to the molecular axis due to their material properties. Can be easily done. The liquid crystal electro-optical device displays ON / OFF, that is, displays light and dark by controlling the amount of transmitted light or the amount of scattering of light using the anisotropy of the dielectric constant. As liquid crystal materials, TN (twisted nematic) liquid crystal, STN (super
Materials known as "twisted nematic" liquid crystal, ferroelectric liquid crystal, polymer liquid crystal or dispersion type liquid crystal are known. It is known that a liquid crystal does not respond to an external voltage in an infinitely short time, but takes a certain time to respond. The value is specific to each liquid crystal material. In the case of a TN liquid crystal, the value is several tens of msec.
The time is several hundred msec for N liquid crystal, several hundred μsec for ferroelectric liquid crystal, and several tens msec for dispersion type or polymer liquid crystal.

[0003] Among electro-optical devices using liquid crystals, the one that can obtain the best image quality is the one using the active matrix system. In a conventional active matrix type liquid crystal electro-optical device, a thin film transistor (TFT) is used as an active element, an amorphous or polycrystalline semiconductor is used for the TFT, and P
In this case, a TFT of only one of the N-type and the N-type was used. That is, in general, an N-channel TFT
(Referred to as NTFT) is connected in series to the pixel. Then, a signal voltage is applied to the signal lines of the matrix, and when signals are applied from both sides to the TFTs provided at the orthogonal portions of the respective signal lines, the ON / OFF state of the liquid crystal pixels is utilized by utilizing the fact that the TFTs are turned ON. OFF was individually controlled. By controlling the pixels by such a method, a liquid crystal electro-optical device having a high contrast can be realized.

[0004]

However, in such an active matrix system, it is extremely difficult to perform gradation display such as light and dark and color tone. Conventionally, for gray scale display, a method has been studied which utilizes the fact that the light transmittance of a liquid crystal changes depending on the magnitude of an applied voltage. This is, for example, the source of the TFT in the matrix.
By supplying an appropriate voltage from the peripheral circuit between the drains and applying a signal voltage to the gate electrode in that state,
It is intended to apply a voltage of that magnitude to the liquid crystal pixels.

However, in such a method, for example, due to the inhomogeneity of the TFT and the inhomogeneity of the matrix wiring, the voltage actually applied to the liquid crystal pixels differs by at least several% depending on each pixel. Oops. On the other hand, for example, the voltage dependence of the light transmittance of the liquid crystal is extremely non-linear, and the light transmittance changes rapidly at a specific voltage. In some cases it was significantly different. Therefore, in practice, achieving 16 gradations has been the limit.

[0006] As described above, the difficulty of gradation display is extremely disadvantageous in that the liquid crystal display device competes with a conventional general display device such as a cathode ray tube (CRT).

An object of the present invention is to propose a completely new method for realizing a gradation display which has been difficult in the past.

[0008]

[Means for Solving the Problem] As mentioned above, it is possible to control the light transmittance of the liquid crystal by controlling the voltage applied to the liquid crystal in an analog manner. It has been found that gradation can be visually obtained by controlling the time during which voltage is applied to the liquid crystal.

For example, when a TN (twisted nematic) liquid crystal, which is a typical liquid crystal material, is used,
For example, in FIG. 1A, when comparing a case where a rectangular pulse as shown by A is applied with a case where a rectangular pulse as shown by C is applied, it is found that A is brighter. . Here, the pulse period was 1 msec. As a result, A was the brightest, and then B, C, and D in that order. This is completely unexpected. This is because in the above-mentioned ordinary TN liquid crystal material, 1 ms
The time ec is too short, and the TN liquid crystal does not react in such a short time. Therefore, in any case, it is impossible to realize the ON state of the liquid crystal. However, in reality, the liquid crystal was able to realize an intermediate density.

The specific principle is not yet known in detail. However, the present inventors have found that gradation expression can be performed using this phenomenon. That is, by applying a pulse to the liquid crystal material at a period such that the liquid crystal material does not react, by controlling the pulse width, an intermediate brightness is realized by digital control, which is exactly the feature of the present invention. Things. As a result of the study of the present inventors, it has been found that the pulse period for obtaining such an intermediate density needs to be 10 msec or less in the case of a TN liquid crystal.

Here, the meaning of the term pulse period will be clarified. That is, in this case,
A plurality of pulses are continuously applied to the liquid crystal. In this case, the pulse cycle refers to the time from the start of one pulse to the start of the next pulse.
Therefore, it is the reciprocal of the pulse repetition frequency. The pulse width refers to a time during which a pulse is in a voltage state. Therefore, in FIG. 1, for example, in the case of a pulse train of C, T is the pulse period, and τ is the pulse width.

A similar effect was observed in the STN liquid crystal, the ferroelectric liquid crystal, and the polymer liquid crystal or the dispersion type liquid crystal. In each case, it became clear that an intermediate color tone can be obtained by applying a pulse having a period shorter than the response time. That is, S
100 msec or less, preferably 10 msec or less for a TN liquid crystal, and 100 μsec or less for a ferroelectric liquid crystal.
sec or less, preferably 10 μsec or less, and 10 msec or less for polymer liquid crystal or dispersion type liquid crystal.
Preferably, by applying a pulse having a cycle of 1 msec or less, a gradation display was obtained.

Normally, for an image of a television or the like, 30 times per second is required.
The still images are sequentially fed out to form a moving image. Therefore, the duration of one still image is about 30 msec.
It is. This time is too early for the human eye,
It is literally “not to be caught”, and as a result, still images cannot be visually identified one by one. In any case, in order to obtain a normal moving image, one still image cannot be continued for 100 msec or longer at the longest.

If 256 gradations are to be displayed using the present invention, for example, if T = 3 msec,
It is necessary to adopt a pulse voltage application method capable of dividing the time of 3 msec by at least 256 as a method of applying a voltage to a pixel. That is, at least 3 msec /
It is necessary to form a circuit in which a pulse voltage of 256 = 11.7 μsec is applied to the pixel. Actually, as shown in FIG. 3, the duty ratio τ / T of the pulse and the light transmittance of the liquid crystal pixel are in a non-linear relationship. In order to obtain 256 gradations, the duty ratio of the pulse must be further reduced. Fine control is necessary.

In addition, when an actual image is displayed, other pixels must be considered. In an actual image display device, for example, there are as many as 400 rows. That is,
As will be described later, the number of active elements in the matrix is 10
An extremely short response of 0 nsec is required. Therefore, an example of a circuit having such a short-time response is shown in FIG.
Hereinafter, the description will be made.

FIG. 4 shows an example of an active matrix circuit of a liquid crystal display device necessary for carrying out the present invention. In the present invention, since the active element is required to respond in a short time of 100 nsec or less, it is necessary to form a circuit that operates at high speed. For this purpose, instead of using only the NTFT or PTFT as in the conventional switching, a modified inverter type circuit configured so that the NTFT and PTFT operate complementarily as shown in FIG. 4 is used. is required.

In this example, an example of an N × M matrix is shown. However, in order to reduce complexity, n
Only the vicinity of the row m column is shown. If you expand the same thing up, down, left and right, you will get a complete one.

FIG. 4 illustrates four modified inverter circuits. Each modified inverter circuit includes at least two NTFTs and at least two PTFTs.
The number of TFTs may be further increased in case of a defect. In this circuit, first, a gate electrode of a pair of NTFTs and PTFTs at the center is connected to a signal line _Xn , and one of the sources or drains of the NTFTs and PTFTs is connected to each other _{. m} is connected to the electrode. This state is the same as that of a normal complementary field effect device (CMOS). This NTFT and PT
The other source or drain of the FT is connected to the source or drain of the second NTFT or PTFT, respectively. The other source or drain of the second NTFT and PTFT is connected to the signal line Y, respectively.
It is connected to _{m + 1} and Y _m. Further, the second NTF
The gate electrodes of T and PTFT are respectively connected to the signal line Y _{m + 1}
It is connected to Y _m and. In the following, the signal lines X1 _, X2 _{, ...}
The X _N, collectively or individually referred to as X-rays, the signal lines Y _1, Y _{2, ..} a Y _M, referred to collectively as, or individually Y line. Although not shown in the figure, a capacitor may be artificially inserted in parallel with the capacitor of the pixel. The capacitor inserted at this time has an action of suppressing a decrease in voltage of the pixel due to spontaneous discharge. The capacity of the capacitor is appropriately several times to about 100 times, preferably 10 times the capacity of the pixel. The reason for this is that the existence of an excessive capacity hinders the high-speed operation which is the object of the present invention and is a feature of the present invention.

Next, an example of the operation of the circuit when such a circuit is used will be described with reference to FIGS. This matrix circuit needs to operate so as to apply a pulsed voltage as shown in FIG. 1A to the liquid crystal cell. FIG. 1B shows an outline of the signal voltages applied to the X-rays and the Y-lines to generate such a pulse. As an example, consider a 400 × 640 matrix.

The signal applied to the X-ray is represented by V (X _n ) in the case of the X _n line, for example, which is actually 256 out of a group of pulses repeated in the period T. Pulse (hereinafter referred to as sub-pulse),
Further, each of the 256 sub-pulses is 400
It can be seen that the pulse train is composed of a pulse train including a number of elements. Here, the number 400 is the number of rows in the matrix. Therefore, if T = 3 msec, the minimum unit of the pulse applied to the X-ray is 29 nsec.

On the other hand, during the time T / 256,
V (Y ₁ ), V (Y _m ), V (Y _{m + 1} ), V (Y
₄₀₀ ) are applied with their respective timings shifted. This pulse needs to be even shorter than the minimum unit pulse of the pulse applied to the X-ray. Eventually, during the time T, 256 pulses are applied to each Y line.

Next, the operation of the actual circuit will be described with reference to FIG. First, a first sub-pulse is applied to each X-ray. Of course, these sub-pulses are different for each X-ray. On the other hand, as described above, a pulse is applied to the Y line in order of Y ₁ and then Y ₂ . First, consider the case where pulse is applied to Y _1. At this time, the active element connected to the pixel Z _1,1 is turned off. That, Y ₁ is the voltage state, and since Y ₂ are not voltage state, among the four TFT active elements of a pixel, NTFT of PTFT and under the above turned ON, the state in which the center of the inverter is operated is there. Then, since the input X ₁ of the inverter being applied voltage, the output is in a state of not applied with voltage is inverted. Then, although the voltage applied to the Y _2, at this time, a state of suffering of voltage to the pixel Z _{1, 2.} That is, the input X ₁ of the inverter because no voltage is applied. Then, this voltage state is continued even after the pulse of the Y ₂ is turned off, then persists until a pulse is applied to Y _2. Similarly, Z _{1, m} and Z _{1, m + 1} are also Z _1,400
Is also in a voltage state.

[0023] In this manner, it pulses Yuki is applied in sequence, consider the case where it is applied to the Y _m. Now, _{assuming that} four pixels Zn _{, m} , Zn _{, m + 1} , Zn _{+ 1, m} , and Zn _{+ 1, m + 1} are focused on, the _Xn and _{Xn + 1} Attention should be paid to the m-th and (m + 1) -th sub-pulses. Since neither the _Xn nor the _{Xn + 1} is in the m-th voltage state, the pixels Zn _{, m} , Z
_{n + 1 and m} are in a voltage (charged) state. Next, a pulse is applied to Y _{m + 1} . Since neither the _Xn nor the _{Xn + 1} is in the (m + 1) -th voltage state, the pixels Zn _{, m + 1} , Z
_{n + 1 and m + 1} are charged.

Next, although omitted in the figure, it is assumed that a second sub-pulse has arrived. At this time, if the m-th and (m + 1) -th voltage states of both X _n and X _{n + 1} are not in the voltage state, the charged state is not lost, and the four pixels continue to be in the voltage state. Thereafter, it is assumed that the voltage state of all four pixels continues until the (h-1) th sub-pulse.

Next, it is assumed that the sub-pulse advances and the h-th sub-pulse arrives. In the figure, to avoid complexity, m
The other than the (th) and (m + 1) th are omitted. At this time,
Since neither the _Xn nor the _{Xn + 1} is in the m-th voltage state, the pixel Z
_{n, m} and Zn _{+ 1, m} continue the voltage state. However, X _{n + 1}
Since the (m + 1) -th is in the voltage state, the pixel Z
_{n + 1 and m} indicate that the pixel Z
_{In the case of n + 1 and m + 1} , the output of the active element is not in the voltage state, the stored charge is released, and the voltage state is interrupted.

Further, when the i-th sub-pulse arrives, since the (m + 1) -th of X _n is in the voltage state, Z _n
The charge state of _{n, m + 1} is released. Hereinafter, the j-th and k-th
, The m-th of X _{n + 1} and X _n are in the voltage state, respectively, so that the charged states of the pixels Zn _{, m} and Zn _{+ 1, m} are k-th and j-th, respectively. Is interrupted during the sub-pulse. Through such a process, V in FIG.
As shown in (Z), the time of the voltage state can be digitally controlled for each pixel.

By repeating such an operation, the width of the voltage pulse applied to each pixel can be arbitrarily controlled as shown in FIG.

As is apparent from the above description, in practicing the present invention, the sub-pulses as described above do not have to be clearly defined pulse-like. For the sake of simplicity, the concept of sub-pulses has been introduced. In particular, it is apparent that the present invention can be implemented even if the sub-pulses are not clear and the signals have almost no boundaries. is there. Furthermore, for simplicity of explanation, the zero level and voltage level of the signal are clarified, but this is only a matter of whether the voltage is below or above the threshold voltage of the liquid crystal or TFT. It need not be absolutely zero. In addition, since the voltage is a relative physical quantity with reference to the potential at an arbitrary point, in the above example, it is apparent that the pulse may have the opposite polarity. Further, an appropriate offset voltage may be applied to the counter electrode of the pixel. In the above example, the screen is 1
Scanning was performed line by line, but first Y1 _, Y3 _, Y
_5, scan _... and so, _{then, Y 2, Y 4, Y} 6, scans and so _.. but can naturally be also called interlaced scanning method.

[0029]

【Example】

Example 1 In this example, a wall-mounted television was manufactured using a liquid crystal display device having a circuit configuration as shown in FIG. The TFT at that time was made of polycrystalline silicon using laser annealing.

FIG. 5 shows an actual arrangement of electrodes and the like corresponding to this circuit configuration for one pixel. First, a method for manufacturing a liquid crystal panel used in this embodiment will be described with reference to FIGS. In order to carry out the present invention, two NTFTs and two PTFTs are required for one pixel.
Although a total of four TFTs are shown in the figure, for simplicity, the numbers are given to only one of the NTFT and PTFT. FIG.
In (A), a silicon oxide film as a blocking layer 51 is formed on a glass 50 that can withstand a heat treatment of inexpensive 700 ° C. or less, for example, about 600 ° C., such as quartz glass, by using a magnetron RF (high frequency) sputtering method.
It is made to a thickness of 0 °. The process conditions were a 100% oxygen atmosphere, a film formation temperature of 15 ° C., an output of 400 to 800 W, and a pressure of 0.5 Pa. The film formation rate using quartz or single crystal silicon as a target was 30 to 100 ° / min.

A silicon film 52 was formed thereon by a plasma CVD method. The film formation temperature is from 250 ° C to 35
In this example, the temperature was set to 320 ° C., and monosilane (SiH
₄ ) was used. Not only monosilane (SiH ₄ ) but also disilane (Si ₂
H ₆ ) Alternatively, trisilane (Si ₃ H ₈ ) may be used. These were introduced into the PCVD apparatus at a pressure of 3 Pa, and 13.56 M
The film was formed by applying a high frequency power of Hz. At this time, an appropriate high frequency power is 0.02 to 0.10 W / cm ² , and in this example, 0.055 W / cm ² was used. The flow rate of monosilane (SiH ₄ ) was set to 20 SCCM, and the deposition rate at that time was about 120 ° / min. In order to control the threshold voltage (Vth) of the PTFT and the NTFT to be approximately the same, boron is used for diborane in a concentration of 1 × 10 ¹⁵ to 1 × 10 ¹⁸ cm.
^-3 may be added during film formation. In addition, not only the plasma CVD but also a sputtering method and a low pressure CVD method may be used for forming the silicon layer to be a channel region of the TFT, and the method will be briefly described below.

When the sputtering method is used, the back pressure before the sputtering is set to 1 × 10 ⁻⁵ Pa or less, and single crystal silicon is used as a target in an atmosphere in which hydrogen is mixed with 20 to 80% of argon. For example, argon was 20% and hydrogen was 80%.
The film formation temperature was 150 ° C., the frequency was 13.56 MHz, the sputter output was 400 to 800 W, and the pressure was 0.5 Pa.

In the case of forming by a reduced pressure gas phase method, 450 to 550 ° C. lower by 100 to 200 ° C. than the crystallization temperature, for example, 5 to 5 ° C.
Disilane (Si ₂ H ₆ ) or trisilane (Si ₃ H ₈ ) was supplied to the CVD apparatus at 30 ° C. to form a film. The reactor pressure is 30 ~
It was set to 300 Pa. The deposition rate was 50-250 ° / min. Suresshuho the PTFT and NTFT - for controlling field voltage (Vth) in substantially the same, boron may be added during deposition as the concentration of ^{1 × 10 15 ~1 × 10 18} cm -3 by using diborane .

The coatings formed by these methods are:
It is preferable that oxygen is 5 × 10 ²¹ cm ⁻³ or less. In order to promote crystallization, the oxygen concentration should be 7 × 10 ¹⁹ cm ⁻³ or less,
Preferably, it is desirable to be 1 × 10 ¹⁹ cm ⁻³ or less,
If the amount is too small, the leakage current in the off state increases due to the backlight, so this concentration was selected. If the oxygen concentration is high, crystallization is difficult, and the laser annealing temperature must be increased or the laser annealing time must be increased. Hydrogen is 4 × 10 ²⁰ cm ⁻³ and silicon 4 × 10 ²²
When compared with cm ^-3 , it was 1 atomic%.

In order to further promote crystallization of the source and the drain, the oxygen concentration is set to 7 × 10 ¹⁹ cm ⁻³ or less, preferably 1 × 10 ¹⁹ cm ⁻³ or less,
Oxygen may be added only to the T channel formation region by ion implantation so as to have a concentration of 5 × 10 ^{20 to} 5 × 10 ²¹ cm ⁻³ .
According to the above method, the amorphous silicon film is
The film was formed to have a thickness of 5000 to 5000 Å, and 1000 Å in this embodiment.

Thereafter, the photoresist 53 is masked with a mask P1.
Was used to form a pattern in which only the source / drain regions were opened. A silicon film 54 serving as an n-type active layer was formed thereon by a plasma CVD method. Film formation temperature is 250 ° C
The temperature is set to 320 ° C. in this embodiment, and monosilane (SiH ₄ ) and monosilane-based phosphine (P
H ₃ ) A 3% concentration was used. These were introduced into the PCVD apparatus at a pressure of 5 Pa, and high-frequency power of 13.56 MHz was applied to form a film. At this time, the high frequency power is 0.05 to
0.20 W / cm ² is appropriate, and in this embodiment, 0.1 W / cm ^2.
20 W / cm ² was used.

The specific conductivity of the n-type silicon layer formed by this method was about 2 × 10 ⁻¹ [Ωcm ⁻¹ ]. The film thickness was 50 °. Thereafter, the resist 53 is removed by a lift-off method, and the n-type impurity diffusion seed region 55 is removed.
Was formed.

Using the same process, a p-type active layer was formed. The gas introduced at that time used monosilane (SiH ₄ ) and monosilane-based diborane (B ₂ H ₆ ) at a concentration of 5%. These were introduced into a PCVD apparatus at a pressure of 4 Pa, and high-frequency power of 13.56 MHz was applied to form a film.
At this time, the high-frequency power is suitably 0.05~0.20W / cm ^2, in this embodiment using 0.120W / cm ^2. The specific conductivity of the p-type silicon layer obtained by this method was about 5 × 10 ^-2 [Ωcm ^-1 ]. The film thickness was 50 °. Thereafter, an n-type impurity diffusion seed region 59 was formed by using a lift-off method as in the case of the N-type region. Thereafter, the silicon film 52 is etched away using the mask P3, and the island region 6 for the N-channel thin film transistor is removed.
3 and island region 6 for P-channel type thin film transistor
4 was formed.

Thereafter, the source, drain, and channel regions were laser-annealed using a XeCl excimer laser, and at the same time, the active layer was laser-doped. At this time, the laser energy has a threshold energy of 130 mJ / cm ^2.
mJ / cm ² is required. However, 220m from the beginning
When energy of J / cm ² or more is irradiated, hydrogen contained in the film is rapidly released, and the film is destroyed. For this purpose, it is necessary to first displace hydrogen and then melt it with low energy. In this embodiment, first 150 m
After purging hydrogen at J / cm ² , 230mJ
The crystallization was carried out at / cm ² .

On this, a silicon oxide film was formed as a gate insulating film to a thickness of 500 to 2000 {for example, 1000}. This was made under the same conditions as those for forming the silicon oxide film as the blocking layer. During the film formation, a small amount of fluorine may be added to fix the sodium ions.

Thereafter, 1 to 5 × 10 ²¹ cm of phosphorus is placed on the upper side.
^-3 silicon film or molybdenum (Mo), tungsten (W), MoSi ₂ or
A multilayer film with WSi ₂ was formed. This was patterned using a fourth photomask P4 to obtain FIG. 6 (D). A gate electrode 66 for NTFT and a gate electrode 67 for PTFT were formed. For example, the channel length is 7 μm, and the gate electrode is 0.2 μm of phosphorus silicon, and 0.3 μm of molybdenum is placed thereon.
It was formed to a thickness of μm.

When aluminum (Al) is used as a gate electrode material, the surface is anodized after patterning with a fourth photomask P4, so that the self-alignment method can be applied. In addition, since the source / drain contact holes can be formed at positions closer to the gate, the characteristics of the TFT can be further improved by reducing the mobility and the threshold voltage.

Thus, a C / TFT can be manufactured without applying a temperature to 400 ° C. or more in all steps. Therefore, it is not necessary to use an expensive substrate such as quartz as a substrate material, and it can be said that the process is very suitable for the large-screen liquid crystal display device of the present invention.

In FIG. 6E, a silicon oxide film was formed on the interlayer insulator 68 by the above-mentioned sputtering method. This silicon oxide film is formed by LPCVD, optical CVD
Or a normal pressure CVD method. For example, 0.2-0.
6 μm thick, and then a fifth photomask P
5 was used to form an electrode window 79. After that, further, aluminum is formed on the entire surface to a thickness of 0.3 μm by a sputtering method, and leads 74 and contacts 73 and 75 are formed using a sixth photomask P6.
The surface was coated with an organic resin 77 for flattening, for example, a translucent polyimide resin, and the electrode drilling was performed again using the seventh photomask P7. Further, ITO (indium tin oxide) was formed on the entire surface by sputtering to a thickness of 0.1 μm, and a pixel electrode 71 was formed using an eighth photomask P8. This ITO is deposited at room temperature to 150 ° C.
Fulfilled by oxygen at 0-400 ° C. or by annealing in air.

The electrical characteristics of the obtained TFT are PTFT
And the mobility is 40 (cm ² / Vs), Vth is -5.9 (V),
NTFT has a mobility of 80 (cm ² / Vs) and a Vth of 5.0
(V).

One substrate for a liquid crystal electro-optical device manufactured according to the above method was obtained. FIG. 5 shows the arrangement of the electrodes and the like of the liquid crystal display device.
TFTs constituting the modified inverter according to the present invention are provided between the signal lines Y ₁ and Y ₂ and between Y ₂ and Y ₃ in parallel with the signal lines X ₁ and X ₂ . Such C / T
A matrix configuration using FT was provided. By repeating such a structure left and right, up and down, 640 × 480,
A liquid crystal display device having a large pixel size of 1280 × 960 can be obtained. In this embodiment, the size is set to 1920 × 400.
Thus, a first substrate was obtained.

FIG. 7 shows a method for manufacturing the other substrate. A polyimide resin obtained by mixing a black pigment with polyimide is formed on a glass substrate to a thickness of 1 μm using a spin coating method,
Black stripe 8 using ninth photomask P9
1 was produced. After that, a film of a polyimide resin mixed with a red pigment was formed to a thickness of 1 μm using a spin coating method,
Red filter 8 using tenth photomask P10
3 was produced. Similarly, a green filter 85 and a blue filter 86 were manufactured using the masks P11 and P12. During the production, each filter was fired at 350 ° C. in nitrogen for 60 minutes. After that, the leveling layer 89 was formed using transparent polyimide also by using the spin coating method.

Thereafter, ITO (indium tin oxide) was formed on the entire surface to a thickness of 0.1 μm by sputtering, and a common electrode 90 was formed using a tenth photomask P10. This ITO is deposited at room temperature to 150 ° C.
Fulfilled with oxygen at 0-300 ° C. or in air, a second substrate was obtained.

A polyimide precursor was printed on the substrate by an offset method, and baked at 350 ° C. for 1 hour in a non-oxidizing atmosphere, for example, nitrogen. Thereafter, a known rubbing method was used to modify the surface of the polyimide, and at least initially, a means for aligning liquid crystal molecules in a certain direction was provided.

Thereafter, the nematic liquid crystal composition was sandwiched between the first substrate and the second substrate, and the periphery was fixed with an epoxy adhesive. A drive IC having a TAB shape and a PCB having a common signal and potential wiring were connected to leads on the substrate, and a polarizing plate was attached on the outside to obtain a transmissive liquid crystal electro-optical device. This was connected to a rear lighting device in which three cold cathode tubes were arranged, and a tuner for receiving TV radio waves to complete a wall-mounted TV. Compared to a conventional CRT system television, the device has a flat shape, so that it can be installed on a wall or the like. The operation of this liquid crystal television was confirmed by applying signals substantially equivalent to those shown in FIGS. 1 and 2 to the liquid crystal pixels.

Example 2 In this example, a wall-mounted television was manufactured using a liquid crystal display device having a circuit configuration as shown in FIG. 4, and a description thereof will be given. Also T at that time
FT was polycrystalline silicon using laser annealing.

Hereinafter, a method of manufacturing the TFT portion will be described with reference to FIG. In FIG. 8 (A), an inexpensive quartz glass or the like of 700 ° C. or less, for example, about 600 ° C.
Magnetron RF on glass 100 that can withstand heat treatment
(High frequency) A silicon oxide film as the blocking layer 101 is formed to a thickness of 1000 to 3000 ° by using a sputtering method. Process conditions are 100% oxygen atmosphere, film formation temperature 1
The temperature was 5 ° C., the output was 400 to 800 W, and the pressure was 0.5 Pa.
The film formation rate using quartz or single crystal silicon as a target was 30 to 100 ° / min.

A silicon film 102 was formed thereon by a plasma CVD method. Film formation temperature is 250 ° C-3
In this example, the temperature was set to 320 ° C.
iH ₄ ) was used. Not only monosilane (SiH ₄ ), but disilane (S
i ₂ H ₆ ) Alternatively, trisilane (Si ₃ H ₈ ) may be used. These were introduced into the PCVD apparatus at a pressure of 3 Pa, and 13.56
The film was formed by applying a high frequency power of MHz. At this time, an appropriate high frequency power is 0.02 to 0.10 W / cm ² , and in this example, 0.055 W / cm ² was used. The flow rate of monosilane (SiH ₄ ) was set to 20 SCCM, and the deposition rate at that time was about 120 ° / min. In order to control the threshold voltage (Vth) of the PTFT and the NTFT to be substantially the same, boron is used in a concentration of 1 × 10 ¹⁵ to 1 × 10 ¹⁸ using diborane.
It may be added during film formation as a concentration of cm ^-3 . Also TFT
In addition to the plasma CVD, the silicon layer serving as the channel region may be formed by a sputtering method or a low-pressure CVD method. The method will be briefly described below.

In the case of the sputtering method, the back pressure before the sputtering was set to 1 × 10 ⁻⁵ Pa or less, and single crystal silicon was used as a target in an atmosphere in which 20 to 80% of hydrogen was mixed with argon. For example, argon was 20% and hydrogen was 80%.
The film formation temperature was 150 ° C., the frequency was 13.56 MHz, the sputter output was 400 to 800 W, and the pressure was 0.5 Pa.

In the case of forming by a reduced pressure gas phase method, 450 to 550 ° C. lower by 100 to 200 ° C. than the crystallization temperature, for example, 5 to 5 ° C.
Disilane (Si ₂ H ₆ ) or trisilane (Si ₃ H ₈ ) was supplied to the CVD apparatus at 30 ° C. to form a film. The reactor pressure is 30 ~
It was set to 300 Pa. The deposition rate was 50-250 ° / min. Suresshuho the PTFT and NTFT - for controlling field voltage (Vth) in substantially the same, boron may be added during deposition as the concentration of ^{1 × 10 15 ~1 × 10 18} cm -3 by using diborane .

The coatings formed by these methods are:
It is preferable that oxygen is 5 × 10 ²¹ cm ⁻³ or less. In order to promote crystallization, the oxygen concentration should be 7 × 10 ¹⁹ cm ⁻³ or less,
Preferably, it is desirable to be 1 × 10 ¹⁹ cm ⁻³ or less,
If the amount is too small, the leakage current in the off state increases due to the backlight, so this concentration was selected. If the oxygen concentration is high, crystallization is difficult, and the laser annealing temperature must be increased or the laser annealing time must be increased. Hydrogen is 4 × 10 ²⁰ cm ⁻³ and silicon 4 × 10 ²²
When compared with cm ^-3 , it was 1 atomic%.

In order to further promote crystallization of the source and the drain, the oxygen concentration is set to 7 × 10 ¹⁹ cm ⁻³ or less, preferably 1 × 10 ¹⁹ cm ⁻³ or less,
Oxygen may be added only to the T channel formation region by ion implantation so as to have a concentration of 5 × 10 ^{20 to} 5 × 10 ²¹ cm ⁻³ .
According to the above method, the amorphous silicon film is
The film was formed to have a thickness of 5000 to 5000 Å, and 1000 Å in this embodiment.

After that, the photoresist 103 is
Should be used as source / drain region of NTFT using 1
A pattern in which only the region was opened was formed. And Regis
Using ion 103 as an ion implantation method with mask 103
Than 2 × 10¹⁴~ 5 × 10 ¹⁶cm^-2, Preferably 2x
10¹⁶cm^-2Only to form the n-type impurity region 104.
Done. After that, the resist 103 was removed.

Similarly, a resist 105 was applied, and using the mask P3, a pattern was formed in which only the regions to be the source / drain regions of the PTFT were opened. Then, using the resist 105 as a mask, a p-type impurity region was formed. Boron was used as the impurity, and the impurity was introduced by ion implantation again in an amount of 2 × 10 ^{14 to} 5 × 10 ¹⁶ cm ⁻² , preferably 2 × 10 ¹⁶ cm ⁻² . Like this. FIG. 8B is obtained.

Thereafter, a thickness of 50 to 3 is formed on the silicon film 102.
00 nm, for example, 100 nm silicon oxide film 107
Was formed by the above-mentioned RF sputtering method. And
Using a XeCl excimer laser, the source, drain and channel regions are crystallized by laser annealing.
Activated. At this time, the threshold energy of the laser energy is 130 mJ / cm ² , and 220 mJ / cm ² is required to melt the entire film thickness. However, when an energy of 220 mJ / cm ² or more is irradiated from the beginning, hydrogen contained in the film is rapidly released, and the film is destroyed. For this purpose, it is necessary to first displace hydrogen and then melt it with low energy. In this embodiment, first
After purging hydrogen at 50 mJ / cm ² , 23
Crystallization was performed at 0 mJ / cm ² . Further, after the end of the laser annealing, the silicon oxide film 107 was removed.

Thereafter, an island-like NTFT region 111 and a PTFT region 112 were formed using a photomask P3. On this, a silicon oxide film 108 was formed as a gate insulating film to a thickness of 500 to 2000 {for example, 1000}. This was made under the same conditions as those for forming the silicon oxide film as the blocking layer. During the film formation, a small amount of fluorine may be added to fix the sodium ions.

After this, 1-5 × 10 ²¹ cm of phosphorus is placed on the upper side.
^-3 silicon film or molybdenum (Mo), tungsten (W), MoSi ₂ or
A multilayer film with WSi ₂ was formed. This was patterned using a fourth photomask P4 to obtain FIG. 8D. A gate electrode 109 for NTFT and a gate electrode 110 for PTFT were formed. For example, a channel length is 7 μm, and a gate electrode is formed of 0.2 μm of phosphorus silicon, and a molybdenum is formed thereon with a thickness of 0.3 μm.

When aluminum (Al) is used as a gate electrode material, the surface is anodized after patterning with a fourth photomask P4, so that the self-alignment method can be applied. In addition, since the source / drain contact holes can be formed at positions closer to the gate, the characteristics of the TFT can be further improved by reducing the mobility and the threshold voltage.

Thus, a C / TFT can be manufactured without applying a temperature to 400 ° C. or more in all steps. Therefore, it is not necessary to use an expensive substrate such as quartz as a substrate material, and it can be said that the process is very suitable for the large-screen liquid crystal display device of the present invention.

In FIG. 8E, a silicon oxide film was formed on the interlayer insulator 113 by the above-described sputtering method. This silicon oxide film is formed by LPCVD, optical CVD
Or a normal pressure CVD method. For example, 0.2-0.
6 μm thick, and then a fifth photomask P
5 was used to form a window 117 for an electrode. Thereafter, aluminum is further formed on the entire surface by a sputtering method to a thickness of 0.3 μm, and leads 116 and contacts 114 and 115 are formed using a sixth photomask P6. 119, for example, a translucent polyimide resin was applied and formed, and an electrode hole was formed again using the seventh photomask P7. In addition, these
TO (indium tin oxide) was formed to a thickness of 0.1 μm by a sputtering method, and a pixel electrode 118 was formed using an eighth photomask P8. This ITO film is formed at room temperature to 150 ° C., and oxygen at 200 to 400 ° C. or annealed in air.
Fulfilled by Le.

The electrical characteristics of the obtained TFT are PTFT
And the mobility is 35 (cm ² / Vs), Vth is -5.9 (V),
The mobility of NTFT is 90 (cm ² / Vs) and Vth is 4.8.
(V).

One substrate for a liquid crystal electro-optical device manufactured according to the above method was obtained. The method for fabricating the other substrate is the same as that in the first embodiment, and will not be described.
Thereafter, the nematic liquid crystal composition was sandwiched between the first substrate and the second substrate, and the periphery was fixed with an epoxy adhesive. A drive IC having a TAB shape and a PCB having a common signal and potential wiring were connected to leads on the substrate, and a polarizing plate was attached on the outside to obtain a transmissive liquid crystal electro-optical device. This was connected to a rear lighting device in which three cold cathode tubes were arranged, and a tuner for receiving TV radio waves to complete a wall-mounted TV. Compared to a conventional CRT system television, the device has a flat shape, so that it can be installed on a wall or the like. The operation of this liquid crystal television was confirmed by applying signals substantially equivalent to those shown in FIGS. 1 and 2 to the liquid crystal pixels.

[0068]

The present invention is characterized in that digital gray scale display is performed in contrast to the conventional analog gray scale display. As an effect, assuming a liquid crystal electro-optical device having a number of pixels of 640 × 400 dots, for example, it is very difficult to manufacture all the 256,000 TFTs without variation in characteristics. In consideration of mass productivity and yield, 16-gradation display is considered to be the limit. However, as in the present invention, gradation display is performed purely by digital control without adding analog signals at all. By doing so, gray scale display of 256 gray scale display or more is possible. Since it is a complete digital display,
The ambiguity of the gradation due to the variation in the characteristics of the FT was completely eliminated. Therefore, even if the variation in the TFT was slight, a very uniform gradation display was possible. Therefore, while the yield has been extremely low in order to obtain a TFT having a small variation, the yield of the TFT is no longer a problem according to the present invention. Was completed.

For example, 256,0 of 640 × 400 dots
When a normal analog gradation display is performed on a liquid crystal electro-optical device in which 00 sets of TFTs are formed in a 300 mm square,
Since there is about ± 10% variation in TFT characteristics,
Six gradation display was the limit. However, when the digital gradation display according to the present invention is performed, the display is hardly affected by the variation in the characteristics of the TFT elements, so that it is possible to display up to 256 gradations.
A variety of 16 colors can be displayed in subtle colors. In the case of displaying software such as television images, for example, even a “rock” made of the same color has a slightly different color due to its minute dents and the like. If you try to display something close to the colors of nature,
Difficulty is required for 16 gradations. With the gradation display according to the present invention, it is possible to impart these minute color changes.

In the embodiment of the present invention, T using silicon is used.
The explanation has been added focusing on FT.
FT can be used as well. In particular, the electron mobility of single crystal germanium is 3600 cm ² / Vs and the hole mobility is 1800 cm ² / Vs, which is the value of single crystal silicon (1350 cm ² / Vs in electron mobility and 480 c in hole mobility).
m ² / Vs), which is an excellent material for implementing the present invention that requires high-speed operation. In addition, germanium has a lower transition temperature from an amorphous state to a crystalline state than silicon, and is suitable for a low-temperature process. In addition, the nucleation rate during crystal growth is low, and therefore, generally, large crystals are obtained when polycrystals are grown. Thus, germanium has characteristics comparable to those of silicon.

In order to explain the technical concept of the present invention, an electro-optical device using liquid crystal, particularly a display device has been mainly described as an example. However, in order to apply the idea of the present invention, no display device is required. It is not necessary to use a so-called projection type television, another optical switch, or an optical shutter. Further, it is apparent that the present invention can be applied to electro-optical materials that are not limited to liquid crystals, as long as optical characteristics change due to electric influences such as electric fields and voltages.

[Brief description of the drawings]

FIG. 1 shows an example of a driving waveform according to the present invention.

FIG. 2 shows an example of a driving waveform according to the present invention.

FIG. 3 shows an example of gradation display characteristics of a liquid crystal according to the present invention.

FIG. 4 shows an example of a matrix configuration according to the invention.

FIG. 5 shows a planar structure of a device according to an example.

FIG. 6 shows a TFT process according to an embodiment.

FIG. 7 shows a process of a color filter according to an example.

FIG. 8 illustrates a TFT process according to an embodiment.

 ────────────────────────────────────────────────── ─── Continuation of front page (56) References JP-A-5-72564 (JP, A)

Claims (3)

(57) [Claims] An N signal lines X _1, X ₂ ,. .
_Xn,. . _XN and M signal lines Y1, orthogonal to it _.
Y ₂ ,. . Y _m,. . A wiring formed in a matrix by a Y _M, to the intersection area of each matrix, at least two N-channel type thin film transistor and the at least two P-channel thin film transistor, the pixel Z provided in the intersection region of the signal lines _{11, Z} 12,. . . Z
_mn,. . . And a Z _MN connects a first P-channel type thin film transistor and one of a source and a drain of the first N-channel thin film transistor, and connect it to the pixel electrode, the source and earthwork
Down the other, respectively, one of a source and a drain of the second P-channel thin film transistor is connected to one of a source and a drain of the second N-channel thin film transistor, the source of the second P-channel type thin film transistor
And the other drain signal lines _{Y 1, Y 2,.} .
Y _m,. . Connected to one signal line Y _m of Y _M, the source及Bido of the second N-channel thin film transistor
The other rain, provided next to the signal line _{Y m,} the signal lines _{Y 1, Y 2,.} . Y _m,. . Y One of _M
Connected to _one signal line Y _{m + 1} and the gate electrodes of the first N-channel thin film transistor and the first P-channel thin film transistor are connected in common to form signal lines X _1, X
_2,. . _Xn,. . Connected to one of the X _N, and connecting the gate electrode of the second P-channel type thin film transistor to the signal line Y _{m + 1,} the gate electrode of the second N-channel type thin film transistor to the signal line Y _m in the connected electro-optical device, while the signal on the signal line Y _m is applied, the signal
A signal having the opposite level to the above signal is applied to the line Y _{m + 1,} and from time T ₀ to T ₁ (T ₁ > T ₀ ) , the signal line X _n
With applying a voltage to the time the signal line _{Y m (T} 1 -T
A process of adding a short signal than _0), in the _{T 3 (T 3> T 2} > T 1) from the time _{T 2,} without adding a voltage to the signal line _{Y m} to the signal line _{X n,} the time (T
₃ -T ₂₎ and a process of adding a short signal than, therefore, the time _(T 1 _{-T 0)} applies a shorter signal
From time shorter than the time _(T 3 -T ₂₎ to the _{Y m}
Until the end of signal application, voltage is applied to the pixel electrode.
A display method characterized in that a grayscale display is realized by realizing a state where the image is displayed. 2. A semiconductor device comprising: N signal lines X _1, X ₂ ,. .
_Xn,. . _XN and M signal lines Y1, orthogonal to it _.
Y ₂ ,. . Y _m,. . A wiring formed in a matrix by a Y _M, to the intersection area of each matrix, at least two N-channel type thin film transistor and the at least two P-channel thin film transistor, the pixel Z provided in the intersection region of the signal lines _{11, Z} 12,. . . Z
_mn,. . . And a Z _MN connects a first P-channel type thin film transistor and one of a source and a drain of the first N-channel thin film transistor, and connect it to the pixel electrode, the source and Tolui
Down the other, respectively, one of a source and a drain of the second P-channel thin film transistor is connected to one of a source and a drain of the second N-channel thin film transistor, the source of the second P-channel type thin film transistor
And the other drain signal lines _{Y 1, Y 2,.} .
Y _m,. . Connected to one signal line Y _m of Y _M, the source及Bido of the second N-channel thin film transistor
The other rain, provided next to the signal line _{Y m,} the signal lines _{Y 1, Y 2,.} . Y _m,. . Y One of _M
Connected to _one signal line Y _{m + 1} and the gate electrodes of the first N-channel thin film transistor and the first P-channel thin film transistor are connected in common to form signal lines X _1, X
_2,. . _Xn,. . Connected to one of the X _N, and connecting the gate electrode of the second P-channel type thin film transistor to the signal line Y _{m + 1,} the gate electrode of the second N-channel type thin film transistor to the signal line Y _m A display method for displaying a signal by applying a pulse having a pulse period of 30 msec or less to a pixel electrode in a connected electro-optical device, wherein a gradation display is performed by changing a pulse width. . Wherein on a substrate, N signal lines _{X 1, X 2,.} .
_Xn,. . _XN and M signal lines Y1, orthogonal to it _.
Y ₂ ,. . Y _m,. . A wiring formed in a matrix by a Y _M, to the intersection area of each matrix, at least two N-channel type thin film transistor and the at least two P-channel thin film transistor, the pixel Z provided in the intersection region of the signal lines _{11, Z} 12,. . . Z
_mn,. . . And a Z _MN connects a first P-channel type thin film transistor and one of a source and a drain of the first N-channel thin film transistor, and connect it to the pixel electrode, the source and drain
Down the other, respectively, one of a source and a drain of the second P-channel thin film transistor is connected to one of a source and a drain of the second N-channel thin film transistor, the source of the second P-channel type thin film transistor
And the other drain signal lines _{Y 1, Y 2,.} .
Y _m,. . Connected to one signal line Y _m of Y _M, the source及Bido of the second N-channel thin film transistor
The other rain, provided next to the signal line _{Y m,} the signal lines _{Y 1, Y 2,.} . Y _m,. . One of YM
Connected to _one signal line Y _{m + 1} and the gate electrodes of the first N-channel thin film transistor and the first P-channel thin film transistor are connected in common to form signal lines X _1, X
_2,. . _Xn,. . Connected to one of the X _N, and connecting the gate electrode of the second P-channel type thin film transistor to the signal line Y _{m + 1,} the gate electrode of the second N-channel type thin film transistor to the signal line Y _m in the connected electro-optical device, periodically signals the arbitrary signal line Y _m is the signal line Y _{m + 1}
Signal is applied at a level opposite to that of the signal.
Is, while the signal is applied, the voltage on any of the signal lines X _n
A step of repeating a plurality of times to a state in which the applied, then, periodically signals to the signal line Y _m is the signal line Y
_{m + 1} is marked with a signal having a level opposite to that of the above signal.
And applying a voltage to the signal line _{Xn a} plurality of times while the signal is being applied .
And a gradation display.