JP3865252B2 - Electro-optic device - Google Patents

Description

The present invention relates to an electro-optical device including a protection circuit that is turned on when an excessive voltage is applied to a pixel wiring and has a function of removing the voltage. The reference invention relates to an image display method in a liquid crystal electro-optical device using a thin film transistor (hereinafter referred to as TFT) as a driving switching element, and particularly to a gradation display method for obtaining an intermediate color tone and light / dark expression. The reference invention particularly relates to a so-called perfect digital gradation display in which gradation display is performed without applying any analog signal to the active element from the outside.

  The liquid crystal composition has different dielectric constants in the horizontal and vertical directions with respect to the molecular axis due to its material properties, so it can be easily arranged horizontally or vertically with respect to external electrolysis. it can. The liquid crystal electro-optical device uses the anisotropy of the dielectric constant to control the amount of transmitted light or the amount of scattering, thereby performing ON / OFF, that is, bright / dark display. As the liquid crystal material, a material called TN (twisted nematic) liquid crystal, STN (super twisted nematic) liquid crystal, ferroelectric liquid crystal, polymer liquid crystal, or dispersion liquid crystal is known. It is known that a liquid crystal does not react to an external voltage in an infinitely short time but takes a certain time to respond. The value is specific to each liquid crystal material. In the case of TN liquid crystal, several tens of msec, in the case of STN liquid crystal, several hundred msec, in the case of ferroelectric liquid crystal, several tens of μsec, in the case of dispersion type or polymer liquid crystal. It is several tens of msec.

  Among electro-optical devices using liquid crystal, the one that can obtain the best image quality is one that uses an active matrix system. In a conventional active matrix type liquid crystal electro-optical device, a thin film transistor (TFT) is used as an active element, an amorphous or polycrystalline semiconductor is used for the TFT, and only one of P type and N type is used for one pixel. A type TFT was used. That is, generally, an N-channel TFT (referred to as NTFT) is connected to a pixel in series. Then, by applying a signal voltage to the signal lines of the matrix and applying a signal from both sides to the TFTs provided at the orthogonal positions of the respective signal lines, the TFTs are turned on. It was to control OFF individually. By controlling the pixels by such a method, a liquid crystal electro-optical device having a large contrast can be realized.

  However, with such an active matrix system, it has been extremely difficult to perform gradation display such as brightness and color tone. Conventionally, for gradation display, a method utilizing the fact that the light transmittance of liquid crystal changes depending on the magnitude of an applied voltage has been studied. For example, an appropriate voltage is supplied from the peripheral circuit between the source and drain of the TFT in the matrix, and a signal voltage is applied to the gate electrode in that state, thereby applying a voltage of that magnitude to the liquid crystal pixel. I was going to do it.

  However, in such a method, for example, due to inhomogeneity of TFT and inhomogeneity of matrix wiring, the voltage applied to the liquid crystal pixels actually differs by several% at least depending on each pixel. On the other hand, for example, the voltage dependence of the light transmittance of the liquid crystal is extremely non-linear, and the light transmittance changes abruptly at a specific voltage. It could be very different. For example, in the TN liquid crystal, the potential difference in the intermediate state between the ON / OFF states is about 1.2 V, and in order to achieve 16 gradations, it is necessary to control the potential difference with an accuracy of 75 mV. Therefore, in reality, it was the limit to achieve 16 gradations.

  Such difficulty in gradation display is extremely disadvantageous when the liquid crystal display device competes with a CRT (cathode ray tube) which is a conventional general display device.

The reference invention is intended to propose a completely new method for realizing a gradation display that has been difficult in the past.
An object of the present invention is to propose an electro-optical device including a protection circuit that is turned on when an excessive voltage is applied to a pixel wiring and has a function of removing the voltage.

As shown in FIG. 10, the protection circuit is provided between a peripheral driving circuit and a pixel, and means a circuit as shown in FIGS. In any case, when an excessive voltage is applied to the wiring of the pixel, it is turned on and has an action of removing the voltage. These protection circuits are configured using a doped or undoped semiconductor material such as silicon, a transparent conductive material such as ITO, or a normal wiring material. Therefore, it can be formed simultaneously with the formation of the pixel circuit.
The present invention includes a first substrate, a second substrate, the first substrate, and a liquid crystal sandwiched between the second substrates, wherein the first substrate includes a display unit, the display A protection circuit electrically connected to a portion, the second substrate is a glass substrate, a black stripe on the glass substrate, a red filter, a green filter and a blue filter on the black stripe, A leveling layer on the red filter, the green filter and the blue filter, and a common electrode on the leveling layer, and the protection circuit includes an N-type thin film transistor, a P-type thin film transistor, a first resistor , And an N-type thin film transistor having a second resistance and configured using a doped or undoped semiconductor material, a transparent conductive material, or a wiring material. One of the source and the drain of the star is electrically connected to the gate through the first resistor, and one of the source and the drain of the N-type thin film transistor is connected through the first resistor and the second resistor. One of the source and drain of the P-type thin film transistor and the gate are electrically connected via the first resistor, and the source and drain of the P-type thin film transistor. Is electrically connected to the display portion via the first resistor and the second resistor, and the other of the source and drain of the N-type thin film transistor and the other of the source and drain of the P-type thin film transistor Is electrically connected .
Now, by controlling the voltage applied to the liquid crystal in an analog manner, by its has been described above that the optical transparency can be controlled, for controlling the amount of time it depends in voltage to the liquid crystal, It was found that gradation can be obtained visually.

  For example, when a TN (twisted nematic) liquid crystal, which is a typical liquid crystal material, is used, for example, a rectangular pulse as indicated by A in FIG. When comparing the case of applying a rectangular pulse, it was found that A was brighter. Here, the pulse period was 1 msec. As a result, A was the brightest, and in the following order, B, C, D. This is completely unexpected. This is because the time of 1 msec is too short in the normal TN liquid crystal material described above, and the TN liquid crystal does not react in such a short time. Therefore, in any case, it should be impossible to realize the ON state of the liquid crystal. However, in practice, the liquid crystal was able to achieve an intermediate darkness.

The specific principle is still unknown in detail. However, it was found that by utilizing the phenomenon of this is possible gradation expression. That is, the characteristic of the reference invention is to realize intermediate brightness by digital control by controlling the pulse width when applying a pulse to the liquid crystal material at such a period that the liquid crystal material does not react. Is. Results of research, the pulse period of for obtaining such intermediate concentration was found to be in the case of a TN liquid crystal is required 10msec or less.

Here, the meaning of the phrase “pulse period” is clarified. That is, in this case, a plurality of pulses are continuously applied to the liquid crystal. In this case, the period of the pulse is the time between the start of one pulse and the start of the next pulse. That means. Therefore, it is the reciprocal of the pulse repetition frequency.
The pulse width refers to the time during which the pulse is in a voltage state. Therefore, in FIG. 1, for example, in the case of a C pulse train, T is the pulse period and τ is the pulse width.

  Similar effects were observed in STN liquid crystals, ferroelectric liquid crystals, polymer liquid crystals, and dispersed liquid crystals. In both cases, it was revealed that an intermediate color tone can be obtained by applying a pulse having a cycle shorter than the response time. That is, STN liquid crystal is 100 msec or less, preferably 10 msec or less, ferroelectric liquid crystal is 10 μsec or less, preferably 1 μsec or less, and polymer liquid crystal or dispersed liquid crystal is 10 msec or less. A gradation display was obtained by applying a pulse with a period of 1 msec or less.

  Usually, in the case of an image on a television or the like, 30 still images are successively drawn out per second to form a moving image. Therefore, the time for one still image to continue is about 30 msec. This time is too early for the human eye and is literally “not even the eye”, and as a result, it is impossible to visually identify each still image. In any case, in order to obtain a normal moving image, a single still image cannot be continued for 100 msec or longer.

For example, if 256 gradation display is performed using the reference invention , for example, if T = 3 msec, a pulse voltage applying method capable of dividing at least 256 this 3 msec time is applied to the pixel. It is necessary to adopt as a method to do. That is, it is necessary to build a circuit in which a pulse voltage of 3 msec / 256 = 11.7 μsec is applied to the pixel at the shortest. Actually, as shown in FIG. 3, the duty ratio τ / T of the pulse and the light transmittance of the liquid crystal pixel are in a non-linear relationship. In order to obtain 256 gradations, the duty ratio of the pulse is further increased. Fine control is necessary.

  In addition, when actual image display is performed, other pixels must be taken into consideration. In an actual image display device, for example, there are 400 rows. That is, as will be described later, the active element of the matrix is required to have an extremely short response of 100 nsec. An example of a circuit having such a short-time response is shown in FIG. 4 and will be described below.

FIG. 4 shows an example of an active matrix circuit of a liquid crystal display device necessary for carrying out the reference invention . In the reference invention , since the active element is required to respond in a short time of 100 nsec or less, it is necessary to build a circuit that operates at high speed. For this purpose, an inverter type circuit in which NTFT and PTFT are operated in a complementary manner as shown in FIG. 4 is used instead of switching only with NTFT or PTFT as in the prior art. is necessary.

  In this example, an example of an N × M matrix is shown, but only the vicinity of n rows and m columns is shown in order to avoid complexity. If the same thing is developed up, down, left and right, a complete one can be obtained.

FIG. 4 shows four inverter circuits. Each inverter circuit includes at least one NTFT and at least one PTFT. The number of TFTs may be further increased in case there is a defect. In this circuit, the gate electrodes of NTFT and PTFT are connected to a signal line _Xn , and one of the source or drain of NTFT and PTFT is connected to each other, which is connected to the electrodes of pixels Zn _{and m} . The other of the source or drain of the NTFT and PTFT, respectively, are connected to the signal line Y _m and _{Y m.} In the following, signal lines X _1, X _{2,. . XN} are collectively or individually referred to as X-rays, and signal lines Y1 _{, Y2,. .} Y _M is collectively or individually called a Y line. In the figure, a capacitor is artificially inserted in parallel with the capacitor of the pixel. The capacitor inserted at this time has a function of decelerating the speed at which the voltage of the pixel decreases due to natural discharge. Since the voltage drop of the pixel is determined by the variation of the pixel, particularly in the invention in which gradation display is performed with the voltage applied to the pixel being constant as in the reference invention , the image quality is reduced. It causes a decrease. However, by inserting a capacitor in parallel with the pixel in this way, a voltage drop due to pixel variation can be remarkably suppressed, and high image quality can be obtained.

  Next, an example of the operation of the circuit when such a circuit is used will be described with reference to FIGS. This matrix circuit needs to operate so as to apply a pulse voltage as shown in FIG. 1A to the liquid crystal cell. Accordingly, FIG. 1B shows an outline of signal voltages applied to the X-ray and the Y-line in order to generate such a pulse. As an example, consider a 400 × 640 matrix.

The signal applied to the X-ray is indicated by, for example, V (X _n ) in the case of the _Xn line, which is actually 256 pulses (hereinafter referred to as a group of pulses repeated in the period T). It is understood that each of the 256 subpulses is composed of a pulse train containing 400 elements. Here, the number 400 is the number of rows in the matrix. Therefore, the minimum unit of pulses applied to X-rays is 29 nsec if T = 3 msec.

On the other hand, on the Y line, during the time T / 256, pulses as indicated by V (Y ₁ ), V (Y _m ), V (Y _{m + 1} ), and V (Y ₄₀₀ ) in the figure are respectively displayed. Applied at different timings. This pulse needs to be shorter than the minimum unit pulse of the pulse applied to the X-ray. Eventually, during time T, 256 pulses are applied to each Y line. Further, the signal line Y _m and are diametrically opposed to the signal line Y _m, as shown in FIG. 1 (C), signals to complement signals applied to the signal line Y _m is applied. In the following description, each time, the signals Y _m is not necessary to description, it is assumed that (reversed phase) signal as to complement the signal of Y _m is added.

Next, the actual operation of the circuit will be described with reference to FIG. First, a first sub-pulse is applied to each X-ray. Of course, these sub-pulses are different for each X-ray. On the other hand, as described above, pulses are sequentially applied to the Y line in the order of Y ₁ and then Y ₂ . First, consider the case where pulse is applied to Y _1. At this time, the active elements connected to the pixels Z ₁ and ₁ are turned off. That is, since Y ₁ is in the voltage state (V _H ) and Y ₁ is not in the voltage state (V _L ), PTFT and NTFT are in a state of operating as inverters. Further since the input _{X 1} of the inverter is _{V H,} the output becomes _{V L} inverted. Next, a voltage is applied to Y _2. At this time, the pixels Z ₁ and ₂ are in a state where voltage is applied. That is, the input _{X 1} of the inverter is because a _{V L.} Thereafter, _{X 1} is keeping the _{V L, Y 2} is Y ₂ signal is inverted _{V H} to _{V L.} Then, PTFT and NTFT function not as an inverter but as a buffer. At this time, since X ₁ is V _L , this circuit does not operate, and thus the charge stored in the liquid crystal cell is retained. Thereafter, a signal of V _L or V _H is applied to X ₁ , but this circuit does not operate regardless of which signal is applied. Therefore, the electric charge stored in the liquid crystal cell continues to be retained. This state lasts at least until Y ₁ is then V _H and Y ₁ is V _L. Similarly, Z _{1, m,} Z _{1, m + 1,} and Z _1,400 are in a voltage state, and the state is maintained.

In this way, it pulses Yuki is applied in sequence, consider the case where it is applied to the Y _m. If we are now paying attention to the four pixels Z _{n, m} , Z _{n, m + 1} , Z _{n + 1, m} , Z _{n + 1, m + 1} , the m th and (m + 1) of the first sub-pulse of X _n and X _{n + 1} Pay attention to the second. Since both _Xn and _{Xn + 1} are the mth _VL , the pixels Zn _{, m} and Zn _{+ 1, m} are in the voltage (charge) state. A pulse is then applied to Y _{m + 1} . X _n be _{X n + 1} is also the (m + 1) th is because _{V L,} pixel _Z n _{Again, m + 1, Z n +} 1, m + 1 becomes charged.

Next, although omitted in the figure, it is assumed that the second sub-pulse has come. At this time, _if both _{Xn and Xn + 1} are m-th and (m + 1) -th _VL , the charged state is not lost, and the above four pixels continue to be in the voltage state. Thereafter, it is assumed that the voltage state of all four pixels continues until the (h−1) th sub-pulse.

Next, it is assumed that the sub-pulse has advanced and the h-th sub-pulse has come. In the figure, except m-th and (m + 1) -th are omitted to avoid complexity. At this time, since both _Xn and _{Xn + 1} are the mth _VL , the pixels Zn _{, m} and Zn _{+ 1, m} continue to be in the voltage state. _However, since the _{X n + 1} is the (m + 1) th is _{V H,} the pixel _{Z n + 1, m} although voltage state continues, pixel _{Z n + 1, m + 1,} the output of the active element is no longer voltage state, are stored The charge is released and the voltage state is interrupted.

Further, when the sub-pulses of the i has come, the _{X n} (m + 1) -th so becomes _{V H, Z n,} the state of charge of the _{m + 1} is canceled. Hereinafter, in the j-th and k-th sub-pulses, since the m-th of X _{n + 1} and X _n becomes V _{H ,} the charging states of the pixels Z _{n, m} and Z _{n + 1 and m} are respectively , Interrupted during the jth subpulse. Through this process, the voltage state time can be digitally controlled for each pixel as shown by V (Z) in FIG.

  By repeating such an operation, the width of the voltage pulse applied to each pixel can be arbitrarily controlled as shown in FIG.

As is clear from the above description, in carrying out the reference invention , the sub-pulses as described above do not have to be clearly pulsed. In order to simplify the explanation, the concept of sub-pulses has been introduced. In particular, it is obvious that the reference invention can be implemented even if the signal between the sub-pulses is not clear and the signal has almost no boundary. is there. Furthermore, in order to make the explanation easy to understand, the zero level and the voltage level of the signal have been clarified, but this is only a problem whether it is below or above the threshold voltage of the liquid crystal or TFT. It need not be zero. In addition, since the voltage is a relative physical quantity based on the potential at an arbitrary point, it is obvious that the pulse may have an opposite polarity in the above example. Furthermore, an appropriate offset voltage may be applied to the counter electrode of the pixel. Further, in the above example, although the screen were being scanned line by line in order, first _{Y 1, Y 3, Y 5} ,. _{. .} Scans and so, _{then, Y 2, Y 4, Y} 6 ,. _. It goes without saying that so-called interlaced scanning is also possible.

The protection circuit of the present invention is a circuit as shown in FIGS. 11 and 12, which is provided between a peripheral driving circuit and a pixel, as shown in FIG. In any case, when an excessive voltage is applied to the wiring of the pixel, it is turned on and has an action of removing the voltage. These protection circuits are configured using a doped or undoped semiconductor material such as silicon, a transparent conductive material such as ITO, or a normal wiring material. Therefore, it can be formed simultaneously with the formation of the pixel circuit.
The reference invention is characterized in that digital gradation display is performed in contrast to the conventional analog gradation display. As an effect, for example, when a liquid crystal electro-optical device having a pixel number of 640 × 400 dots is assumed, it is very difficult to produce the characteristics of all 256,000 TFTs without variation. In terms of mass productivity and yield, 16 gradation display is considered to be the limit, but as in the reference invention , gradation display is purely digitally controlled without adding any analog signal. By doing so, gradation display of 256 gradation display or more is possible. Since the display is a complete digital display, there is no ambiguity in gradation due to variations in TFT characteristics. Therefore, even with slight variations in TFT, extremely uniform gradation display is possible. Therefore, in the past, the yield was extremely poor in order to obtain TFTs with little variation, but the yield of TFTs was not so much a problem with the reference invention , so the yield of liquid crystal devices was improved and the manufacturing cost was remarkably suppressed. I was able to.

For example, when a normal analog gradation display is performed on a liquid crystal electro-optical device in which 256,000 TFTs of 640 × 400 dots are formed in a 300 mm square, there is about ± 10% variation in TFT characteristics. 16 gradation display was the limit. However, when the digital gradation display according to the reference invention is performed, it is difficult to be affected by variations in characteristics of the TFT elements, so that it is possible to display up to 256 gradations, and the color display has a wide variety of 16,777 and 216 colors. Display of various colors. When projecting software such as television images, for example, even the “rock” of the same color has a slightly different hue due to its fine depressions. When a display close to natural colors is to be displayed, difficulty is required with 16 gradations. The gradation display according to the reference invention makes it possible to add these minute color tone changes.

In the embodiments of the present invention, the description has been made with a focus on TFTs using silicon, but TFTs using germanium can be used as well. In particular, the electron mobility of the single crystal germanium 3600 cm ² / Vs, the Hall mobility and 1800 cm ² / Vs, the single crystal silicon value of (1350 cm ² / Vs in electron mobility, 480 cm ² / Vs in hole mobility) Since it exceeds the characteristics, it is an extremely excellent material for carrying out the reference invention that requires high-speed operation. Further, germanium has a lower transition temperature from an amorphous state to a crystalline state than silicon, and is suitable for a low temperature process. In addition, the nucleation rate during crystal growth is small, so that generally large crystals can be obtained when polycrystalline growth is performed. Thus, germanium has characteristics comparable to silicon.

  In order to explain the technical idea of the present invention, an electro-optical device using liquid crystal, particularly a display device, has been described as an example, but in order to apply the idea of the present invention, it is necessary to be a display device. It may be a so-called projection television, other optical switch, or optical shutter. Furthermore, the electro-optic material is not limited to liquid crystal, and it will be apparent that the present invention can be applied to any material whose optical characteristics change due to electric influences such as electric field and voltage.

  In this embodiment, a wall-mounted television is manufactured using a liquid crystal display device having a circuit configuration as shown in FIG. The TFT at that time was polycrystalline silicon using laser annealing.

  An arrangement configuration of actual electrodes and the like corresponding to this circuit configuration is shown in FIG. 5 for one pixel. First, a method for manufacturing a liquid crystal panel used in this embodiment will be described with reference to FIGS. In FIG. 6A, a silicon oxide film as a blocking layer 51 is formed on a glass 50 such as quartz glass that can withstand heat treatment at an inexpensive temperature of 700 ° C. or less, for example, about 600 ° C., using a magnetron RF (radio frequency) sputtering method. Fabricate to a thickness of ~ 300 nm. The process conditions were an oxygen 100% atmosphere, a film forming temperature of 150 ° C., an output of 400 to 800 W, and a pressure of 0.5 Pa. The deposition rate using quartz or single crystal silicon as the target was 3 to 10 nm / min.

A silicon film 52 was formed on the silicon film by plasma CVD. The film forming temperature was 250 ° C. to 350 ° C. and 320 ° C. in this example, and monosilane (SiH ₄ ) was used. Not only monosilane (SiH ₄ ) but also disilane (Si ₂ H ₆ ) or trisilane (Si ₃ H ₈ ) may be used. These were introduced into a PCVD apparatus at a pressure of 3 Pa, and a high frequency power of 13.56 MHz was applied to form a film. At this time, 0.02-0.10 W / cm ² is appropriate for the high-frequency power, and 0.055 W / cm ² was used in this example. The flow rate of monosilane (SiH ₄ ) was 20 SCCM, and the film formation rate at that time was about 12 nm / min. In order to control the threshold voltage (Vth) of PTFT and NTFT to be approximately the same, boron may be added during film formation at a concentration of 1 × 10 ¹⁵ to 1 × 10 ¹⁸ cm ⁻³ using diborane. . Further, not only this plasma CVD but also sputtering or low pressure CVD may be used for forming a silicon layer which becomes a channel region of the TFT, and the method will be briefly described below.

When the sputtering method was used, the back pressure before sputtering was set to 1 × 10 ⁻⁵ Pa or less, single crystal silicon was used as a target, and the atmosphere was mixed with 20 to 80% of hydrogen in argon. For example, 20% argon and 80% hydrogen. The film forming temperature was 150 ° C., the frequency was 13.56 MHz, the sputtering output was 400 to 800 W, and the pressure was 0.5 Pa.

When forming by a low pressure vapor phase method, disilane (Si ₂ H ₆ ) or trisilane (Si ₃ H ₈ ) is supplied to a CVD apparatus at 450 to 550 ° C., for example, 530 ° C., which is 100 to 200 ° C. lower than the crystallization temperature. A film was formed. The pressure in the reactor was 30 to 300 Pa. The film formation rate was 5 to 25 nm / min. In order to control the threshold voltage (Vth) of PTFT and NTFT to be approximately the same, boron may be added during film formation at a concentration of 1 × 10 ¹⁵ to 1 × 10 ¹⁸ cm ⁻³ using diborane. .

The film formed by these methods preferably has oxygen of 5 × 10 ²¹ cm ⁻³ or less. In order to promote crystallization, it is desirable that the oxygen concentration be 7 × 10 ¹⁹ cm ⁻³ or less, preferably 1 × 10 ¹⁹ cm ⁻³ or less. This concentration was selected because the current increases. If this oxygen concentration is high, crystallization is difficult and the laser annealing temperature must be increased or the laser annealing time must be increased. Hydrogen was 4 × 10 ²⁰ cm ⁻³ , which was 1 atomic% as compared with silicon 4 × 10 ²² cm ⁻³ .

Further, in order to further promote crystallization with respect to the source and the drain, the oxygen concentration is set to 7 × 10 ¹⁹ cm ⁻³ or less, preferably 1 × 10 ¹⁹ cm ⁻³ or less, and the channel forming region of the TFT constituting the pixel Oxygen may be added only to 5 × 10 ^{20 to} 5 × 10 ²¹ cm ⁻³ by ion implantation. By the above method, an amorphous silicon film was formed to a thickness of 50 to 500 nm, in this embodiment, 100 nm.

Thereafter, a pattern in which only the source / drain regions were opened using the photoresist 53 using the mask P1 was formed. A silicon film 54 to be an n-type active layer was formed thereon by plasma CVD. The film forming temperature was 250 ° C. to 350 ° C., and in this example, 320 ° C., and monosilane (SiH ₄ ) and monosilane-based phosphine (PH ₃ ) 3% concentration were used. These were introduced into the PCVD apparatus at a pressure of 5 Pa, and a high frequency power of 13.56 MHz was applied to form a film. At this time, the high-frequency power is suitably 0.05~0.20W / cm ^2, in this embodiment using 0.120W / cm ^2.

The specific conductivity of the n-type silicon layer completed by this method was about 2 × 10 ⁻¹ [Ωcm ⁻¹ ]. The film thickness was 5 nm. In this way, FIG. 6 (A) was obtained. Thereafter, using a lift-off method, the resist 53 was removed, and source / drain regions 55 and 56 were formed.

A p-type active layer was formed using the same process. The introduction gas used here was monosilane (SiH ₄ ) and monosilane-based diborane (B ₂ H ₆ ) having a concentration of 5%. These were introduced into a PCVD apparatus at a pressure of 4 Pa, and a high frequency power of 13.56 MHz was applied to form a film. At this time, the high-frequency power is suitably 0.05~0.20W / cm ^2, in this embodiment using 0.120W / cm ^2. The specific conductivity of the p-type silicon layer completed by this method was about 5 × 10 ⁻² [Ωcm ⁻¹ ]. The film thickness was 5 nm. Thus, FIG. 6B was obtained. Thereafter, source / drain regions 59 and 60 were formed by using a lift-off method in the same manner as the N-type region. Thereafter, the silicon film 52 was removed by etching using the mask P3 to form an N-channel thin film transistor island region 63 and a P-channel thin film transistor island region 64.

Thereafter, as shown in FIG. 6C, the source / drain / channel regions were laser-annealed using a XeCl excimer laser, and at the same time, the active layer was laser-doped. The laser energy at this time has a threshold energy of 130 mJ / cm ² , and 220 mJ / cm ² is required to melt the entire film thickness. However, when energy of 220 mJ / cm ² or more is irradiated from the beginning, hydrogen contained in the film is suddenly released, so that the film is destroyed. For this reason, it is necessary to melt after first expelling hydrogen with low energy. After performing the flush hydrogen in the first 150 mJ / cm ² in the present embodiment was subjected to crystallization at 230 mJ / cm ^2.

  A silicon oxide film was formed thereon as a gate insulating film to a thickness of 50 to 200 nm, for example 100 nm. This was performed under the same conditions as the production of the silicon oxide film as the blocking layer. During the film formation, a small amount of fluorine may be added to fix sodium ions.

Thereafter, a silicon film having a phosphorus concentration of 1 to 5 × 10 ²¹ cm ^{−3 on} the upper side or a multilayer of this silicon film and molybdenum (Mo), tungsten (W), MoSi ₂ or WSi ₂ thereon. A film was formed. This was patterned with a fourth photomask P4 to obtain FIG. 6D. A gate electrode 66 for NTFT and a gate electrode 67 for PTFT were formed. For example, the channel length was 7 μm, the gate electrode was formed with a thickness of 0.2 μm of phosphorus-silicon, and molybdenum was formed thereon with a thickness of 0.3 μm. At the same time, as shown in FIG. 7D ′, the gate wiring 65 and the wiring 68 arranged in parallel therewith were also patterned.

In addition to the above materials, for example, aluminum (Al) can also be used as the gate electrode material. When aluminum is used, after patterning with a fourth photomask P4, the surface is anodized so that the self-line method can be applied. Therefore, the source / drain contact holes are closer to the gate. Since it can be formed at a position, the TFT characteristics can be further improved from the reduction of mobility and threshold voltage.

In this way, a C / TFT can be produced without applying temperature in all steps to 400 ° C. or higher. Therefore, it is not necessary to use an expensive substrate such as quartz as the substrate material, and it can be said that the process is extremely suitable for a large- screen liquid crystal display device.

  In FIG. 6E, an interlayer insulator 69 is formed as a silicon oxide film by the sputtering method described above. The silicon oxide film may be formed by LPCVD, photo CVD, or atmospheric pressure CVD. For example, the electrode window 79 is formed to a thickness of 0.2 to 0.6 μm, and then the electrode window 79 is formed using the fifth photomask P5. Thereafter, aluminum was formed on the whole by sputtering to a thickness of 0.3 μm, and leads 74 and contacts 73 and 75 were produced using a sixth photomask P6. In this way, FIG. 6E and FIG. 7E 'were obtained. After that, the surface was coated and formed with an organic resin 77 for planarization, for example, a light-transmitting polyimide resin, and electrode drilling was performed again with the seventh photomask P7. Further, ITO (indium tin oxide) was formed to a thickness of 0.1 μm on all of these by sputtering, and a pixel electrode 71 was formed using an eighth photomask P8. This ITO was formed at room temperature to 150 ° C., and was achieved by oxygen at 200 to 400 ° C. or annealing in the atmosphere. In this way, FIG. 6F and FIG. 7F 'were obtained. A cross-sectional view taken along line A-A ′ of FIG. 7F ′ is illustrated in FIG. Actually, a counter electrode is provided on the liquid crystal material, and a capacitance is generated between the counter electrode and the electrode 71 as shown in the figure. At the same time, a capacitance is generated between the wiring 68 and the electrode 71. Then, by maintaining the wiring 68 at the same potential as the counter electrode, a circuit in which a capacitor is inserted in parallel with the liquid crystal pixel is formed as shown in FIG. Particularly, the wiring 68 is parallel to the gate wiring 65 by arranging as in this embodiment, so that the parasitic capacitance between the two wirings is small, and therefore, there is an effect of reducing the attenuation and delay of the signal propagating through the gate wiring. .

  Further, when the wiring 68 formed in this way is used while being grounded, it can be used as a grounding line for a protection circuit provided at the end of each matrix. As shown in FIG. 10, the protection circuit is provided between a peripheral driving circuit and a pixel, and means a circuit as shown in FIGS. In any case, when an excessive voltage is applied to the wiring of the pixel, it is turned on and has an action of removing the voltage. These protection circuits are configured using a doped or undoped semiconductor material such as silicon, a transparent conductive material such as ITO, or a normal wiring material. Therefore, it can be formed simultaneously with the formation of the pixel circuit.

  This will be apparent from, for example, that each protection circuit in FIG. 11 is composed of NTFT, PTFT, or a C / TFT combining them. In the protection circuit of FIG. 12, TFTs are not used, but the diodes are configured by, for example, PIN junctions, and diodes that place particular emphasis on zener characteristics have a structure such as NIN, PIP, or NPN, PNP. Needless to say, it is obvious that it can be manufactured by using the manufacturing method shown in this embodiment.

The electrical characteristics of the TFT obtained as described above are PTFT, the mobility is 40 (cm ² / Vs), Vth is −5.9 (V), and the NTFT is 80 (cm ^2). / Vs) and Vth were 5.0 (V).

One substrate for a liquid crystal electro-optical device manufactured according to the above method could be obtained. FIG. 5 shows the arrangement of electrodes and the like of this liquid crystal display device. During TFT constituting the inverter according to the reference invention of the signal lines _{Y 1} and Y _1, and between _{Y 2} and Y _2, are provided in parallel to the signal lines _X 1, _{X 2.} By repeating such a matrix configuration left and right and up and down, a liquid crystal display device with large pixels of 640 × 480 and 1280 × 960 can be obtained. In this embodiment, it is 1920 × 400. In this way, a first substrate was obtained.

  A method for manufacturing the other substrate is shown in FIGS. A polyimide resin in which a black pigment is mixed with polyimide was formed on a glass substrate to a thickness of 1 μm by using a spin coating method, and a black stripe 81 was formed using a ninth photomask P9. Thereafter, a polyimide resin mixed with a red pigment was formed into a thickness of 1 μm by using a spin coating method, and a red filter 83 was manufactured using a tenth photomask P10. Similarly, the green filter 85 and the blue filter 86 were produced using the masks P11 and P12. During the production, each filter was baked in nitrogen at 350 ° C. for 60 minutes. Thereafter, the leveling layer 89 was formed using transparent polyimide, also using the spin coating method.

  Thereafter, ITO (indium tin oxide) was formed to a thickness of 0.1 μm on all of them by a sputtering method, and a common electrode 90 was formed using a tenth photomask P10. This ITO was formed into a film at room temperature to 150 ° C., and was achieved by oxygen at 200 to 300 ° C. or annealing in the atmosphere to obtain a second substrate.

  A polyimide precursor was printed on the substrate using an offset method, and baked at 350 ° C. for 1 hour in a non-oxidizing atmosphere such as nitrogen. Thereafter, a known rubbing method was used to modify the polyimide surface, and at least initially, means for aligning liquid crystal molecules in a certain direction was provided.

  Thereafter, the nematic liquid crystal composition was sandwiched between the first substrate and the second substrate, and the periphery was fixed with an epoxy adhesive. A TAB-shaped drive IC and a PCB having a common signal and potential wiring were connected to leads on the substrate, and a polarizing plate was attached to the outside to obtain a transmissive liquid crystal electro-optical device. This was connected to a rear illuminator with three cold-cathode tubes and a tuner for receiving TV radio waves to complete a wall-mounted TV. Compared to a conventional CRT television, it is a flat device, so it can be installed on a wall or the like. The operation of this liquid crystal television was confirmed by applying a signal substantially equivalent to that shown in FIGS. 1 and 2 to the liquid crystal pixels.

Reference example

In the reference example , a wall-mounted television is manufactured using a liquid crystal display device having a circuit configuration as shown in FIG. The TFT at that time was polycrystalline silicon using laser annealing.

  Hereinafter, a method for manufacturing the TFT portion will be described with reference to FIG. In FIG. 9A, a silicon oxide film 100 as a blocking layer 101 is formed on a glass 100 such as quartz glass that can withstand heat treatment at an inexpensive temperature of 700 ° C. or less, for example, about 600 ° C., using a magnetron RF (radio frequency) sputtering method. Fabricate to a thickness of ~ 300 nm. The process conditions were an oxygen 100% atmosphere, a film forming temperature of 15 ° C., an output of 400 to 800 W, and a pressure of 0.5 Pa. The deposition rate using quartz or single crystal silicon as the target was 3 to 10 nm / min.

A silicon film 102 was formed on the silicon film by plasma CVD. The film forming temperature was 250 ° C. to 350 ° C., 320 ° C. in this reference example , and monosilane (SiH ₄ ) was used. Not only monosilane (SiH ₄ ) but also disilane (Si ₂ H ₆ ) or trisilane (Si ₃ H ₈ ) may be used. These were introduced into a PCVD apparatus at a pressure of 3 Pa, and a high frequency power of 13.56 MHz was applied to form a film. At this time, 0.02-0.10 W / cm ² is appropriate for the high-frequency power, and 0.055 W / cm ² was used in this reference example . The flow rate of monosilane (SiH ₄ ) was 20 SCCM, and the film formation rate at that time was about 12 nm / min. In order to control the threshold voltage (Vth) of PTFT and NTFT to be approximately the same, boron may be added during film formation at a concentration of 1 × 10 ¹⁵ to 1 × 10 ¹⁸ cm ⁻³ using diborane. . Further, not only this plasma CVD but also sputtering or low pressure CVD may be used for forming a silicon layer which becomes a channel region of the TFT, and the method will be briefly described below.

When the sputtering method was used, the back pressure before sputtering was set to 1 × 10 ⁻⁵ Pa or less, single crystal silicon was used as a target, and the atmosphere was mixed with 20 to 80% of hydrogen in argon. For example, 20% argon and 80% hydrogen. The film forming temperature was 150 ° C., the frequency was 13.56 MHz, the sputtering output was 400 to 800 W, and the pressure was 0.5 Pa.

When forming by a low pressure vapor phase method, disilane (Si ₂ H ₆ ) or trisilane (Si ₃ H ₈ ) is supplied to a CVD apparatus at 450 to 550 ° C., for example, 530 ° C., which is 100 to 200 ° C. lower than the crystallization temperature. A film was formed. The pressure in the reactor was 30 to 300 Pa. The film formation rate was 5 to 25 nm / min. In order to control the threshold voltage (Vth) of PTFT and NTFT to be approximately the same, boron may be added during film formation at a concentration of 1 × 10 ¹⁵ to 1 × 10 ¹⁸ cm ⁻³ using diborane. .

The film formed by these methods preferably has oxygen of 5 × 10 ²¹ cm ⁻³ or less. In order to promote crystallization, it is desirable that the oxygen concentration be 7 × 10 ¹⁹ cm ⁻³ or less, preferably 1 × 10 ¹⁹ cm ⁻³ or less. This concentration was selected because the current increases. If this oxygen concentration is high, crystallization is difficult and the laser annealing temperature must be increased or the laser annealing time must be increased. Hydrogen was 4 × 10 ²⁰ cm ⁻³ , which was 1 atomic% as compared with silicon 4 × 10 ²² cm ⁻³ .

Further, in order to further promote crystallization with respect to the source and the drain, the oxygen concentration is set to 7 × 10 ¹⁹ cm ⁻³ or less, preferably 1 × 10 ¹⁹ cm ⁻³ or less, and the channel forming region of the TFT constituting the pixel Oxygen may be added only to 5 × 10 ^{20 to} 5 × 10 ²¹ cm ⁻³ by ion implantation. By the above method, an amorphous silicon film was formed to a thickness of 50 to 500 nm, in this reference example , 100 nm.

Thereafter, a pattern was formed in which the photoresist 103 was opened only in the regions to be the source / drain regions of the NTFT using the mask P1. Then, by using the resist 103 as a mask, phosphorus ions are implanted by 2 × 10 ^{14 to} 5 × 10 ¹⁶ cm ⁻² , preferably 2 × 10 ¹⁶ cm ⁻² by ion implantation to form the n-type impurity region 104. . Thereafter, the resist 103 was removed.

Similarly, a resist 105 was applied, and a pattern was formed in which only the regions to be the source / drain regions of the PTFT were opened using the mask P2. Then, a p-type impurity region 106 was formed using the resist 105 as a mask. As the impurity, boron was used, and the impurity was introduced by 2 × 10 ^{14 to} 5 × 10 ¹⁶ cm ⁻² , preferably 2 × 10 ¹⁶ cm ⁻² , also using the ion implantation method. In this way , FIG. 9B was obtained.

Thereafter, a silicon oxide film 107 having a thickness of 50 to 300 nm, for example, 100 nm was formed on the silicon film 102 by the above-described RF sputtering method. Then, using a XeCl excimer laser, the source / drain / channel regions were crystallized and activated by laser annealing. The laser energy at this time has a threshold energy of 130 mJ / cm ² , and 220 mJ / cm ² is required to melt the entire film thickness. However, when energy of 220 mJ / cm ² or more is irradiated from the beginning, hydrogen contained in the film is suddenly released, so that the film is destroyed. For this reason, it is necessary to melt after first expelling hydrogen with low energy. After performing the flush hydrogen in the first 150 mJ / cm ² In the present Example, it was subjected to crystallization at 230 mJ / cm ^2. Further, the silicon oxide film 107 was removed after the laser annealing.

  Thereafter, island-shaped NTFT regions 111 and PTFT regions 112 were formed using a photomask P3. On this, a silicon oxide film 108 was formed as a gate insulating film to a thickness of 50 to 200 nm, for example, 100 nm. This was performed under the same conditions as the production of the silicon oxide film as the blocking layer. During the film formation, a small amount of fluorine may be added to fix sodium ions.

Thereafter, a silicon film having a phosphorus concentration of 1 to 5 × 10 ²¹ cm ^{−3 on} the upper side or a multilayer of this silicon film and molybdenum (Mo), tungsten (W), MoSi ₂ or WSi ₂ thereon. A film was formed. This was patterned with a fourth photomask P4 to obtain FIG. 9D. A gate electrode 109 for NTFT and a gate electrode 110 for PTFT were formed. For example, the channel length was 7 μm, the gate electrode was formed with a thickness of 0.2 μm of phosphorus-silicon, and molybdenum was formed thereon with a thickness of 0.3 μm. Although not shown in the drawing, a gate wiring and a wiring parallel thereto are formed as in the case of the first embodiment.

  As a material for this wiring, for example, aluminum (Al) can be used in addition to the above materials. When aluminum is used, after patterning with a fourth photomask P4, the surface is anodized so that the self-line method can be applied. Therefore, the source / drain contact holes are closer to the gate. Since it can be formed at a position, the TFT characteristics can be further improved from the reduction of mobility and threshold voltage.

In this way, a C / TFT can be produced without applying temperature in all steps to 400 ° C. or higher. Therefore, it is not necessary to use an expensive substrate such as quartz as the substrate material, and it can be said that the process is extremely suitable for a large- screen liquid crystal display device.

  In FIG. 9E, the interlayer insulator 113 is formed as a silicon oxide film by the sputtering method described above. The silicon oxide film may be formed by LPCVD, photo CVD, or atmospheric pressure CVD. For example, the electrode window 117 is formed to a thickness of 0.2 to 0.6 μm, and then the electrode window 117 is formed using the fifth photomask P5. Thereafter, aluminum is formed to a thickness of 0.3 μm on all of these by sputtering and the lead 116 and the contacts 114 and 115 are formed using the sixth photomask P6, and then the surface is made of an organic resin for flattening. 119, for example, a translucent polyimide resin was applied and formed, and electrode drilling was performed again with the seventh photomask P7. Further, ITO (indium tin oxide) was formed to a thickness of 0.1 μm on all of these by sputtering, and a pixel electrode 118 was formed using an eighth photomask P8. This ITO was formed at room temperature to 150 ° C., and was achieved by oxygen at 200 to 400 ° C. or annealing in the atmosphere.

The TFT obtained has PTFT mobility of 35 (cm ² / Vs), Vth of −5.9 (V), NTFT mobility of 90 (cm ² / Vs), and Vth of 4 .8 (V).

  One substrate for a liquid crystal electro-optical device manufactured according to the above method could be obtained. The other substrate manufacturing method is the same as that of the first embodiment, and is therefore omitted. Thereafter, the nematic liquid crystal composition was sandwiched between the first substrate and the second substrate, and the periphery was fixed with an epoxy adhesive. A TAB-shaped drive IC and a PCB having a common signal and potential wiring were connected to leads on the substrate, and a polarizing plate was attached to the outside to obtain a transmissive liquid crystal electro-optical device. This was connected to a rear illuminator with three cold-cathode tubes and a tuner for receiving TV radio waves to complete a wall-mounted TV. Compared to a conventional CRT television, it is a flat device, so it can be installed on a wall or the like. The operation of this liquid crystal television was confirmed by applying a signal substantially equivalent to that shown in FIGS. 1 and 2 to the liquid crystal pixels.

An example of a drive motion waveform. An example of a drive motion waveform. An example of a gradation display characteristics of the LCD. Shows an example of Ma Torikusu configuration. Shows a planar structure of element. Shows the process of T FT. Shows the process of T FT. It shows the color filter of the process. Shows the process of T FT. It shows a connection example of a protection circuit. Shows an example of the protection circuit. Shows an example of the protection circuit.

Claims (14)

A first substrate; a second substrate; a liquid crystal sandwiched between the first substrate and the second substrate;
The first substrate has a display unit and a protection circuit electrically connected to the display unit,
The second substrate includes a glass substrate, a black stripe on the glass substrate, a red filter, a green filter and a blue filter on the black stripe, and a leveling layer on the red filter, the green filter and the blue filter. And a common electrode on the leveling layer,
The protection circuit includes an N-type thin film transistor, a P-type thin film transistor, a first resistor, and a second resistor, and is a semiconductor material that is doped or undoped, a transparent conductive material, or a wiring material Configured with
One of the source and drain of the N-type thin film transistor and the gate are electrically connected via the first resistor, and one of the source and drain of the N-type thin film transistor is connected to the first resistor and the second resistor. Electrically connected to the display unit via a resistor ;
One of the source and drain of the P-type thin film transistor is electrically connected to the gate through the first resistor, and one of the source and drain of the P-type thin film transistor is connected to the first resistor and the second resistor. Electrically connected to the display unit via a resistor;
The other of the source and drain of the N-type thin film transistor and the other of the source and drain of the P-type thin film transistor are electrically connected . A first substrate; a second substrate; a liquid crystal sandwiched between the first substrate and the second substrate;
The first substrate has a display unit and a protection circuit electrically connected to the display unit,
The second substrate includes a glass substrate, a film containing a patterned black pigment on the glass substrate, a red filter, a green filter and a blue filter, and the red filter, the green filter and the blue color on the film. A leveling layer on the filter, and a common electrode on the leveling layer,
The protection circuit includes an N-type thin film transistor, a P-type thin film transistor, a first resistor, and a second resistor, and is a semiconductor material that is doped or undoped, a transparent conductive material, or a wiring material Configured with
One of the source and drain of the N-type thin film transistor and the gate are electrically connected via the first resistor, and one of the source and drain of the N-type thin film transistor is connected to the first resistor and the second resistor. Electrically connected to the display unit via a resistor ;
One of the source and drain of the P-type thin film transistor is electrically connected to the gate through the first resistor, and one of the source and drain of the P-type thin film transistor is connected to the first resistor and the second resistor. Electrically connected to the display unit via a resistor;
The other of the source and drain of the N-type thin film transistor and the other of the source and drain of the P-type thin film transistor are electrically connected . A first substrate; a second substrate; a liquid crystal sandwiched between the first substrate and the second substrate;
The first substrate has a display unit and a protection circuit electrically connected to the display unit,
The second substrate includes a glass substrate, a polyimide film including a patterned black pigment on the glass substrate, a red filter, a green filter and a blue filter on the polyimide film, the red filter, the green filter, and Having a leveling layer on the blue filter and a common electrode on the leveling layer;
The protection circuit includes an N-type thin film transistor, a P-type thin film transistor, a first resistor, and a second resistor, and is a semiconductor material that is doped or undoped, a transparent conductive material, or a wiring material Configured with
One of the source and drain of the N-type thin film transistor and the gate are electrically connected via the first resistor, and one of the source and drain of the N-type thin film transistor is connected to the first resistor and the second resistor. Electrically connected to the display unit via a resistor ;
One of the source and drain of the P-type thin film transistor is electrically connected to the gate through the first resistor, and one of the source and drain of the P-type thin film transistor is connected to the first resistor and the second resistor. Electrically connected to the display unit via a resistor;
The other of the source and drain of the N-type thin film transistor and the other of the source and drain of the P-type thin film transistor are electrically connected . A first substrate; a second substrate; a liquid crystal sandwiched between the first substrate and the second substrate;
The first substrate has a display unit and a protection circuit electrically connected to the display unit,
The second substrate includes a glass substrate, a black stripe on the glass substrate, a red filter, a green filter and a blue filter on the black stripe, and a leveling layer on the red filter, the green filter and the blue filter. And a common electrode on the leveling layer,
The red filter, the green filter and the blue filter do not overlap each other,
The protective circuit includes an N-type thin film transistor, a P-type thin film transistor, a first resistor, and a second resistor, and is a semiconductor material that is doped or undoped, a transparent conductive material, or a wiring material Configured with
One of the source and drain of the N-type thin film transistor and the gate are electrically connected via the first resistor, and one of the source and drain of the N-type thin film transistor is connected to the first resistor and the second resistor. Electrically connected to the display unit via a resistor ;
One of the source and drain of the P-type thin film transistor is electrically connected to the gate through the first resistor, and one of the source and drain of the P-type thin film transistor is connected to the first resistor and the second resistor. Electrically connected to the display unit via a resistor;
The other of the source and drain of the N-type thin film transistor and the other of the source and drain of the P-type thin film transistor are electrically connected . A first substrate; a second substrate; a liquid crystal sandwiched between the first substrate and the second substrate;
The first substrate has a display unit and a protection circuit electrically connected to the display unit,
The second substrate includes a glass substrate, a film containing a patterned black pigment on the glass substrate, a red filter, a green filter and a blue filter, and the red filter, the green filter and the blue color on the film. A leveling layer on the filter, and a common electrode on the leveling layer,
The red filter, the green filter and the blue filter do not overlap each other,
The protection circuit includes an N-type thin film transistor, a P-type thin film transistor, a first resistor, and a second resistor, and is a semiconductor material that is doped or undoped, a transparent conductive material, or a wiring material Configured with
One of the source and drain of the N-type thin film transistor and the gate are electrically connected via the first resistor, and one of the source and drain of the N-type thin film transistor is connected to the first resistor and the second resistor. Electrically connected to the display unit via a resistor ;
One of the source and drain of the P-type thin film transistor is electrically connected to the gate through the first resistor, and one of the source and drain of the P-type thin film transistor is connected to the first resistor and the second resistor. Electrically connected to the display unit via a resistor;
The other of the source and drain of the N-type thin film transistor and the other of the source and drain of the P-type thin film transistor are electrically connected . A first substrate; a second substrate; a liquid crystal sandwiched between the first substrate and the second substrate;
The first substrate has a display unit and a protection circuit electrically connected to the display unit,
The second substrate includes a glass substrate, a polyimide film including a patterned black pigment on the glass substrate, a red filter, a green filter and a blue filter on the polyimide film, the red filter, the green filter, and Having a leveling layer on the blue filter and a common electrode on the leveling layer;
The red filter, the green filter and the blue filter do not overlap each other,
The protection circuit includes an N-type thin film transistor, a P-type thin film transistor, a first resistor, and a second resistor, and is a semiconductor material that is doped or undoped, a transparent conductive material, or a wiring material Configured with
One of the source and drain of the N-type thin film transistor and the gate are electrically connected via the first resistor, and one of the source and drain of the N-type thin film transistor is connected to the first resistor and the second resistor. Electrically connected to the display unit via a resistor ;
One of the source and drain of the P-type thin film transistor is electrically connected to the gate through the first resistor, and one of the source and drain of the P-type thin film transistor is connected to the first resistor and the second resistor. Electrically connected to the display unit via a resistor;
The other of the source and drain of the N-type thin film transistor and the other of the source and drain of the P-type thin film transistor are electrically connected . A first substrate; a second substrate; a liquid crystal sandwiched between the first substrate and the second substrate;
The first substrate has a display unit and a protection circuit electrically connected to the display unit,
The second substrate includes a glass substrate, a black stripe on the glass substrate, a red filter, a green filter and a blue filter on the black stripe, and a polyimide film on the red filter, the green filter and the blue filter. And a common electrode on the leveling layer,
The protection circuit includes an N-type thin film transistor, a P-type thin film transistor, a first resistor, and a second resistor, and is a semiconductor material that is doped or undoped, a transparent conductive material, or a wiring material Configured with
One of the source and drain of the N-type thin film transistor and the gate are electrically connected via the first resistor, and one of the source and drain of the N-type thin film transistor is connected to the first resistor and the second resistor. Electrically connected to the display unit via a resistor ;
One of the source and drain of the P-type thin film transistor is electrically connected to the gate through the first resistor, and one of the source and drain of the P-type thin film transistor is connected to the first resistor and the second resistor. Electrically connected to the display unit via a resistor;
The other of the source and drain of the N-type thin film transistor and the other of the source and drain of the P-type thin film transistor are electrically connected . A first substrate; a second substrate; a liquid crystal sandwiched between the first substrate and the second substrate;
The first substrate has a display unit and a protection circuit electrically connected to the display unit,
The second substrate includes a glass substrate, a film containing a patterned black pigment on the glass substrate, a red filter, a green filter and a blue filter, and the red filter, the green filter and the blue color on the film. A leveling layer made of a polyimide film on the filter, and a common electrode on the leveling layer,
The protection circuit includes an N-type thin film transistor, a P-type thin film transistor, a first resistor, and a second resistor, and is a semiconductor material that is doped or undoped, a transparent conductive material, or a wiring material Configured with
One of the source and drain of the N-type thin film transistor and the gate are electrically connected via the first resistor, and one of the source and drain of the N-type thin film transistor is connected to the first resistor and the second resistor. Electrically connected to the display unit via a resistor ;
One of the source and drain of the P-type thin film transistor is electrically connected to the gate through the first resistor, and one of the source and drain of the P-type thin film transistor is connected to the first resistor and the second resistor. Electrically connected to the display unit via a resistor;
The other of the source and drain of the N-type thin film transistor and the other of the source and drain of the P-type thin film transistor are electrically connected . A first substrate; a second substrate; a liquid crystal sandwiched between the first substrate and the second substrate;
The first substrate has a display unit and a protection circuit electrically connected to the display unit,
The second substrate includes a glass substrate, a polyimide film including a patterned black pigment on the glass substrate, a red filter, a green filter and a blue filter on the polyimide film, the red filter, the green filter, and A leveling layer made of a polyimide film on the blue filter, and a common electrode on the leveling layer,
The protection circuit includes an N-type thin film transistor, a P-type thin film transistor, a first resistor, and a second resistor, and is a semiconductor material that is doped or undoped, a transparent conductive material, or a wiring material Configured with
One of the source and drain of the N-type thin film transistor and the gate are electrically connected via the first resistor, and one of the source and drain of the N-type thin film transistor is connected to the first resistor and the second resistor. Electrically connected to the display unit via a resistor ;
One of the source and drain of the P-type thin film transistor is electrically connected to the gate through the first resistor, and one of the source and drain of the P-type thin film transistor is connected to the first resistor and the second resistor. Electrically connected to the display unit via a resistor;
The other of the source and drain of the N-type thin film transistor and the other of the source and drain of the P-type thin film transistor are electrically connected . A first substrate; a second substrate; a liquid crystal sandwiched between the first substrate and the second substrate;
The first substrate has a display unit and a protection circuit electrically connected to the display unit,
The second substrate includes a glass substrate, a black stripe on the glass substrate, a red filter, a green filter and a blue filter on the black stripe, and a polyimide film on the red filter, the green filter and the blue filter. And a common electrode on the leveling layer,
The red filter, the green filter and the blue filter do not overlap each other,
The protection circuit includes an N-type thin film transistor, a P-type thin film transistor, a first resistor, and a second resistor, and is a semiconductor material that is doped or undoped, a transparent conductive material, or a wiring material Configured with
One of the source and drain of the N-type thin film transistor and the gate are electrically connected via the first resistor, and one of the source and drain of the N-type thin film transistor is connected to the first resistor and the second resistor. Electrically connected to the display unit via a resistor ;
One of the source and drain of the P-type thin film transistor is electrically connected to the gate through the first resistor, and one of the source and drain of the P-type thin film transistor is connected to the first resistor and the second resistor. Electrically connected to the display unit via a resistor;
The other of the source and drain of the N-type thin film transistor and the other of the source and drain of the P-type thin film transistor are electrically connected . A first substrate; a second substrate; a liquid crystal sandwiched between the first substrate and the second substrate;
The first substrate has a display unit and a protection circuit electrically connected to the display unit,
The second substrate includes a glass substrate, a film containing a patterned black pigment on the glass substrate, a red filter, a green filter and a blue filter, and the red filter, the green filter and the blue color on the film. A leveling layer made of a polyimide film on the filter, and a common electrode on the leveling layer,
The red filter, the green filter and the blue filter do not overlap each other,
The protection circuit includes an N-type thin film transistor, a P-type thin film transistor, a first resistor, and a second resistor, and is a semiconductor material that is doped or undoped, a transparent conductive material, or a wiring material Configured with
One of the source and drain of the N-type thin film transistor and the gate are electrically connected via the first resistor, and one of the source and drain of the N-type thin film transistor is connected to the first resistor and the second resistor. Electrically connected to the display unit via a resistor ;
One of the source and drain of the P-type thin film transistor is electrically connected to the gate through the first resistor, and one of the source and drain of the P-type thin film transistor is connected to the first resistor and the second resistor. Electrically connected to the display unit via a resistor;
The other of the source and drain of the N-type thin film transistor and the other of the source and drain of the P-type thin film transistor are electrically connected . A first substrate; a second substrate; a liquid crystal sandwiched between the first substrate and the second substrate;
The first substrate has a display unit and a protection circuit electrically connected to the display unit,
The second substrate includes a glass substrate, a polyimide film including a patterned black pigment on the glass substrate, a red filter, a green filter and a blue filter on the polyimide film, the red filter, the green filter, and A leveling layer made of a polyimide film on the blue filter, and a common electrode on the leveling layer,
The red filter, the green filter and the blue filter do not overlap each other,
The protective circuit includes an N-type thin film transistor, a P-type thin film transistor, a first resistor, and a second resistor, and is a semiconductor material that is doped or undoped, a transparent conductive material, or a wiring material Configured with
One of the source and drain of the N-type thin film transistor and the gate are electrically connected via the first resistor, and one of the source and drain of the N-type thin film transistor is connected to the first resistor and the second resistor. Electrically connected to the display unit via a resistor ;
One of the source and drain of the P-type thin film transistor is electrically connected to the gate through the first resistor, and one of the source and drain of the P-type thin film transistor is connected to the first resistor and the second resistor. Electrically connected to the display unit via a resistor;
The other of the source and drain of the N-type thin film transistor and the other of the source and drain of the P-type thin film transistor are electrically connected . In any one of Claims 1 to 12,
The electro-optical device, wherein the common electrode is made of ITO. In any one of Claims 1 thru / or Claim 13,
A television using the electro-optical device.

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