JPH0680659B2 - Wiring structure for semiconductor device and manufacturing method thereof - Google Patents

Wiring structure for semiconductor device and manufacturing method thereof

Info

Publication number
JPH0680659B2
JPH0680659B2 JP18038086A JP18038086A JPH0680659B2 JP H0680659 B2 JPH0680659 B2 JP H0680659B2 JP 18038086 A JP18038086 A JP 18038086A JP 18038086 A JP18038086 A JP 18038086A JP H0680659 B2 JPH0680659 B2 JP H0680659B2
Authority
JP
Japan
Prior art keywords
wiring
base
wiring structure
insulating
semiconductor device
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP18038086A
Other languages
Japanese (ja)
Other versions
JPS6336546A (en
Inventor
信幸 羽山
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Electric Co Ltd filed Critical Nippon Electric Co Ltd
Priority to JP18038086A priority Critical patent/JPH0680659B2/en
Publication of JPS6336546A publication Critical patent/JPS6336546A/en
Publication of JPH0680659B2 publication Critical patent/JPH0680659B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は半導体装置の配線構造体において、特に微細寸
法を有する配線構造体とその製造方法に関するものであ
る。
The present invention relates to a wiring structure of a semiconductor device, and more particularly to a wiring structure having a fine dimension and a method for manufacturing the same.

〔従来の技術〕[Conventional technology]

半導体装置、特に半導体集積回路においては高集積化・
高速化の方向で開発が進められている。したがってトラ
ンジスタ等の能動素子の微細化や高速化とともに電気信
号の伝送および給電・接地のために用いられる配線構造
体の微細化および低損失化が重要となる。すなわち配線
構造体が有する配線抵抗は、信号用配線においては伝送
される信号の減衰を、給電用配線においては電圧降下
を、接地用配線においては接地電位の変動を、それぞれ
生じさせるので、可能な限り低減させる必要がある。ま
た配線容量も高速・高周波信号の減衰および遅延を生じ
させるので、低減化が必要である。さらに同一平面上に
隣接する配線間の容量および多層配線間の容量も信号の
クロストークを生じさせるので低減化が必要である。
High integration in semiconductor devices, especially in semiconductor integrated circuits
Development is proceeding in the direction of speeding up. Therefore, it is important to miniaturize and speed up active elements such as transistors, and miniaturize and reduce loss of a wiring structure used for electric signal transmission and power feeding / grounding. In other words, the wiring resistance of the wiring structure causes attenuation of the transmitted signal in the signal wiring, a voltage drop in the power supply wiring, and a fluctuation in the ground potential in the ground wiring, which is possible. It is necessary to reduce as much as possible. In addition, the wiring capacitance also causes attenuation and delay of high-speed and high-frequency signals, so reduction is necessary. Further, the capacitance between wirings adjacent to each other on the same plane and the capacitance between multi-layer wirings also cause signal crosstalk, and therefore need to be reduced.

第2図は従来の配線構造体の電流方向に対し垂直な断面
を示す図である。同図において基体21は表面が絶縁性を
有するSiまたはGaAs等の半導体基板から成り、配線22は
AlまたはAu等の良導電性の材料から成る。配線22は略短
形断面を有し、その幅W方向は、基体21に対し、平行に
配置されている。
FIG. 2 is a view showing a cross section perpendicular to the current direction of a conventional wiring structure. In the figure, the base 21 is made of a semiconductor substrate such as Si or GaAs having an insulating surface, and the wiring 22 is
It is made of a material having good conductivity such as Al or Au. The wiring 22 has a substantially rectangular cross section, and its width W direction is arranged parallel to the base 21.

このような構造において配線抵抗の低減には従来より配
線材料として低固有抵抗材料を選択することのほか、配
線の厚さtあるいは配線の幅wを広げることにより図ら
れて来た。また配線容量の低減には基体21との対向面積
を減少させること、すなわち配線の幅wを減少させるこ
とにより図られて来た。
In such a structure, the wiring resistance has been conventionally reduced by selecting a low specific resistance material as the wiring material and widening the wiring thickness t or the wiring width w. Further, the wiring capacity has been reduced by reducing the area facing the base 21, that is, by reducing the width w of the wiring.

(発明が解決しようとする問題点) このような従来の配線構造体においては、次のような問
題点がある。すなわち配線抵抗の低減化のために配線の
幅wを広げることは配線容量の増加をもたらすとともに
集績回路の集績度を増すこと及びチップ寸法を縮少する
ことを困難にする。これ等の問題をさけるには配線断面
の厚みと幅の比すなわちアスペクトレシオt/wを大きく
することが必要となるが、アスペクトレシオt/wを大き
くするために厚みを増加するとストレスの増加等による
配線のはがれが発生し易い。また幅を小さくするにはEB
露光装置などによって微細パターンを描画したり、厚み
方向に精度よくエッチングするための装置を必要とする
ので、スループットの低下や生産性の低下、しいては生
産コストの増大をもたらす。
(Problems to be Solved by the Invention) Such a conventional wiring structure has the following problems. That is, widening the width w of the wiring to reduce the wiring resistance increases the wiring capacitance and makes it difficult to increase the collecting degree of the collecting circuit and reduce the chip size. In order to avoid these problems, it is necessary to increase the thickness-width ratio of the wiring cross section, that is, the aspect ratio t / w. Wiring is easily peeled off due to. To reduce the width, EB
Since an apparatus for drawing a fine pattern by an exposure apparatus or the like and for accurately etching in the thickness direction is required, throughput is lowered, productivity is lowered, and production cost is increased.

本発明の目的は上記のような問題点を解決し、配線容量
の増加および集績度の低下をもたらすことなく配線抵抗
の低減化を図れる配線構造体および極めて簡単なプロセ
スによる製造方法を提供することにある。
An object of the present invention is to solve the above-mentioned problems, and to provide a wiring structure capable of reducing the wiring resistance without increasing the wiring capacitance and decreasing the degree of accumulation, and a manufacturing method by an extremely simple process. Especially.

〔問題点を解決するための手段〕[Means for solving problems]

本発明の配線構造体は、半導体装置の基体と、前記基体
上に形成し前記基体の主面に対して傾斜を有する側面を
備えた絶縁性の支持体と、前記支持体の前記側面上に形
成した金属膜と、前記金属膜上に形成した絶縁膜とを有
し、その製造方法は、半導体装置の基体の主面に対して
傾斜を有する側面を備えた絶縁性の支持体を前記基体上
に形成する工程と、前記支持体を含む前記基体の主面に
金属膜および絶縁膜を順次に積層する工程と、前記基体
の主面に平行な前記金属膜上の前記絶縁膜を前記主面に
垂直な方向の異方性を有するエッチング手段によって除
去し、前記支持体の前記側面の前記金属膜上に絶縁性の
側壁を形成する工程と、前記側壁をマスクとして前記金
属膜の露出部をエッチングして除去する工程とを含んで
構成される。
The wiring structure of the present invention includes a base of a semiconductor device, an insulative support having a side surface formed on the base and having an inclination with respect to a main surface of the base, and an insulating support on the side surface of the support. A method of manufacturing the same includes a formed metal film and an insulating film formed on the metal film, and an insulating support having a side surface having an inclination with respect to a main surface of a base of a semiconductor device. Forming a metal film and an insulating film on the main surface of the base body including the support in order, and forming the insulating film on the metal film parallel to the main surface of the base body with the main film. Removing by an etching means having anisotropy in the direction perpendicular to the surface to form an insulating side wall on the metal film on the side surface of the support, and the exposed portion of the metal film using the side wall as a mask Is removed by etching.

〔作用〕[Action]

本発明における配線構造体においては基体の一主面に対
し配線構造体の幅方向が斜めに形成されているので、平
面寸法が同じの従来の配線構造体に比して配線の実効断
面積を広く取ることができる。さらに基体あるいは他の
配線に対する対向面が斜めになっているので、基体ある
いは他の配線間とに生ずる配線容量も減ずることができ
る。
In the wiring structure according to the present invention, the width direction of the wiring structure is formed obliquely with respect to the one main surface of the base body, so that the effective cross-sectional area of the wiring is smaller than that of the conventional wiring structure having the same plane dimension. Can be widely taken. Further, since the surface facing the substrate or other wiring is inclined, the wiring capacitance generated between the substrate or other wiring can be reduced.

〔実施例〕〔Example〕

以下、本発明について図面を参照しながら説明する。 Hereinafter, the present invention will be described with reference to the drawings.

第1図(a),(b),(c),および(d)は本発明
による半導体装置の配線構造体およびその製造方法の一
実施例を示す断面図である。各図は配線構造体に流す電
流の方向に対して垂直方向の断面を示す。
1 (a), (b), (c), and (d) are cross-sectional views showing an embodiment of a wiring structure of a semiconductor device and a method of manufacturing the same according to the present invention. Each drawing shows a cross section in the direction perpendicular to the direction of the current flowing through the wiring structure.

まず第1図(a)においてSiまたはGaAs等の半導体から
成る基体11上にSiO2またはSi3N4等の絶縁膜を成膜し、
所定パターンを有するフォトレジストマスク14を用いて
前記絶縁膜をウェットエッチングする。そしてエッチン
グの際に生ずるアンダーカットを利用して基体11に対し
傾斜した側面を有する絶縁性支持材13を形成する。エッ
チングには、たとえば絶縁膜がSiO2の場合にはフッ酸系
のエッチャントが適する。絶縁性支持材13の側面の傾斜
角θおよび幅wはエッチング条件および絶縁性支持材13
の厚みにより制御される。傾斜角θは望ましくは略45°
に設定するのが良い。
First, in FIG. 1 (a), an insulating film such as SiO 2 or Si 3 N 4 is formed on a substrate 11 made of a semiconductor such as Si or GaAs,
The insulating film is wet-etched using a photoresist mask 14 having a predetermined pattern. Then, the insulating support material 13 having side surfaces inclined with respect to the base 11 is formed by utilizing the undercut generated during the etching. For etching, for example, when the insulating film is SiO 2, a hydrofluoric acid-based etchant is suitable. The inclination angle θ and the width w of the side surface of the insulating support material 13 depend on the etching conditions and the insulating support material 13.
Controlled by the thickness of. The inclination angle θ is preferably about 45 °
It is better to set to.

つぎに第1図(b)に示すようにフォトレジストマスク
14を除去した後、絶縁性支持材13を含む基体11上に絶縁
性支持材13の側面上が所定の厚みtとなるようにAuまた
はAl等から成る配線用金膜15をスパッタ法あるいは蒸着
法などにより成膜する。さらに配線用金属膜15を覆うよ
うにSiO2またはSi3N4等の絶縁膜16をスパッタ法または
化学的気相成長法などにより成膜する。
Next, as shown in FIG. 1 (b), a photoresist mask
After removing 14, the wiring gold film 15 made of Au or Al is sputtered or vapor-deposited on the substrate 11 including the insulating support material 13 so that the side surface of the insulating support material 13 has a predetermined thickness t. The film is formed by a method or the like. Further, an insulating film 16 such as SiO 2 or Si 3 N 4 is formed so as to cover the wiring metal film 15 by a sputtering method or a chemical vapor deposition method.

さらに第1図(c)に示すように基体11の上面からCF4
ガス等の反応性ドライエッチングによる異方性エッチン
グによって基体11の一主面に対して平行な平坦面部分の
絶縁膜16を選択的に除去し、絶縁性支持材13上の側面上
のみに絶縁性側壁16aを形成する。
Further, as shown in FIG. 1 (c), CF 4
The insulating film 16 on the flat surface portion parallel to one main surface of the substrate 11 is selectively removed by anisotropic etching by reactive dry etching using gas or the like, and insulation is provided only on the side surface on the insulating support material 13. Forming a side wall 16a.

最後に第1図(d)に示すように絶縁性側壁16aをマス
クとして配線用金属膜15の露出領域をイオンミリング法
などによりエッチング除去する。このようにして平面寸
法wを有する配線15aが形成される。なお絶縁性側壁16a
は必要に応じて除去しても良い。
Finally, as shown in FIG. 1D, the exposed region of the wiring metal film 15 is removed by etching by ion milling or the like using the insulating side wall 16a as a mask. In this way, the wiring 15a having the plane dimension w is formed. Insulating side wall 16a
May be removed if necessary.

以上の工程によって基体11の一主面に対し幅w1方向が角
度θだけ傾斜した配線構造体が完成する。かかる配線構
造体の幅w1はw/cosθで与えられるから、その断面積は
略w・t/cosθとなる。したがって平面寸法が同じ(幅
w,厚みt)従来の配線構造体の断面積と比較すると1/co
sθ(|cosθ|<1)だけ大きな断面積が得られる。な
お傾斜角θを大きくすれば上記の改善効果を大きくする
ことができるが、配線用金属膜15を制御性良く被着する
ことが困難になるので、前述したようにθは略45°程度
が望ましい。
Through the above steps, the wiring structure in which the width w 1 direction is inclined by the angle θ with respect to the one main surface of the base 11 is completed. Since the width w 1 of such a wiring structure is given by w / cos θ, its cross-sectional area is approximately w · t / cos θ. Therefore, the plane dimensions are the same (width
w, thickness t) 1 / co when compared with the cross-sectional area of the conventional wiring structure
A cross-sectional area as large as sθ (| cosθ | <1) is obtained. It should be noted that if the tilt angle θ is increased, the above-described improvement effect can be increased, but it becomes difficult to deposit the wiring metal film 15 with good controllability, so that θ is about 45 ° as described above. desirable.

第1図においては基体11に対し傾斜した側面を有する絶
縁性支持材13の形成方法としてウェットエッチング法に
おけるアンダーカットを利用した方法を示したが、他の
手法として所定のパターンを有するフォトレジスト等の
有機物を高温で熱処理した際に生ずるパターン端部のダ
レを利用しても良い。すなわち該有機物を絶縁性支持材
13として直接利用するか、あるいはパターン端部のダレ
を一担他の絶縁膜に転写し該絶縁膜を絶縁性支持材13と
して利用しても良い。また他の手法として基体11に対し
て斜め入射されたイオンビームによるテーパエッチング
法により絶縁性支持材13を形成しても良い。
In FIG. 1, a method using undercut in a wet etching method is shown as a method of forming the insulating support material 13 having a side surface inclined with respect to the substrate 11, but as another method, a photoresist having a predetermined pattern or the like is used. It is also possible to use the sagging at the end of the pattern that occurs when the organic substance is heat-treated at a high temperature. That is, the organic substance is used as an insulating support material.
It may be directly used as 13, or the sag of the pattern end may be transferred to another insulating film, and the insulating film may be used as the insulating support material 13. As another method, the insulating support material 13 may be formed by a taper etching method using an ion beam obliquely incident on the substrate 11.

〔発明の効果〕 以上、説明したように本発明によれば絶縁性支持材の傾
斜した側面に配線を形成するので極めて簡単に微細な配
線構造体が実現できる。しかも基体に対して配線の幅方
向が斜めに形成されているので実効的な配線の断面積が
大きいことによる配線抵抵の低減、および基体あるいは
他の配線に対する対向面が斜めになるので、基体あるい
は他の配線間とに生ずる配線容量を減ずることができ
る。したがって半導体集績回路の高集績化・高速性能お
よび安定性の向上が図られる。
[Effects of the Invention] As described above, according to the present invention, since wiring is formed on the inclined side surface of the insulating support material, a fine wiring structure can be realized very easily. Moreover, since the width direction of the wiring is formed obliquely with respect to the base, the wiring resistance is reduced due to the large effective cross-sectional area of the wiring, and the opposing surface to the base or other wiring is inclined. Alternatively, the wiring capacitance generated between other wirings can be reduced. Therefore, the semiconductor collecting circuit can be improved in collecting performance, high-speed performance, and stability.

【図面の簡単な説明】[Brief description of drawings]

第1図は本発明の一実施例を示す工程断面図、第2図は
従来の配線構造体を示す断面図である。 11……基体、13……絶縁性支持材、15……配線用金属
膜、15a……配線、16a……絶縁性側壁。
FIG. 1 is a process sectional view showing an embodiment of the present invention, and FIG. 2 is a sectional view showing a conventional wiring structure. 11 ... Base, 13 ... Insulating support material, 15 ... Wiring metal film, 15a ... Wiring, 16a ... Insulating side wall.

Claims (2)

【特許請求の範囲】[Claims] 【請求項1】半導体装置の基体と、前記基体上に形成し
前記基体の主面に対して傾斜を有する側面を備えた絶縁
性の支持体と、前記支持体の前記側面上に形成した金属
膜とを有することを特徴とする半導体装置の配線構造
体。
1. A base of a semiconductor device, an insulative support having a side surface formed on the base and having an inclination with respect to a main surface of the base, and a metal formed on the side surface of the support. A wiring structure for a semiconductor device, comprising: a film.
【請求項2】半導体装置の基体の主面に対して傾斜を有
する側面を備えた絶縁性の支持体を前記基体上に形成す
る工程と、前記支持体を含む前記基体の主面に金属膜お
よび絶縁膜を順次に積層する工程と、前記基体の主面に
平行な前記金属膜上の前記絶縁膜を前記主面に垂直な方
向の異方性を有するエッチング手段によって除去し、前
記支持体の前記側面の前記金属膜上に絶縁性の側壁を形
成する工程と、前記側壁をマスクとして前記金属膜の露
出部をエッチングして除去する工程とを含むことを特徴
とする半導体装置の配線構造体の製造方法。
2. A step of forming an insulative support having a side surface inclined with respect to a main surface of a base of a semiconductor device on the base, and a metal film on the main surface of the base including the support. And a step of sequentially stacking insulating films, and removing the insulating film on the metal film parallel to the main surface of the base by etching means having anisotropy in a direction perpendicular to the main surface, And a step of forming an insulating side wall on the metal film on the side surface, and a step of etching and removing an exposed portion of the metal film using the side wall as a mask. Body manufacturing method.
JP18038086A 1986-07-30 1986-07-30 Wiring structure for semiconductor device and manufacturing method thereof Expired - Fee Related JPH0680659B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP18038086A JPH0680659B2 (en) 1986-07-30 1986-07-30 Wiring structure for semiconductor device and manufacturing method thereof

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP18038086A JPH0680659B2 (en) 1986-07-30 1986-07-30 Wiring structure for semiconductor device and manufacturing method thereof

Publications (2)

Publication Number Publication Date
JPS6336546A JPS6336546A (en) 1988-02-17
JPH0680659B2 true JPH0680659B2 (en) 1994-10-12

Family

ID=16082222

Family Applications (1)

Application Number Title Priority Date Filing Date
JP18038086A Expired - Fee Related JPH0680659B2 (en) 1986-07-30 1986-07-30 Wiring structure for semiconductor device and manufacturing method thereof

Country Status (1)

Country Link
JP (1) JPH0680659B2 (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2695919B2 (en) * 1989-06-01 1998-01-14 沖電気工業株式会社 Wiring pattern forming method

Also Published As

Publication number Publication date
JPS6336546A (en) 1988-02-17

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