JPH0677772A - Coefficient processing method, coefficient processing circuit and video tape recorder - Google Patents

Abstract

PURPOSE:To prevent divergence of the algorithm. CONSTITUTION:Digital data recorded on a magnetic tape 1 are reproduced by a magnetic head 2, equalized by an equalization circuit 7 consisting of an FIR transversal filter 5 and an arithmetic operation 21 and a decoder 8 discriminates the logic of the equalized data and outputs the result. The arithmetic operation circuit 21 monitors an odd number order of center tap coefficients in an FIR transversal filter 5 to discriminate whether or not the algorithm used for the filter is divergent and when it is discriminated that the algorithm is divergent, a threshold level TH used for discriminating the logic is revised to a level closer to 0.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a coefficient processing method, a coefficient processing circuit and a video tape recorder suitable for use in a digital video tape recorder for digitally recording and reproducing a video signal.

[0002]

2. Description of the Related Art FIG. 13 shows a structural example of a reproducing system of a conventional digital video tape recorder. Magnetic tape 1
Video data or audio data is recorded digitally on the. The magnetic head 2 is the magnetic tape 1.
To reproduce the data recorded on the
To the A / D converter 4 via. The data A / D converted by the A / D converter 4 is supplied to an odd-numbered FIR transversal filter 5 as an adaptive filter and an arithmetic circuit 6.

The arithmetic circuit 6 uses the data supplied from the A / D converter 4 to calculate the FIR transversal filter 5
The coefficient of the FIR transversal filter 5 is calculated.
Is output to. FIR type transversal filter 5
Is the coefficient supplied from the arithmetic circuit 6 to the A / D converter 4
The input data is multiplied and output to the decoder 8. The decoder 8 decodes the data supplied from the FIR transversal filter 5 which constitutes the equalization circuit (equalizer) 7 together with the arithmetic circuit 6, and outputs it as logic 1 or 0 data to a circuit (not shown).

The FIR type transversal filter 5 is
For example, it is configured as shown in FIG. That is, in this embodiment, the input data is the delay circuit 11 ₁
To 11 _N-1 are sequentially delayed. The input / output of each delay circuit 11 _{1 to} 11 _N-1 is
In the multipliers 12 _{0 to} 12 _N-1 , the coefficients P _{0 (n) to} P _{0 (n)}
It is multiplied by _{N-1 (n )} . The adder 13 is configured to add the outputs of the multipliers 12 _{0 to} 12 _N−1 and output the result.

Next, the operation of the arithmetic circuit 6 will be described with reference to the flowchart of FIG. The digital data reproduced from the magnetic tape 1 by the magnetic head 2 is amplified by the amplifier 3,
It is input to the A / D converter 4 and A / D converted. A / D
The data output from the converter 4 is input to an equalization circuit (equalizer) 7 including a filter 5 and an arithmetic circuit 6.

The arithmetic circuit 6 executes the same processing as the processing performed by the filter 5 having the configuration shown in FIG. 14 on the data input from the A / D converter 4 according to the flowchart of FIG. 15 by software. To do.

First, the arithmetic circuit 6 generates the same data as when it is sequentially delayed by one clock by the delay circuits 11 _{1 to} 11 _N-1 of the filter 5. As a result, the input data string X _(n) represented by the following equation is obtained (step S1). X _(n) = [x _(n) , x _(n-1) , ... x _{(n-N + 1)} ] ...
(1)

On the other hand, the following equation is formed by the tap coefficients P _{0 (n)} , P _{1 (n)} , ... P _{N-1 (n)} to be loaded into the multipliers 12 _{0 to} 12 _N-1. The indicated tap coefficient vector P _(n)
To generate. P _(n) = [P _{0 (n)} , P _{1 (n)} , ... P _{N-1 (n)} ] ...
(2)

Next, the multipliers 12 _{0 to} 12 _N-1 multiply the inputs and outputs of the delay circuits 11 _{1 to} 11 _N-1 by these tap coefficients and output the added values by the adder 13. The output y _(n) obtained in this case is calculated according to the following equation.
(Step S2). y _(n) = P _(n) X ' _(n) ... (3) Here, X' _(n) represents the transposed matrix of the vector X _(n) of the input data string.

Next, with the value y _(n) obtained in step S2,
The error ε _(n) is calculated from the target value d _(n) (step S
3).

The target value d _(n) is determined as follows from the relationship between the value of the output y _(n) and a preset threshold TH.

That is, d _(n) is set to 1 when y _(n) > TH, set to -1 when y _(n) <-TH, and -TH <y
_{When (n)} <TH, it is set to 0. Then, in each of these cases, the error ε _(n) is obtained from the following equations. When y _(n) > TH ε _(n) = d _(n) -y _(n) = 1-y _(n) ... (4) y _(n) <-TH If ε _(n) = d _(n) -y _(n) = -1-y _(n) (5) -TH <y _(n) <TH case ε _(n) = d _(n) -y _(n) = 0- y _(n) = -y _(n) (6)

Next, according to the LMS method (minimum mean square method) as a gradient method, the average 2 at a certain time point is calculated.
When the multiplication error is E [{ε _(n) } ² ], the next coefficient P _{(n + 1) of the} multipliers 12 _{0 to} 12 _N-1 is calculated according to the following equation. P _{(n + 1)} = P _(n) -(α / 2 ₎ ∇P _(n) E [{ε _(n) } ² ] = P _(n) −αE [ε _(n) ∇P _(n) { ε _(n) }] = P _(n) −αE [ε _(n) X _(n) ] (7) where α is a step size, and is a size at which the gradient (gradient) is decreased at a time. It is a positive number to determine.

However, when the state of the signal input from the A / D converter 4 changes with time, the expected value E [ε _(n) X _(n) ] of the signal also changes. Therefore, the unbiased variance value ε _(n) X _(n) is used instead of the expected value. As a result, the equation (7) can be rewritten as follows. P _{(n + 1)} = P _(n) -αε _(n) X _(n) (8)

According to this equation, the tap coefficients of the soft multipliers 12 _{0 to} 12 _{N-1 in} the arithmetic circuit 6 are updated (step S4).

Then, the coefficients thus calculated are loaded into the actual multipliers 12 _{0 to} 12 _N-1 of the filter 5 (step S5).

As described above, the coefficients calculated by the calculation circuit 6 are loaded into the respective multipliers of the filter 5, and A /
The data output from the D converter 4 is multiplied by the coefficient to be equalized. Then, this equalized output is output to the decoder 8. The decoder 8 compares the output of the filter 5 with a predetermined threshold value and determines (decodes) the logic of 1 or 0.

[0018]

As described above, the conventional device updates the tap coefficient according to the LMS (Least Mean Square) method so that the error of the input data with respect to the target value becomes zero. I have to. As a result, when, for example, a head clock portion or a non-signal portion is reproduced from the magnetic tape 1, data close to 0 is input for a relatively long time, so that the output of the filter 5 is entirely output by the decoder 8. It is decoded as a logic 0, and the tap coefficient of the filter 5 is continuously updated so that the output y _(n) itself becomes an error ε _(n) and approaches 0 according to the equation (6). Therefore, after that, even if a normal input signal is supplied, the tap coefficient becomes too small,
The output of the filter 5 is not decoded as logic 1 in the decoder 8 and there is a problem that it diverges.

The present invention has been made in view of such a situation, and aims to prevent divergence.

[0020]

The coefficient processing method according to claim 1 is a coefficient processing method of an odd-order FIR transversal filter 5 for equalizing by multiplying input data by a predetermined coefficient, The error between the value corresponding to the output of the filter 5 and the target value is calculated, a new coefficient for minimizing the mean square value of the error is calculated, and the value corresponding to the coefficient of the center tap of the filter 5 is set to a predetermined reference. It is characterized by comparing with a value.

A coefficient processing circuit according to a second aspect of the present invention is an odd-order F which multiplies input data by a predetermined coefficient to equalize the data.
In the coefficient processing circuit having the IR transversal filter 5 and the calculation circuit 21 for calculating the coefficient of the filter 5, the calculation circuit 21 calculates the error between the value corresponding to the output of the filter 5 and the target value. S13 as a calculation means of the above, and step S14 as a second calculation means for calculating a new coefficient that minimizes the mean square value of the error.
And step S15 as a comparison means for comparing the value corresponding to the coefficient of the center tap of the filter 5 with a predetermined reference value.
And is provided.

A video tape recorder according to a third aspect of the present invention is a magnetic head 2 for reproducing the data recorded on the magnetic tape 1, and an odd-order FIR for multiplying the data reproduced by the magnetic head 2 by a predetermined coefficient. In a video tape recorder having a type transversal filter 5 and a calculation circuit 21 for calculating the coefficient of the filter 5, a step as a first calculation means for calculating an error between a value corresponding to the output of the filter 5 and a target value. S13 and average of error 2
It is provided with step S14 as a second calculation means for calculating a new coefficient for minimizing the power value and step S15 as a comparison means for comparing the coefficient of the center tap of the filter 5 with a predetermined reference value. And

According to the coefficient processing method of claim 4, in the coefficient processing method of the FIR transversal filter 5 as an adaptive filter for multiplying input data by a predetermined coefficient to equalize, the output of the filter 5 is used. The error between the corresponding value and the target value is calculated, a new coefficient that minimizes the mean square value of the error is calculated, the value corresponding to the output of the filter 5 is decoded, and the continuous value of the decoded data is calculated. The number of logical 0s or 1s to be counted is counted and the counted number is compared with a predetermined reference value.

A coefficient processing circuit according to a fifth aspect of the present invention is a FIR transversal filter 5 as an adaptive filter that multiplies input data by a predetermined coefficient to equalize the data, and an arithmetic circuit that calculates the coefficient of the filter 5. 31 and filter 5
In the coefficient processing circuit that includes the decoder 8 that decodes the output of the filter 5, the calculation circuit 31 calculates the error between the target value and the value corresponding to the output of the filter 5 in step S23, and Step S24 as a second calculating means for calculating a new coefficient that minimizes the mean square value, and the number of consecutive logic 0 or 1 in the data corresponding to the data decoded by the decoder 8 is counted. It is characterized by including step S26 as counting means and step S27 as comparing means for comparing the count value counted by the counting means with a predetermined reference value.

A video tape recorder according to a sixth aspect of the present invention serves as a magnetic head 2 for reproducing the data recorded on the magnetic tape 1, and an adaptive filter for multiplying the data reproduced by the magnetic head 2 by a predetermined coefficient. In a video tape recorder having the FIR transversal filter 5, an arithmetic circuit 31 for computing the coefficient of the filter 5, and a decoder 8 for decoding the output of the filter 5,
The arithmetic circuit 31 operates as a first arithmetic unit that calculates an error between the value corresponding to the output of the filter 5 and the target value, and a new coefficient that minimizes the mean square value of the error. 2 as the calculation means, step S26 as the counting means for counting the number of consecutive logic 0 or 1 in the data corresponding to the data decoded by the decoder 8, and the count value counted by the counting means. Is compared with a predetermined reference value, and step S27 as a comparison means is provided.

According to the coefficient processing method of claim 7, in the coefficient processing method of the FIR type transversal filter 5 as an adaptive filter for multiplying input data by a predetermined coefficient to equalize, the output of the filter 5 is used. The error between the corresponding value and the target value is calculated, a new coefficient that minimizes the mean square value of the error is calculated, the output of the filter 5 is decoded by the Viterbi decoder 44, and the continuous data among the decoded data is calculated. The number of logical 0s or 1s to be stored is stored.

The coefficient processing circuit according to claim 8 is a FIR transversal filter 5 as an adaptive filter for equalizing by multiplying input data by a predetermined coefficient, and an arithmetic circuit for calculating the coefficient of the filter 5. 41 and the filter 5
In the coefficient processing circuit including the Viterbi decoder 44 that decodes the output of the filter 5, the calculation circuit 41 calculates the error between the value corresponding to the output of the filter 5 and the target value, and the step S43 as the first calculation means and the error. And the step S44 as a second calculation means for calculating a new coefficient that minimizes the mean square value of the Viterbi decoder 44, the Viterbi decoder 44 stores the number of consecutive logical 0 or 1 for the capacity, Is provided with a buffer memory 45 as a storage means for outputting an overflow signal.

A video tape recorder according to a ninth aspect of the invention is a magnetic head 2 for reproducing the data recorded on the magnetic tape 1, and an adaptive filter for multiplying the data reproduced by the magnetic head 2 by a predetermined coefficient. In the video tape recorder having the FIR transversal filter 5, the arithmetic circuit 41 for arithmetically operating the coefficient of the filter 5, and the Viterbi decoder 44 for decoding the output of the filter 5, the arithmetic circuit 41 corresponds to the output of the filter 5. Step S43 as a first calculating means for calculating the error between the value and the target value, and step S4 as a second calculating means for calculating a new coefficient that minimizes the mean square value of the error.
4, the Viterbi decoder 44 stores the number of consecutive logical 0s or 1s by its capacity, and includes a buffer memory 45 as a storage unit that outputs an overflow signal when the capacity overflows. To do.

A coefficient processing circuit according to a tenth aspect of the present invention includes an FIR type transversal filter 5 for multiplying input data by a predetermined coefficient for equalization, and an arithmetic circuit 21 for calculating the coefficient of the filter 5. In the coefficient processing circuit,
The arithmetic circuit 21 operates as an error calculating means for calculating an error between the value corresponding to the output of the filter 5 and the target value in step S.
13, step S14 as a coefficient calculation means for calculating a new coefficient that minimizes the mean square value of the error, and step S15 as a detection means for detecting the divergence of the filter 5.
And step S16 as control means for controlling the threshold value for estimating the target value, corresponding to the detection result of step S15.
And is provided.

A coefficient processing circuit according to a eleventh aspect of the present invention has an FIR type transversal filter 5 for equalizing input data by multiplying a predetermined coefficient, and an arithmetic circuit 31 for calculating the coefficient of the filter 5. In the coefficient processing circuit,
The arithmetic circuit 31 is a step S as an error calculating means for calculating an error between the value corresponding to the output of the filter 5 and the target value.
23, step S24 as a coefficient calculation means for calculating a new coefficient for minimizing the mean square value of the error, and step S27 as a detection means for detecting the divergence of the filter 5.
And a step S28 as a coefficient changing means for changing the coefficient to a coefficient for suppressing divergence, corresponding to the detection result of step S27.

[0031]

According to the present invention, the value corresponding to the coefficient of the center tap of the odd-type FIR transversal filter 5 is compared with a predetermined reference value.

Further, in the invention described in claims 4 to 6, among the data corresponding to the decoded data,
The number of consecutive logic 0's or 1's is counted and the count value is compared with a predetermined reference value.

Further, in the invention described in claims 7 to 9, the number of consecutive logic 0 or 1 of the data decoded by the Viterbi decoder 44 is stored.

Therefore, in any case, the divergence can be reliably detected with a simple structure, and the divergence state can be quickly recovered.

According to the tenth aspect of the invention, when the divergence is detected, the threshold value for estimating the target value is changed.

Further, in the invention described in claim 11, the coefficient is changed when divergence is detected.

Therefore, in any case, the divergent state can be avoided or the divergent state can be quickly returned to in a simple and reliable manner.

[0038]

1 is a block diagram showing the configuration of an embodiment of a video tape recorder according to the present invention, in which parts corresponding to those in FIG. 13 are designated by the same reference numerals. In this embodiment, the equalization circuit 7 is composed of a filter 5 and an arithmetic circuit 21. Other configurations are shown in FIG.
It is similar to the case in. That is, the video tape recorder of the present invention is basically configured similarly to the conventional case shown in FIG. 13, and the arithmetic processing in the arithmetic circuit 21 is different from the conventional case.

Therefore, the operation will be described below with reference to the flow chart of FIG.

The processing of steps S11 to S14 is shown in FIG.
This is the same as the processing of steps S1 to S4 shown in FIG.
That is, up to this point, the same processing as in the conventional LMS algorithm is executed.

Then, after step S14, step S
In step 15, the coefficient of the center tap of the filter 5 is detected by the arithmetic circuit 21, and its value is compared with a predetermined reference value set in advance. When the FIR transversal filter 5 of odd order diverges, the tap coefficient thereof finally becomes 0.

Here, it will be explained that when the tap coefficient of the filter 5 diverges, it becomes 0.

From the above equation (3), the output y _(n) of the filter 5 can be expressed by the following equation.

[0044]

[Equation 1]

The mean square error MSE can be expressed by the following equation.

[0046]

[Equation 2]

Where ∂MSE / ∂P ₀ = ∂MSE / ∂P ₁
= ... ∂MSE / ∂P _N-1 = 0 for tap coefficient P ₀ ,
The optimum coefficient is P ₁ , ... P _N-1 .

Now, the following equation is established. ∂MSE / ∂P _k = -2E [d _(n) x _(nk) ] + 2ΣP _i E [x _(ni) x _(nk) ] (11) ∂MSE / ∂P _k = 0 ... ( 12)

Therefore, the following equation holds.

[0050]

[Equation 3]

Here, when d _(n) = 0, the equation (13) can be expressed by the following equation.

[0052]

[Equation 4]

Here, since E [x _(ni) x _(nk) ] ≠ 0, the following equation is satisfied to satisfy the above equation (14). P ₀ = P ₁ = ... P _k = ... P _N-1 = 0 ... (15)

With such divergence, the tap coefficient finally becomes zero. Therefore, in order to detect this divergence symptom, it is determined in step S15 whether or not the tap coefficient continuously decreases. The number of consecutive times (reference value) that serves as a criterion for determination can be appropriately set in the system.

If it is determined in step S15 that there is a tendency of divergence, the process proceeds to step S16, and the threshold value used in calculating the error ε _(n) in step S13 (equations (4) to (6)). Decrease TH (close to 0).

That is, as shown in FIG. 3, a positive threshold value TH is provided between the positive value output from the A / D converter 4 and 0 with respect to the input 1 and the input -1. Against A
A negative threshold value between the negative value output from the / D converter 4 and 0
TH is provided. As described above, a value equal to or higher than TH is determined to be a logic 1, a value equal to or lower than −TH is determined to be −1, and a value between −TH and TH is determined to be 0, but in step S16. As a result of bringing TH closer to 0, the range in which the data input from the A / D converter 4 is determined to be logic 0 is narrowed as shown by the broken line in FIG.
This causes a lot of data to be judged as logical 1 or -1. As a result, divergence is suppressed, or even if it occurs, it is quickly avoided.

After step S16, the process returns to step S11 to repeat the subsequent processing.

If it is determined in step S15 that the tap coefficient has not decreased (not diverged), the process proceeds to step S17, where the threshold value TH is the original value (the value before being decreased in step S16). ), And if it is not the original value (if it is the reduced value in step S16), the process proceeds to step S18 and this threshold TH is increased (returned to the original value). ). Thereafter, the process proceeds to step S19, the coefficient is loaded into each of the multipliers 12 ₀ to 12 _N-1 of the filter 5. When it is determined in step S17 that the threshold value TH is the original value, step S18 is skipped and the process directly proceeds to step S19. After step S19, the process returns to step S11, and the subsequent processes are repeatedly executed.

FIG. 4 shows a second embodiment of the video tape recorder of the present invention. In this embodiment, F
IR transversal filter 5 and equalization circuit 7
The arithmetic circuit 31 constituting the above-mentioned device has a built-in counter 32, and the memory 33 is connected to the arithmetic circuit 31.
Other configurations are similar to those in FIG.

Next, the operation of the embodiment shown in FIG. 4 will be described with reference to FIG.
This will be described with reference to the flowchart in FIG.

The processing of steps S21 to S24 is shown in FIG.
The processing is the same as the processing of steps S11 to S14 in (the processing of steps S1 to S4 in FIG. 15). That is, the processing of the normal LMS algorithm is executed.

Next, in step S25, the arithmetic circuit 3
1 determines whether or not the logic decoded by comparing the output of the A / D converter 4 with the threshold value TH is 0 (or may be logic 1) in the internal software. If not logical 0 (if logical 1), the process proceeds to step S29,
The counter 32 incorporated in the arithmetic circuit 31 is reset. Then, the new coefficient calculated in step S24 is loaded into each multiplier of the filter 5 in step S30. After step S30, step S21
Then, the subsequent processing is repeated.

When it is determined in step S25 that the logic decoded by the internal software is 0, the process proceeds to step S26 and the value of the counter 32 is incremented by 1. Then, in step S27, it is determined whether or not the count value of the counter 32 is larger than a preset assumed zero run number.

The maximum value T _max (maximum inversion interval) in which logic 0 continues is the modulation method (for example, M) in the magnetic tape 1.
² , 8-10 conversion method)). Therefore, the number of zero runs is set corresponding to this T _max .
In the case of NRZ, T _max theoretically becomes infinite, but if the number of zero runs is actually measured under the actual detection method and system, the number of zero runs having a probability lower than the predetermined occurrence probability can be obtained. Therefore, in this case, the value of the extremely low occurrence probability may be set as the assumed zero run number.

As described above, in the case where the number of logic 0s, which is larger than the number of zero runs determined by the modulation method, continues, this can be determined as divergence. Therefore, in this case, the process proceeds from step S27 to step S28,
At this time, the data used for the calculation in the calculation circuit 31 and the data obtained by the calculation based on the data are discarded. Then, an initial value stored in advance in the memory 33 is set in each multiplier of the filter 5. This initial value is
Not to mention that the value does not diverge. Alternatively, as the value set at this time, the tap coefficient in the non-divergent state may be stored in the memory 33 at any time, and this data may be read and loaded.

After step S28, the process returns to step S21, and the subsequent processes are repeated.

When it is determined in step S27 that the count value of the counter 32 is smaller than the assumed number of zero runs, no divergence has occurred, so the process returns to step S22 and the subsequent processing is repeated.

FIG. 6 shows still another embodiment of the video tape recorder of the present invention. In this embodiment, the arithmetic circuit 41, which constitutes the equalizing circuit 7 together with the filter 5, has a built-in counter 42 and the arithmetic circuit 4
A memory 43 is connected to 1. Further, in this embodiment, the decoder is composed of a Viterbi decoder 44, and this Viterbi decoder 44 has a buffer memory 45 built therein. Then, the buffer memory 45
Is supplied to the counter 42. Other configurations are the same as those in FIG.

The feature of this embodiment is that the Viterbi decoder 44 is used as a decoder. Therefore, first, the operation of this Viterbi decoder will be described. Now, it is assumed that the Viterbi decoder 44 uses the Ferguson algorithm and uses PR4 (Partial Response Class IV) as the reproduction detection method. PR4
Has 1-D ² as the characteristic of the system, which can be divided into two systems having the characteristic of 1-D and 1 + D.

The trellis diagram corresponding to the system having the characteristic of 1-D is as shown in FIG. Data can be decoded by following this trellis diagram. That is, on this trellis diagram, the accumulated metric is compared at each time and the path is traced to obtain the decoded data.

-1, 0, 1 on the path shown in FIG. 7 indicates the decoded result. In the case of NRZI, this 1, -1
Will eventually be decoded as 1.

In the Ferguson algorithm, at each time, the three types of merges shown in FIG. 8 are detected, the paths obtained by them are traced, and the data is decoded. The three types of merges are plus (+) merge, minus (-) merge, and non-merge.

This merge can be detected as follows using Δ _k expressed by the following equation. ^{_{Here, f k +, f k -}} - Δ k = f k + -f k are each S _k = + 1 and S _k =
-1 (FIG. 7). Further, y _k in the following equation is the value of the identification point of the reproduced signal.

Case 1: When Δ _k −y _{k + 1} > 1, Plus Merge Δ _{k + 1} = y _{k + 1} +1 Case 2: When <1 <Δ _k −y _{k + 1} <1, Non-merge Δ _{k + 1} = Δ _k Case 3: When Δ _k −y _{k + 1} <−1, minus merge Δ _{k + 1} = y _{k + 1} −1

That is, the merging is detected by focusing on whether Δ _k −y _{k + 1} is 1 or more or −1 or less.

Next, the actual detection operation will be described. As shown in FIG. 9, 1.8, 1.2, -at the reproduction identification points at the respective timings of k = 1, 2, and 3.
It is assumed that the data of 1.7 is output from the A / D converter 4. However, the levels of these signals are supposed to be -2, 0, and 2, respectively.

If the threshold value TH is 1 in the conventional decoder, this data series is decoded as 1 if 1 or more, -1 if -1 or less, or -1 or if a value between 1 and 1 is 0. It is decoded as (1,1, -1).

On the other hand, in the Viterbi decoder 44 based on the Ferguson algorithm, merge is detected at the time of k = 1. Here, if Δ ₀ = 0, the value of y ₁ is now 1.8, which corresponds to case 3 described above, and a minus merge is detected (FIG. 1).
0). As a result, Δ ₁ becomes 0.8 according to the following equation. Δ ₁ = y ₁ -1 = 1.8-1 = 0.8

Next, at the timing of k = 2, y
_{Since 2} = 1.2 and Δ ₁ is 0.8, the non-merge is detected corresponding to the case 2 described above.

That is, as shown in FIG. 10, when k = 1, there is a merge threshold in the range of ± 1 centering on Δ ₀ = 0, and when k = 2, Δ ₁ = It has a merging threshold in the range of ± 1 around 0.8, ie at 1.8 and −0.2. In FIG. 10, minus merge occurs when the upper threshold is exceeded, and plus merge occurs when the lower threshold is exceeded.

As described above, the trellis diagram represented by the merge shown in FIG. 11 is obtained corresponding to the examples shown in FIGS. 9 and 10.

As is clear from FIG. 11, the decoded data in this case is (1, 0 ,?). At k = 3 ,? This is because the next merge has not yet been decided.

In the conventional decoder, the second data is decoded as logic 1, but in the Viterbi decoder it is understood that it is decoded as logic 0.

Since the magnetic recording / reproducing system has a differential characteristic, 0 or low level (-1) should occur after the high level (+1). However, k = 2
, The conventional decoded data is high level (+1)
However, in the Viterbi decoder, it is correctly 0.
Is decoded.

However, when decoding is performed by this Viterbi decoder, when a merge occurs at time k-1,
The decode value at time k is not determined until the next merge occurs. Therefore, provisional estimation is performed without waiting for the next merge, this is stored in the buffer memory 45, and this is rewritten when a merge occurs later.

The tentative estimation can be performed according to the following rules. (1) When positive merge occurs at time k-1 When Δ _k > 0 b _(k) = 0 When Δ _k <0 b _(k) = 1 (2) Negative merge occurs at time k-1 When Δ _k > 0 b _(k) = 1 When Δ _k <0 b _(k) = 0 (3) When no merge occurs at time k−1 b _(k) = 0 B _(k) represents the estimated decoded value at time k.

When the non-merge occurs continuously beyond the capacity of the buffer memory 45, the estimated value obtained by the above method overflows and is output. If the equalization algorithm falls into a divergent state due to the reproduction of the head clock or the no-signal recording unit, the output of the filter 5 (the input of the Viterbi decoder 44) continuously has a value close to 0, and the above-mentioned (3) The non-merge state of will be continuous.

The fact that the overflow continues when the capacity of the buffer memory 45 is increased to some extent can be considered as the divergence of the algorithm. Therefore, the divergence of the algorithm can be detected by feeding back this overflow information to the algorithm.

In accordance with the above principle, the processing shown in the flowchart of FIG. 12 is executed in the embodiment of FIG. That is, first in steps S41 to S45,
The same LMS processing as in steps S1 to S5 shown in FIG. 15 is executed.

Then, from step S45 to step S4
6, the counter 42 incorporated in the arithmetic circuit 41 counts when the output buffer memory 45 of the Viterbi decoder 44 outputs a flag indicating overflow. Then, in step S47, it is determined whether or not the count value is equal to or larger than a predetermined reference value R set in advance. If the count value is smaller than the reference value R, no divergence has occurred, and therefore the process returns to step S41 and the subsequent processes are repeated.

On the other hand, in step S47,
When it is determined that the count value is equal to or greater than the reference value R, it is determined that divergence has occurred, the process proceeds to step S48, and the coefficient of the initial value stored in the memory 43 is read,
It is loaded into the multiplier of filter 5. Then, the algorithm is reset once. After step S48, the process returns to step S41, and the subsequent processes are repeatedly executed.

In this embodiment as well, it is possible to store the tap coefficient in a state in which it does not diverge in the memory 43 and load it in step S48.

In the above embodiment, the same processing as that executed by the filter 5 is performed by the arithmetic circuits 21, 31, 4
Although the calculation is performed by software in No. 1, the calculation can be performed using the actual output of the filter 5 and the decoder 8.

In the above embodiment, the divergence or its tendency is detected by the coefficient of the center tap, the zero run or the overflow, and the threshold TH is changed or the coefficient is changed as the processing when the divergence or its tendency is detected. Although the predetermined initial value or the predetermined coefficient that does not diverge is changed, the divergence detection method and the processing method when detected can be arbitrarily combined.

[0095]

As described above, according to the coefficient processing method, the coefficient processing circuit and the video tape recorder described in claims 1 to 3, the coefficient of the center tap of the filter is compared with a predetermined reference value.

Further, according to the coefficient processing method, the coefficient processing circuit and the video tape recorder described in claims 4 to 6, the count value of continuous logic 0 or 1 in the decoded data is set as the predetermined reference value. I tried to compare.

Further, according to the coefficient processing method, the coefficient processing circuit and the video tape recorder described in claims 7 to 9, a signal in which the number of consecutive logical 0s or 1s overflows is detected.

Therefore, in any case, it is possible to reliably detect the divergence or its tendency and avoid the divergence or promptly return to the non-divergence state even if the divergence occurs, with a simple configuration. .

According to the invention described in claim 10,
When divergence was detected, the threshold value for estimating the target value was changed.

According to the eleventh aspect of the invention, the coefficient is changed when divergence is detected.

Therefore, in any case, it is possible to easily and reliably avoid the divergent state or quickly recover from the divergent state.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of an embodiment of a video tape recorder of the present invention.

FIG. 2 is a flowchart illustrating the operation of the embodiment of FIG.

FIG. 3 is a diagram illustrating a process of step S16 of FIG.

FIG. 4 is a block diagram showing the configuration of another embodiment of the video tape recorder of the present invention.

5 is a flowchart illustrating the operation of the embodiment of FIG.

FIG. 6 is a block diagram showing the configuration of still another embodiment of the video tape recorder of the present invention.

7 is a trellis diagram for explaining the operation principle of the Viterbi decoder 44 of FIG.

FIG. 8 is a diagram illustrating the merging of FIG. 7.

9 is a diagram illustrating an operation of the Viterbi decoder 44 of FIG.

FIG. 10 is a diagram illustrating a merge threshold in the example of FIG.

FIG. 11 is a trellis diagram corresponding to the input of FIG.

12 is a flowchart illustrating the operation of the embodiment of FIG.

FIG. 13 is a block diagram showing a configuration example of a conventional video tape recorder.

14 is a block diagram showing a configuration example of the FIR transversal filter 5 of FIG.

FIG. 15 is a flowchart illustrating the operation of FIG.

[Explanation of symbols]

1 magnetic tape 2 magnetic head 3 amplifier 4 A / D converter 5 FIR type transversal filter 6 arithmetic circuit 7 equalization circuit 8 decoder 11 _{1 to} 11 _N-1 delay circuit 12 _{0 to} 12 _N-1 multiplier 13 adder 21, 31 arithmetic circuit 32 counter 33 memory 41 arithmetic circuit 42 counter 43 memory 44 Viterbi decoder 45 buffer memory

Claims (11)

[Claims] 1. A coefficient processing method for an odd-order FIR transversal filter that multiplies input data by a predetermined coefficient for equalization, and calculates an error between a value corresponding to the output of the filter and a target value. Then, a new coefficient that minimizes the mean square value of the error is calculated, and the value corresponding to the coefficient of the center tap of the filter is compared with a predetermined reference value. 2. A coefficient processing circuit having an odd-order FIR transversal filter for equalizing input data by multiplying it by a predetermined coefficient, and an operation circuit for calculating the coefficient of the filter, The circuit includes a first calculation unit that calculates an error between a value corresponding to the output of the filter and a target value, and a second calculation unit that calculates a new coefficient that minimizes the mean square value of the error. A coefficient processing circuit for comparing a value corresponding to a coefficient of a center tap of the filter with a predetermined reference value. 3. A magnetic head for reproducing data recorded on a magnetic tape, an odd-order FIR transversal filter for multiplying data reproduced by the magnetic head by a predetermined coefficient, and the coefficient of the filter. In a video tape recorder having a calculation circuit for calculating, a first calculation means for calculating an error between a value corresponding to the output of the filter and a target value, and a new means for minimizing the mean square value of the error. A video tape recorder, comprising: a second calculating means for calculating a coefficient; and a comparing means for comparing a value corresponding to the coefficient of the center tap of the filter with a predetermined reference value. 4. A coefficient processing method for an adaptive filter, which multiplies input data by a predetermined coefficient for equalization, calculates an error between a value corresponding to the output of the adaptive filter and a target value, A new coefficient that minimizes the mean square value is calculated, the value corresponding to the output of the adaptive filter is decoded, and a continuous logic 0 or 1 is included in the decoded data.
The coefficient processing method is characterized by counting the number of cells and comparing the counted number with a predetermined reference value. 5. Coefficients including an adaptive filter that multiplies input data by a predetermined coefficient for equalization, an arithmetic circuit that calculates the coefficient of the adaptive filter, and a decoder that decodes the output of the adaptive filter. In the processing circuit, the arithmetic circuit calculates a first arithmetic means for calculating an error between a value corresponding to the output of the adaptive filter and a target value, and a new coefficient for minimizing a mean square value of the error. Second counting means, counting means for counting the number of consecutive logic 0 or 1 in the data corresponding to the data decoded by the decoder, and a count value counted by the counting means to a predetermined reference value. A coefficient processing circuit including: 6. A magnetic head for reproducing data recorded on a magnetic tape, an adaptive filter for multiplying the data reproduced by the magnetic head by a predetermined coefficient, and an arithmetic circuit for calculating the coefficient of the adaptive filter. And a decoder for decoding the output of the adaptive filter, wherein the arithmetic circuit calculates a difference between a value corresponding to the output of the adaptive filter and a target value, and Second computing means for computing a new coefficient for minimizing the mean square value of the error, and counting means for counting the number of consecutive logic 0 or 1 in the data corresponding to the data decoded by the decoder. And a comparison means for comparing the count value counted by the counting means with a predetermined reference value. 7. A coefficient processing method of an adaptive filter for multiplying input data by a predetermined coefficient for equalization, wherein an error between a value corresponding to an output of the adaptive filter and a target value is calculated, and the error A new coefficient that minimizes the mean square value is calculated, the output of the adaptive filter is decoded by a Viterbi decoder, and a continuous logic 0 or 1 of the decoded data is calculated.
A coefficient processing method characterized by storing the number of 8. An adaptive filter that multiplies input data by a predetermined coefficient to equalize it, an arithmetic circuit that calculates the coefficient of the adaptive filter, and a Viterbi decoder that decodes the output of the adaptive filter. In the coefficient processing circuit, the arithmetic circuit includes a first arithmetic unit that calculates an error between a value corresponding to the output of the adaptive filter and a target value, and a new coefficient that minimizes a mean square value of the error. A second computing means for computing, wherein the Viterbi decoder stores the number of consecutive logical 0s or 1s for the capacity thereof,
A coefficient processing circuit comprising storage means for outputting an overflow signal when the capacity overflows. 9. A magnetic head for reproducing data recorded on a magnetic tape, an adaptive filter for multiplying data reproduced by the magnetic head by a predetermined coefficient, and an arithmetic circuit for calculating the coefficient of the adaptive filter. A video tape recorder having a Viterbi decoder for decoding the output of the adaptive filter, wherein the arithmetic circuit calculates a difference between a value corresponding to the output of the adaptive filter and a target value; A second computing unit for computing a new coefficient that minimizes the mean square value of the error, wherein the Viterbi decoder stores the number of consecutive logical 0s or 1s corresponding to its capacity,
A video tape recorder comprising storage means for outputting an overflow signal when the capacity overflows. 10. A coefficient processing circuit having an FIR transversal filter for equalizing input data by multiplying a predetermined coefficient, and an arithmetic circuit for calculating the coefficient of the filter, wherein the arithmetic circuit comprises: Error calculation means for calculating an error between a value corresponding to the output of the filter and a target value, coefficient calculation means for calculating a new coefficient for minimizing the mean square value of the error, and divergence of the filter is detected. And a control unit that controls a threshold value for estimating the target value in accordance with a detection result of the detection unit. 11. A coefficient processing circuit having an FIR transversal filter for equalizing input data by multiplying a predetermined coefficient, and an arithmetic circuit for calculating the coefficient of the filter, wherein the arithmetic circuit comprises: Error calculation means for calculating an error between a value corresponding to the output of the filter and a target value, coefficient calculation means for calculating a new coefficient for minimizing the mean square value of the error, and divergence of the filter is detected. And a coefficient changing circuit that changes the coefficient into a coefficient that suppresses divergence in accordance with the detection result of the detecting means.