JPH067574B2 - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPH067574B2 JPH067574B2 JP62082302A JP8230287A JPH067574B2 JP H067574 B2 JPH067574 B2 JP H067574B2 JP 62082302 A JP62082302 A JP 62082302A JP 8230287 A JP8230287 A JP 8230287A JP H067574 B2 JPH067574 B2 JP H067574B2
- Authority
- JP
- Japan
- Prior art keywords
- pull
- gate
- transistor
- output buffer
- resistance
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
- H01L27/10—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
- H01L27/118—Masterslice integrated circuits
- H01L27/11898—Input and output buffer/driver structures
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
- Design And Manufacture Of Integrated Circuits (AREA)
- Semiconductor Integrated Circuits (AREA)
Description
【発明の詳細な説明】 〔産業上の利用分野〕 本発明はプルアップ抵抗またはプルダウン抵抗を有する
半導体装置に関する。The present invention relates to a semiconductor device having a pull-up resistor or a pull-down resistor.
従来この種の半導体装置は図３に示す様に、プルアップ
抵抗，プルダウン抵抗は出力バッファとは別にドレイ
ン，ゲート，ソースを形成してトランジスタ抵抗として
いた。図はプルダウン抵抗を有する入出力バッファの概
略図である。Conventionally, in this type of semiconductor device, as shown in FIG. 3, pull-up resistors and pull-down resistors are formed as a transistor resistor by forming a drain, a gate and a source separately from the output buffer. The figure is a schematic diagram of an input / output buffer having a pull-down resistor.
上述した従来の半導体装置は、プルアップ抵抗，プルダ
ウン抵抗をトランジスタ抵抗で形成する際出力バッファ
とはまったく別個にドレインゲート，ソースをつくるの
で、その分面積を広く取る必要があった。これはチップ
面積の増大すなわち低歩留りコスト高となる欠点があっ
た。In the above-described conventional semiconductor device, when the pull-up resistor and the pull-down resistor are formed by the transistor resistance, the drain gate and the source are made completely separately from the output buffer, so that it is necessary to take a large area accordingly. This has a drawback that the chip area increases, that is, the yield rate becomes high.
本発明の半導体装置は、トランジスタ抵抗でプルアップ
抵抗，プルダウン抵抗を形成するとき該トランジスタ抵
抗のゲート部は出力バッファの最終段のトランジスタ
の、ゲートのコンタクト部としドレイン部は出力バッフ
ァの最終段のトランジスタの拡散層を用いている。In the semiconductor device of the present invention, when a pull-up resistor and a pull-down resistor are formed by the transistor resistance, the gate portion of the transistor resistance is the contact portion of the transistor of the final stage of the output buffer, and the drain portion is the final stage of the output buffer. The diffusion layer of the transistor is used.
次に本発明について図面を参照して説明する。 Next, the present invention will be described with reference to the drawings.
第１図は本発明を施した、出力バッファの最終段のＮチ
ャネル型トランジスタ部の概略図である。１はゲート，
２はゲートのコンタクト部，３は出力トランジスタのＮ
＋拡散層である。４は２と同様出力バッファの最終段の
トランジスタのゲートのコンタクト部であるがプルダウ
ン抵抗使用時にはゲートコンタクト部そのものがゲート
となる。５はプルダウン抵抗用のＮ＋拡散層である。実
際にプルダウン抵抗として使用するときは、５のＮ＋拡
散層はソース、４のゲートは常にハイレベルとし、３の
Ｎ＋拡散層はドレインとなってＰＡＤにつなげることに
よってプルダウンのトランジスタ抵抗となる。FIG. 1 is a schematic diagram of an N-channel type transistor section at the final stage of an output buffer to which the present invention is applied. 1 is the gate,
2 is a gate contact portion, 3 is an output transistor N
+ It is a diffusion layer. Reference numeral 4 is the contact portion of the gate of the transistor at the final stage of the output buffer as in the case of 2. However, when the pull-down resistor is used, the gate contact portion itself becomes the gate. Reference numeral 5 is an N + diffusion layer for pull-down resistance. When actually used as a pull-down resistor, the N + diffusion layer of 5 is a source, the gate of 4 is always at a high level, and the N + diffusion layer of 3 serves as a drain and is connected to PAD to serve as a pull-down transistor resistance. .
第２図は、第１図に金属配線を施し、プルダウン付入力
バッファとした入出力バッファ部の概略図である。第２
図で斜線部は金属配線を表わしている。FIG. 2 is a schematic diagram of an input / output buffer section which is a pull-down input buffer obtained by applying the metal wiring to FIG. Second
In the figure, the shaded area represents the metal wiring.
６の金属配線は接地電位に接続されており、７はソース
のコンタクトである。８の金属配線はプルダウンのトラ
ンジスタ抵抗を常にＯＮ状態とするためハイクランプさ
れており、９はゲートのコンタクトである。The metal wiring 6 is connected to the ground potential, and 7 is a source contact. The metal wiring 8 is highly clamped so that the pull-down transistor resistance is always in the ON state, and 9 is a gate contact.
１０はドレイン側のコンタクトであるが、プルダウント
ランジスタ以外のところでも数多くコンタクトを取って
いるのはＮ＋拡散層の容量で静電耐圧を向上させるため
である。３のドレインから１１のＰＡＤに金属配線でつ
ながっている。Although 10 is a contact on the drain side, many contacts other than the pull-down transistor are made to improve the electrostatic breakdown voltage by the capacitance of the N + diffusion layer. The drain of 3 is connected to the PAD of 11 by metal wiring.
１２は入力保護の抵抗部であり、１３は入力バッファに
つながる金属配線である。Reference numeral 12 is a resistance portion for input protection, and 13 is a metal wiring connected to the input buffer.
図からわかる様にトランジスタ抵抗の通常の構成法に比
べゲート，ドレインの分がないのでレイアウト面積を小
さくできる。As can be seen from the figure, the layout area can be reduced because there are no gates and drains compared to the usual method of configuring transistor resistance.
以上説明した様に本発明は出力バッファの最終段のトラ
ンジスタのゲートのコンタクト部をプルアップまたはプ
ルダウン抵抗のゲートとし、最終の拡散層を抵抗のドレ
インとすることによってプルアップ抵抗，プルダウン抵
抗の面積を小さくすることができ、チップレイアウト面
積の減少、すなわち高歩留り，低価格の半導体装置を実
現できる効果がある。As described above, according to the present invention, the contact portion of the gate of the transistor at the final stage of the output buffer is the gate of the pull-up or pull-down resistor, and the final diffusion layer is the drain of the resistor. And the chip layout area can be reduced, that is, a semiconductor device with high yield and low cost can be realized.
第１図は本発明を施した出力バッファ部の最終段トラン
ジスタの概略図、第２図は第１図に金属配線を施しプル
ダウン付入力バッファとした一実施例、第３図はプルダ
ウン抵抗を有する入出力バッファ部の概略図。 １……ゲート、２……ゲートのコンタクト部、３……出
力トランジスタのＮ＋拡散層、４……プルダウン抵抗の
ゲート、５……プルダウン抵抗のソース、６……接地電
位の金属配線、７……ソースのコンタクト、８……ハイ
クランプされた金属配線、９……ゲートのコンタクト、
１０……ドレインのコンタクト、１１……ＰＡＤ、１２
……入力保護の抵抗部、１３……入力バッファにつなが
る金属配線、１４……プルアップ抵抗のドレイン部。FIG. 1 is a schematic diagram of a final stage transistor of an output buffer unit according to the present invention, FIG. 2 is an embodiment of a pull-down input buffer with metal wiring shown in FIG. 1, and FIG. 3 has a pull-down resistor. FIG. 3 is a schematic diagram of an input / output buffer unit. 1 ... Gate, 2 ... Gate contact part, 3 ... N + diffusion layer of output transistor, 4 ... Pulldown resistor gate, 5 ... Pulldown resistor source, 6 ... Ground potential metal wiring, 7 ...... Source contact, 8 …… High-clamped metal wiring, 9 …… Gate contact,
10 ... Drain contact, 11 ... PAD, 12
...... Resistance section for input protection, 13 ...... Metal wiring connected to input buffer, 14 ...... Drain section for pull-up resistance.
Claims (1)
スの入出力バッファ部において、プルアップ抵抗または
プルダウン抵抗を形成するトランジスタ抵抗のゲート部
は出力バッファの最終段のトランジスタの、ゲートのコ
ンタクト部とし、ドレイン部は出力バッファの最終段の
トランジスタの拡散層としたことを特徴とする半導体装
置。1. In a complementary MOS gate array master slice input / output buffer section, a gate section of a transistor resistance forming a pull-up resistance or a pull-down resistance is a contact section of a gate of a final stage transistor of an output buffer, A semiconductor device characterized in that the drain portion is a diffusion layer of a final stage transistor of an output buffer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62082302A JPH067574B2 (en) | 1987-04-02 | 1987-04-02 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62082302A JPH067574B2 (en) | 1987-04-02 | 1987-04-02 | Semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS63246845A JPS63246845A (en) | 1988-10-13 |
| JPH067574B2 true JPH067574B2 (en) | 1994-01-26 |
Family
ID=13770755
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP62082302A Expired - Lifetime JPH067574B2 (en) | 1987-04-02 | 1987-04-02 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH067574B2 (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| DE69630864T2 (en) * | 1996-01-31 | 2004-11-04 | Sgs-Thomson Microelectronics S.R.L., Agrate Brianza | Process for the production of non-volatile storage devices with tunnel oxide |
-
1987
- 1987-04-02 JP JP62082302A patent/JPH067574B2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JPS63246845A (en) | 1988-10-13 |
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