JP3123854B2 - Semiconductor device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly to a semiconductor device having CMOS transistors forming an integrated resistance block.

[0002]

2. Description of the Related Art Conventionally, in the above-described CMOS semiconductor device, a resistor block is often used in combination of a P-channel (ch) transistor and an N-channel (ch) transistor.

As an example of a resistance block in such a semiconductor device, a CMO having a base step and an upper step
Referring to FIG. 4 showing the resistance block of the S semiconductor device,
The power supplied to the gate polysilicon 12 of the resistor block 13 (block surrounded by a dotted line) composed of the Pch transistor 14 and the Nch transistor 15 in the base process is the power supply line 16, 17, 18 in the upper process.
Thus, the aluminum wirings formed in different processes such as the second aluminum wiring 21 and the first aluminum wiring 22 are connected to each other, and the other wirings 23 are considered.
Power is supplied.

Here, a power supply line 16 is a 5V VDD voltage line, a power supply line 17 is a 3V VDD voltage line,
The power supply line 18 is a ground (GND) potential line.

The first and second aluminum wirings 22 and 2
1, the gate polysilicon 12 is electrically connected by a through hole 39. In the resistance block 13, a resistance input wiring 19 is introduced, and a resistance output wiring 20 is led out. The above components are arranged at corners on the chip B.

[0006]

The gate polysilicon 12 of the resistance block 13 of the conventional CMOS semiconductor device is used.
Is supplied to the required power supply lines 16, 1
Power is drawn from the aluminum wirings 21 and 22 from the wirings 7 and 18.

However, the aluminum wirings 21 and 22
Is crossed with another signal wiring 23, the aluminum wiring formed in another process such as the first aluminum wiring 22 or the second aluminum wiring 21 is connected in consideration of the signal wiring 23. In addition, since the power supply is drawn while preventing a short circuit with the other signal wiring 23, there is a problem that when evaluation after design or correction of a layout pattern is required, the number of steps required for correction is increased.

Further, since the aluminum wirings are connected to each other, a separate wiring area is required, and the area of the chip B is increased. Therefore, there is also a problem that the manufacturing cost is increased.

Accordingly, an object of the present invention is to solve the above problems and reduce the number of steps required for correcting a layout pattern and to reduce the chip area.

[0010]

A semiconductor device according to the present invention comprises a P-channel transistor and an N-channel transistor in a semiconductor device having a base region forming a transistor and an upper region forming a wiring. The potential supply section of the gate layer of the
It is characterized in that it extends until it crosses a plurality of different power supply lines.

By doing so, in a layout modification such as a specification change, the contact at the intersection of the power supply line and the gate polysilicon can be simply moved.
Power can be easily taken from other power supply lines.

[0012]

FIG. 1 shows a semiconductor device according to a first embodiment of the present invention. In this embodiment, a resistance block 2 is constructed by using a Pch transistor 3 in a base step and an Nch transistor 4 in a base step. The gate polysilicon 1 in the base step of the resistor block 2 is extended in advance until it crosses the power supply lines 5, 6, 7 in the upper step.

Referring to FIG. 2, which is a cross-sectional view taken along the line AA 'of FIG. 1, the semiconductor substrate 35 has a gate polysilicon 1 in an underlying process in advance under power lines 5, 6, 7 in an upper process. , The contact 10 is connected to the power supply lines 5, 6,
The power can be easily taken by simply moving it to any one of 7.

By doing so, power can be directly supplied without considering the input line 8 of the resistor block 2 in the upper process or the signal wiring 11 of another block in the upper process, and the power supply can be increased from 5V. When the layout pattern is corrected to 3 V, the correction can be easily performed only by moving the contact 10, and the man-hour for the correction is reduced as compared with the related art, and the chip A
Area also becomes smaller.

Referring to FIG. 3, which is a second embodiment of the present invention, this embodiment shows that a gate polysilicon 26 in a base step of a resistance block 29 in an internal region of a CMOS semiconductor device is provided.
Is conventionally controlled by the ON / OFF control signal wirings 30 and 31 of the transistor in the upper process, but the gate polysilicon 26 in the lower process is connected to the power supply line 2 in the upper process.
4 and 25, so that the Pch / Nch transistor 2
7, 28 can be forcibly fixed to ON.

That is, the gate polysilicon 2 in the underlying process
ON / OFF of the upper process connected to the potential supply part of No. 6
The control signal wirings 30 and 31 or the power supply line 24 in the upper process
By simply moving the contact 34 to either one of the 25, the ON / OFF of the resistor block 29 can be controlled or fixed to ON without considering other signal wirings 40 in the upper ground process.

[0017]

As described above, according to the semiconductor device of the present invention, instead of connecting the aluminum wiring formed in another process in consideration of other signal wiring from the gate layer of the resistance block to the power supply line, And multiple gate layers
Since then extended to different power supply lines, the evaluation and specification changes, after design, only easily moved con data transfected when correction of the layout pattern is required, because the necessary power can be supplied, modified Man-hours for
Further, since aluminum wiring is not used from the gate layer of the resistor block to the power supply line, there is no wiring area for the aluminum wiring, and the chip area is reduced, so that the cost for manufacturing the chip is reduced.

[Brief description of the drawings]

FIG. 1 is a layout diagram of a first embodiment of the present invention.

FIG. 2 is a cross-sectional view taken along line AA 'of FIG.

FIG. 3 is a layout diagram of a second embodiment of the present invention.

FIG. 4 is a layout diagram of a conventional resistance block.

[Explanation of symbols]

A, B Semiconductor chip 1, 12, 26 Gate polysilicon 2, 13, 29 Resistor block 3, 14, 27 P-channel (ch) transistor 4, 15, 28 N-channel (ch) transistor 5, 16, 255 Power supply of 5.5V Line 6,173V power supply line 7,18,24 Ground potential line 8,19,32 Resistance input wiring 9,20,33 Resistance output wiring 10 Contact 11,23,40 Other signal wiring 21,22 Aluminum Wiring 30 ON / OFF control signal line of Pch transistor 31 ON / OFF control signal line of Nch transistor 34 Contact 35 Semiconductor substrate 36, 37 Oxide film 38 Protective film 39 Through hole

Continuation of the front page (58) Field surveyed (Int.Cl. ⁷ , DB name) H01L 27/04 H01L 21/82 H01L 21/822

Claims (2)

(57) [Claims] 1. A semiconductor device having a base region forming a transistor and an upper region forming a wiring,
The semiconductor device is characterized in that is extended until it intersects the potential supply portion of the gate layer of the configured resistors blocks the channel transistor and N-channel transistors under different supply lines of the upper base region. 2. The semiconductor device according to claim 1, wherein the gate layer is made of polysilicon.