JPH0673215B2 - Disc motor control circuit - Google Patents

Description

The present invention relates to a disc motor control circuit of a CD (compact disc) reproducing device.

(B) Conventional technology In the CD player, the disc motor is controlled so that the linear velocity is constant for the disc rotation. for that reason,
Based on the EFM signal extracted from the disk, the sync signal created by the PLL circuit is divided by the divider circuit, and the divided output obtained as a result and the reference clock pulse created by the crystal oscillator circuit are divided. The phase difference from the frequency-divided output thus obtained is detected, and the disk motor is servo-controlled so that the phase difference disappears. However, in the PLL circuit, the range of synchronizing the sync signal created from the EFM signal with the EFM signal is ±
Since it is only about 5%, it is necessary to adjust the linear velocity to this accuracy. This is called a rough servo.

Therefore, conventionally, it was detected whether the rotation of the disk is in a stable state or in an unstable state, and if it is in an unstable state, the phase control is switched to the direct control so that the stable state can be immediately approached. There is. In addition, in order to obtain information indicating whether the rotation speed is fast or slow, the longest period of EFM signal (11-bit continuous period) is detected, and if this longest period is longer than the reference period created by the reference clock pulse, Determines that the rotation speed is slow, and if the rotation speed is short, the rotation speed is fast.

Regarding the above-mentioned disc motor control circuit, see Japanese Patent Laid-Open No. 60-
It is described in detail in Japanese Patent No. 85465.

(C) Problems to be Solved by the Invention However, in the circuit that detects the longest period of the EFM signal as in the conventional art, for example, when a dropout occurs in the EFM signal due to a track jump or a scratch, The detected longest cycle becomes longer than the reference cycle, and although the normal rotation is performed, it is determined that the rotation is slow and the rotation speed is controlled to increase. Further, since the longest cycle is 11 bits, there is a drawback that the number of bits constituting the counter for detecting this is increased and the number of elements is increased.

(D) Means for Solving Problems The present invention has been made in view of the above-mentioned points.
The shift register for inputting the M signal based on the reference clock pulse and the ratio of the shortest period (3-bit continuous period) of the EFM signal to the reference period determined by the reference clock pulse depending on the contents of the shift register A discriminating circuit for discriminating, first and second flip-flops which are set and reset according to the result of the discriminating circuit, and which generate a signal instructing acceleration of the rotation speed of the disk motor and a signal instructing deceleration, and the phase A rotation speed detection circuit for detecting that the disk motor is rotating outside the servo range of the rotation speed of the disk motor by comparison, and a rotation speed of the disk motor based on the result of the phase comparison by the detection output of the rotation speed detection circuit. Signal for instructing acceleration and deceleration signal and outputs of the first and second flip-flops A disc based on the discrimination of the shortest period of the EFM signal when the signal is out of the control range of the phase comparison, provided with a selection circuit for switching and outputting a signal instructing acceleration of the rotation speed of the disk motor and a signal instructing deceleration It controls the motor.

(E) Operation According to the above-mentioned means, when it is detected that the rotation speed of the disk motor is out of the servo range of the phase control, the servo is performed based on the determination of the shortest period of the EFM signal. That is,
The shortest cycle of the EFM signal is detected and compared with the reference cycle created from the reference clock pulse to determine whether the rotation of the disk motor is fast or slow. Therefore, even if the EFM signal is dropped out due to a track jump or a scratch, the period is not recognized as the shortest period, so that misjudgment is prevented.

(F) Embodiment FIG. 1 is a block diagram showing an embodiment of the present invention. The shift register (1) sequentially inputs the EFM signal based on the 8.64 MHz reference clock pulse φ _8M generated by the crystal oscillation circuit (not shown), and outputs the 2-bit output E of the preceding stage.
-A signal change of the EFM signal, that is, a rising edge and a falling edge of the EFM signal is detected by the OR output, a pulse for one cycle of the reference clock pulse _φ8M is generated when the EFM signal changes, and the pulse is generated in the third stage. The subsequent 7 bits are sequentially shifted. The discrimination circuit (2) is a shift register (1).
Input the 7-bit output from the 3rd stage onward, and depending on the bit distance that is "1" in the 7-bit, the shortest period of the EFM signal is 2.0T, 2.5T, 3.0T, or 3.5T or more. It is a decoder that distinguishes whether or not there is. Here, T is a 1-bit standard period of the EFM signal based on the reference clock pulse φ _8M . So if the disc is spinning fast
It is determined to be 2.5T or 2.0T, 3.0T if it is rotating at standard speed, and 3.5T or more if it is rotating slowly. Discrimination output D _{2.0T of} this discrimination circuit (2),
D _2.5T, D _3.0T and D _3.5T is a shift register (1)
Since the EFM signal is sequentially shifted, it is output every time the shortest period thereof is detected and applied to the hold circuit (3). The hold circuit (3) outputs D _2.5T , D _3.0T and D
R-SFF set by _3.5T (4) (5) (6)
And half the period of 32 frames (the period when the signal 16FL is "1")
A counter (7) that generates an output of "1" when a predetermined number of "15" is counted for 2.0T.
The R-SFF (4) (5) (6) and the counter (7) are reset by the pulse 1 / 32FL output once every 32 frames from the frame counter (8). That is, the hold circuit (3) is reset once every 32 frames and accumulates outputs D _2.0T , D _2.5T , D _3.0T and D _3.5T for the following 32 frames. Further, the frame counter (8) is a frame frequency obtained by _dividing the reference clock pulse φ _8M.
A 5-bit counter for counting the pulses phi _FLM of 7.35 KHz, and outputs a pulse 1 / 32FL when the pulse phi _FLM to 21 counted, outputs a pulse ENA when counted 17 bottom preference circuit (9) Apply to. The bottom priority circuit (9) prioritizes the output of the counter (7), the output Q of R-SFF (4), the output Q of R-SFF (5), and the output of R-SFF (6). It is a gate circuit that outputs based on the pulse ENA, and the output 2.0T is the first FF, that is, R-SFF.
Applied to the set input S of (10), the output 3.5T is
FF, that is, applied to the set input S of R-SFF (11), and outputs 2.0T and 2.5T are R- through the OR gate (12).
Applied to reset input R of SFF (11), output 3.0T and
3.5T is applied to the reset input R of R-SFF (10) through the OR gate (13). Therefore, R-SFF (10) is EFM
Set when the shortest period of the signal is determined to be 2.0T, the signal (-) for decelerating the disk motor is output, and then
It is reset when 3.0T or 3.5T is discriminated by deceleration of the disk motor. On the other hand, R-SFF (11) is E
It is set when the shortest period of the FM signal is 3.5T or more, and outputs the signal (+) that accelerates the disk motor, and is reset when 2.5T or 2.0T is judged by the acceleration of the disk motor.

The rotation speed detection circuit (15) is R-SFF (10) or R
One of SFF (11) is set, and the number of coincidences between the frame sync signal of the EFM signal and the standard frame sync signal created based on the reference clock pulse φ _8M is 32.
The fact that the predetermined number of "8" has not been reached between frames is detected as 32 consecutive times, and it is determined that the disk motor is out of the servo range for phase comparison due to this detection. And select the detection signal SEL (14)
Apply to. Therefore, the rotation speed detection circuit (15) is
-The output of the NOR gate (17) to which the outputs of SFF (10) and (11) are applied is reset input R via the OR gate (18).
The counter SYEQ, which indicates the coincidence between the frame sync signal of the EFM signal and the standard frame sync signal, is applied to the counter (19) that is applied to the counter (19) to which the signal 1 / 32FL from the frame counter (8) is applied It consists of a counter (20) applied to the input CL and the signal 1/32 FL applied to the reset input R. The counter (19) sets the detection signal SEL to "1" when the count value becomes "32", and the counter (20) counters via the OR gate (18) when the count value becomes "8". Reset (19). Therefore, during 32 frames the signal
SYEQ does not reach 8 and R-SFF (10) or (1
If one is set, the counter (1
9) is not reset and continues counting the signal 1 / 32FL,
The detection signal SEL becomes "1" when 32 states are continuous. The selection circuit (14) is controlled by the detection signal SEL from the rotation speed detection circuit (15), and the output (-) of the R-SFF (10) instructing deceleration of the rotation speed of the disk motor.
And a control signal PH that instructs deceleration from the phase control circuit (16)
(-) Is switched to output as a control signal CLV (-) that controls the deceleration of the rotation speed of the disk motor, and at the same time,
R-SFF (1
The output (+) of 1) and the control signal PH (+) instructing the acceleration from the phase control circuit (16) are switched and output as the control signal CLV (+) which controls the acceleration of the rotation speed of the disk motor. Therefore, when the detection signal SEL becomes "1", the selection circuit (14) outputs the outputs (-) and (+) of the R-SFFs (10) and (11) to the control signals CLV (-) and CLV (+). Is output to the drive circuit of the disk motor.

Next, the rough servo operation of the disk motor in the circuit shown in FIG. 1 will be described with reference to FIG.

First, in Fig. 2, the shortest period of the EFM signal is judged to be 2.0T, 1.75T to 2.25T, and 2.5T is 2.25T to 2.75T, 3.0T. 2.75T
From 3. to 3.25T, it is more than 3.25T that is discriminated as 3.5T. Now, when the rotation speed of the disk is significantly slow, the shortest period is determined to be 3.5T or more from the EFM signal shifted to the shift register (1), and R-SFF (11) is set. Also, in this case, the signal SYEQ hardly occurs, so the rotation speed detection circuit (15)
Set L to “1”. Therefore, the control signal CLV (+) has R-SF
The output “1” of F (11) appears, and the control signal CLV (-) is R-
The output “0” of SFF (10) appears. As a result, the disc motor is controlled to be accelerated, and the shortest period of the EFM signal extracted from the disc is gradually shortened. Then, beyond the determination range of 3.5T, the output D _3.0T is generated to fall within the determination range of 3.0T from the determining circuit (2), this 3.0T
R-SFF (11) is not reset depending on the result of the determination, and the acceleration state of the disk motor continues. Then, when the shortest period falls within the discrimination range of 2.5T, the discrimination circuit (2) outputs D
_2.5T occurs, and R-SFF (1
Since 1) is reset, the control signal CLV (+) becomes "0" and the disk motor acceleration is stopped. At this time, R
-SFF (10) and (11) outputs are both "0", so NOR
The output of the gate (17) becomes "1", and the counter (19) of the rotation speed detection circuit (15) is reset. Therefore, since the detection signal SEL becomes "0", the selection circuit (14)
The control signal PH (-) of the phase control circuit (16) is switched to the control signal CLV (-) from the output (-) of FF (10) and at the same time, the phase is output from the output (+) of R-SFF (11). Control circuit (1
6) Control signal PH (+) is switched to control signal CLV (+) and output. As a result, the rotation of the disk motor is phase controlled.

By such rough servo operation, even when the rotation speed of the disk motor changes significantly, it is possible to quickly pull in the controllable range by phase comparison. Further, even if the EFM signal dropout occurs due to a track jump or a scratch during the rough servo operation, the period is not discriminated by the discriminating circuit (2) as the shortest period, so the disc motor It is possible to prevent a malfunction that is recognized as a slow rotation.

(G) Effect of the Invention As described above, according to the present invention, the reliability of the control circuit of the disk motor of the CD reproducing device is improved, and the number of constituent elements when the control circuit is integrated is reduced. . Furthermore,
Since it is possible to determine whether or not to perform rough servo by the control circuit itself, it is not necessary to make the determination by the microcomputer as in the conventional case, and there is an advantage that the load on the microcomputer can be reduced.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing an embodiment of the present invention, and FIG. 2 is a diagram showing the operation of the circuit shown in FIG. (1) …… Shift register, (2) …… Discrimination circuit,
(3) …… Hold circuit, (8) …… Frame counter, (9) …… Bottom priority circuit, (10) (11) …… R-
SFF, (14) …… Selection circuit, (15) …… Rotation speed detection circuit, (16) …… Phase control circuit.

Front page continuation (72) Inventor Kazuhiro Kimura 180 Sakata, Oizumi-cho, Gunma-gun Oozumi-cho, Tokyo Sanyo Electric Co., Ltd. (72) Inventor Hiroyuki Arai 180 Sakata, Oizumi-machi, Gunma-gun Sakai, Tokyo In the company

Claims (1)

[Claims] 1. A disk motor control circuit for controlling the rotation speed of a disk motor by phase comparison between a frequency-divided output of a sync signal and a frequency-divided output of a reference clock pulse generated based on an EFM signal. A shift register for inputting a signal based on a reference clock pulse, and the ratio of the shortest period (3-bit continuous period) of the EFM signal to the reference period determined by the reference clock pulse according to the contents of the shift register A discriminating circuit, and first and second flip-flops that are set and reset according to the discriminating result of the discriminating circuit, and that generate a signal instructing acceleration and a signal instructing deceleration of the rotation speed of the disk motor; The rotation speed detection that detects that the disk motor is rotating outside the servo range of the rotation speed of the disk motor An output circuit, a signal for instructing acceleration and deceleration of the rotational speed of the disk motor based on the result of the phase comparison based on the detection output of the rotational speed detection circuit, and an output of the first and second flip-flops. A disc motor based on the discrimination of the shortest period of the EFM signal when the control circuit for phase comparison is provided with a selection circuit for switching and outputting a signal instructing acceleration and deceleration of the rotation speed of the disc motor. A disk motor control circuit characterized by controlling