JPH0673216B2 - Disc motor control circuit - Google Patents

Description

The present invention relates to a disc motor control circuit of a CD (compact disc) reproducing device.

(B) Conventional technology In the CD player, the disc motor is controlled so that the linear velocity is constant for the disc rotation. for that reason,
Based on the EFM signal extracted from the disk, the sync signal created by the PLL circuit is divided by the divider circuit, and the divided output obtained as a result and the reference clock pulse created by the crystal oscillator circuit are divided. The phase difference from the frequency-divided output thus obtained is detected, and the disk motor is servo-controlled so that the phase difference disappears. However, in the PLL circuit, the range of synchronizing the sync signal created from the EFM signal with the EFM signal is ±
Since there are only about 5, it is necessary to match the linear velocity to this accuracy. This is called a rough servo.

Therefore, conventionally, it was detected whether the rotation of the disk is in a stable state or in an unstable state, and if it is in an unstable state, the phase control is switched to the direct control so that the stable state can be immediately approached. There is. In addition, in order to obtain information indicating whether the rotation speed is fast or slow, the longest period of EFM signal (11-bit continuous period) is detected, and if this longest period is longer than the reference period created by the reference clock pulse, Determines that the rotation speed is slow, and if the rotation speed is short, the rotation speed is fast.

Regarding the above-mentioned disc motor control circuit, see Japanese Patent Laid-Open No. 60-
It is described in detail in Japanese Patent No. 85465.

(C) Problems to be solved by the invention However, in a circuit that detects the longest period of the EFM signal as in the past, for example, when a dropout occurs in the EFM signal due to a track jump or a flaw, it is detected. The determined maximum cycle becomes longer than the reference cycle, and it is determined that the rotation speed is slow despite normal rotation, and the rotation speed is controlled to increase. Further, even if the EFM signal disappears due to some trouble, the rough servo determines that the rotation speed is slow, so there is a risk of falling into high-speed rotation in the positive direction.

On the other hand, when the disk motor is stopped or nearly stopped due to an external factor (for example, when the disk is forcibly stopped by a foreign object), the signal from the disk disappears, so the slice circuit for extracting the EFM signal The input fluctuates near the slice level, and high frequency components are generated in the output line of the EFM signal. As a result, it is determined that the longest cycle is shorter than the reference cycle, and as a result, the rough servo acts in the direction of decelerating the disk motor, and there is a risk that the disk motor may fall in high speed reverse rotation.

(D) Means for Solving Problems The present invention has been made in view of the above-mentioned points.
An EFM presence / absence detection circuit for detecting the presence / absence of an M signal, a gate circuit for inhibiting phase servo and rough servo when a detection signal without the EFM signal is generated from the detection circuit, and a disk at a predetermined interval when the detection signal without the EFM signal is generated. By providing an intermittent acceleration circuit that outputs an acceleration signal of the motor and a counter that counts while the rough servo is generating the deceleration signal when selecting the rough servo and prohibits the generation of the deceleration signal when counting a predetermined number of disks, This is to prevent the motor from falling in the forward high speed rotation or the reverse high speed rotation.

(E) Action According to the above-mentioned means, when a dropout occurs in the EFM signal due to a track jump or a scratch, or when the EFM signal disappears due to some trouble, the EFM signal is lost.
A detection signal without an EFM signal is generated from the signal presence / absence detection circuit, the gate circuit is controlled by the signal, and the signals from the phase servo and rough servo are cut off. This causes the disk motor to freely rotate and slowly move toward the deceleration direction. When the detection signal without the EFM signal is generated, the intermittent acceleration circuit accelerates the disk motor at a predetermined interval in the forward rotation direction to drive the disk motor which may be stopped. Furthermore, in the state where the rough servo generating the acceleration signal is selected, if the deceleration signal is still generated even after the lapse of a predetermined period based on the counter,
It is determined that the disk motor has not been decelerated, and the deceleration signal is prohibited. Due to these actions, abnormal rotation of the disk motor is prevented.

(F) Embodiment FIG. 1 is a circuit diagram showing an embodiment of the present invention. The phase servo circuit is composed of frequency dividing circuits (1) and (2) and a phase comparison circuit (3). The frequency divider circuit (1) is a synchronization pulse P generated by a PLL circuit (not shown) based on the EFM signal.
It is a circuit that divides LCK (4.32MHz) by 588 (one frame), and the dividing circuit (2) is a clock pulse φ _4M (4.32MHz) created by a crystal oscillation circuit (not shown). Is similarly divided by 588, and the phase difference between the divided outputs of the dividing circuits (1) and (2) is detected by the phase comparison circuit (3), and the output of the dividing circuit (1) is detected. If the phase is delayed, the acceleration signal PH (+) “H” is output, if it is advanced, the deceleration signal PH (−) “H” is output, and if they are substantially the same, Both are “L”.

On the other hand, the rough servo circuit is composed of a shift register (4), a decoder (5), a hold circuit (6), a bottom priority circuit (7) and a control signal generation circuit (8). The shift register (4) sequentially inputs the EFM signal according to the 8.64 MHz reference clock pulse φ _8M created by the crystal oscillation circuit. Input to shift register (4) sequentially
The data pattern of the EFM signal is such that the shortest period of the EFM signal is 2.0T, 2.5T, 3.0T, and 3.5 at the decoder (5).
It is determined which one of T. Here, T is the period of 1 bit of the EFM signal based on the reference clock pulse φ _8M . Decoder output of the decoder (5) 2.0T, 2.5T, 3.0T, 3.
5T is stored and held in the hold circuit (6),
It is applied to the photon priority circuit (7). This hold circuit (6) is a 7.35 KHz clock pulse φ _FLM with a period of one frame created based on the reference clock pulse φ _8M.
From the frame counter (9) that counts 32 frames
It is cleared by the pulse 1 / 32FL which is output once every 32 frames. That is, the decoding result of the shortest cycle between 32 frames is held in the hold circuit (6). The bottom priority circuit (7) outputs the pulse EN from the frame counter (9) every 32 frames at a timing different from the pulse 1 / 32FL.
A receives the signal from the hold circuit (6) and outputs the signal with the shortest period to the control signal generation circuit (8).
The control signal generation circuit (8) sets the acceleration signal RO (+) to "H" when the output of the bottom priority circuit (7) is 3.5T, and then outputs the acceleration signal RO (+) when the output becomes 2.5T. "L",
On the other hand, when the output is 2.0T, the deceleration signal RO (-) is "H", and when the output is 3.0T, the deceleration signal RO (-) is "L".

Control circuit PH (+) and PH (-) of the above phase servo circuit
And the control signals RO (+) and RO (-) of the rough servo circuit are
Both are applied to the selection circuit (10), and one of them is sent to the drive circuit of the disk motor as the control signals CLV (+) and CLV (-) by the switching signal SEL. This switching signal
The SEL is created by counters (11) and (12) that detect the rotation state of the disk motor. Counters (11)
Is reset by pulse 1 / 32FL, and when the number of pulse SYEQ that is output each time the frame sync signal of the EFM signal and the standard frame sync signal generated from the reference clock pulse φ _8M match is counted, OR gate (13)
Reset the counter (12) via. Further, the counter (12) switches the switching signal SE when 32 pulses 1 / 32FL are counted.
This is a counter that sets L to "H", and it is reset by the output of the counter (11) and control signal RO (+) or RO.
When either one of (-) is "H", it is reset by the output of NOR gate (14). That is, if the disk is rotating within the control range of the phase servo circuit, a pulse SYEQ is generated while the counter (11) is reset every 32 frames.
Since 8 or more are always generated, the output from the counter (11) is generated, and since the control signals RO (+) and RO (-) are both "L", the output of the NOR gate (14) is " H ". Therefore, the counter (12) is reset and the switching signal
Since SEL becomes “L”, the selection circuit (10) outputs control signal PH
Selectively outputs (+) and PH (-). On the other hand, when the disk motor is rotating outside the control range of the phase servo circuit, either one of the control signals RO (+) or RO (-) becomes "H", and the pulse SYEQ changes during 32 frames. Since the number of counters does not reach eight, the reset of the counter (12) is released. When 32 frames in this state continue 32 times, the switching signal SEL from the counter (12) becomes “H”, so that the selection circuit (10) controls the rough servo circuit control signals RO (+) and RO (RO).
Select (-) to output.

Further, the EFM signal presence / absence detection circuit (15) inputs the EFM signal, and when the rising or falling of the EFM signal does not occur within the period of the pulse φ _M , the detection output NOE is set as “no EFM signal”. L ". This detection output NOE
Is applied to the reset input R of the counter (17) via the OR gate (16) and to the reset input R of the R-SFF (18) and the NOR gate (19). R-SFF (1
The output of 8) is the switching signal SEL and its inverted signal ▲ ▼
Is applied to the applied AND gates (20) and (21) and is also applied to the NAND gate (23) via the inverter (22). On the other hand, the counter (17) forms an intermittent accelerating circuit together with the counter (12). The 4-bit output of the counter (12) and the 2-bit output of the counter (17) are applied to the NAND gate (24), and the NAND gate (24) is applied. The output ITV of (24) is applied to the NOR gate (19) and also to the NAND gate (23) via the inverter (25). This NAND gate (2
4) Output ITV, counter (12) (17) 32 frames ×
8 frames during counting 256, that is, 1 in about 1 second
It becomes “L” for 17.4 ms.

Here, with reference to FIG. 2, the operation when the absence of the EFM signal and the intermittent acceleration operation will be described. When the disk motor is rotating within the phase servo control range, the detection output NOE of the EFM signal presence / absence detection circuit (15) is "H" and the switching signal SEL is "L", so the selection circuit (10)
Control signals PH (+) and PH of the phase comparison circuit (3) from the NAND gates (26) and (27) to the control signals CLV (+) and CLV (-) via the NOR gates (28) and (29). (-) Appears. If the rotation of the disk motor is stopped or nearly stopped due to some abnormality, the control signal RO (+) becomes "H" while the rotation speed before that is decreased, and the counters (11) and (12 ), The switching signal SE
Control signal CLV (+) and CLV (-) because L becomes "H"
Is the control signal RO (+) “H” and RO from the rough servo circuit.
(−) “L” is NAND gate (30), NOR gate (28) and N
Appears through AND gate (31) and NOR gate (29).
After that, when the EFM signal is no longer detected, the detection output NOE becomes "L" and the counting by the counter (17) is started. Then, when the output ITV of the NAND gate (24) becomes "L", RS
FF (18) is set and output Q becomes "0", so AND
Switching signals SEL and ▲ at the gates (20) and (21)
▼ is cut off, and control signals PH (+) and PH (-) and control signal RO are applied to the NAND gates (26) (27) (30) (31).
(+) And RO (-) are cut off. At this time, since the output ITV inversion signal ▲ ▼ = "H" and the inversion signal Q = "H" of the output of the R-SFF (18) are applied to the NAND gate (23), the control signal CLV (+) Becomes "H" and becomes an acceleration signal. That is, the output ITV is "L" at an interval of 17.4 ms in about 1 second.
Each time, the control signal CLV (+) becomes "H" and intermittent acceleration is performed. Due to this intermittent acceleration, the disk motor that was stopped or nearly stopped started to rotate in the forward direction, and when the EFM signal was generated, the detection output NOE became "H", so the R-SFF (18) and counter (17) is reset, and the control signal RO (+) “H” and RO are set by the switching signal SEL.
(-) "L" is output as the control signals CLV (+) and CLV (-), and the rough servo state is set. Furthermore, when the rotation of the disk motor approaches normal and enters the phase servo control range, the switching signal SEL becomes "L", and the control signals PH (+) and PH
(-) Is output as the control signals CLV (+) and CLV (-). In this way, it is possible to deal with the case where the disk motor is stopped or is in a state close to stop.

Further, in the circuit shown in FIG. 1, a counter (32) for preventing high speed reverse rotation is provided. This counter (32) consists of 8 bits, and the output of the 8th bit is connected to the AND gate (3
4) is applied. Further, the control signal RO (−), the switching signal SEL and the pulse 1 / 32FL are applied to the AND gate (34). In addition, the reset input R of the counter (32)
AN with switching signal ▲ ▼ and control signal PH (+) applied
The output of the D gate (35) and the control signal RO (+) are applied via the OR gate (36). That is, the counter (32)
When the control signal RO (-) becomes the deceleration signal of "H", the switching signal SEL is "H" and the rough servo circuit is selected, the pulse 1 / 32FL is counted and the counted value is "128". Signal DES inhibits the deceleration signal from appearing in control signal CLV (-), and when control signal RO (+) becomes "H", and when the phase servo circuit is selected and control signal PH (+) )
Is reset when becomes "H".

Therefore, the operation of preventing the high speed reverse rotation will be described with reference to FIG. If a high frequency component occurs in the EFM signal input when the disk motor stops due to some trouble,
Since the decoder (5) of the rough servo circuit determines that the shortest period is 2.0T, the control signal RO (-) becomes "H" and the switching signal also becomes "H". Therefore, the rough servo circuit is selected and the deceleration signal is applied to the disk motor, and the disk motor is accelerated in the opposite direction as it is. At this time, the counter (32) continues counting pulses 1 / 32FL, and when counting 128 pulses, sets the signal DES to "L". When the signal DES becomes “L”, the NAND gate (26) (3
In 0), the control signal RO (-) and the control signal PH (-) are cut off, so the control signal CLV (-) becomes "L", the deceleration operation is released, and the rotational drive in the reverse direction is prohibited. It Then, the disk motor rotates in the forward direction, and the control signal RO
The counter (32) is reset when (+) becomes "H" or when the normal rotation is performed and the switching signal SEL becomes "L" and the control signal PH (+) becomes "H". On the other hand, when the control signal RO (-) becomes "H" and the switching signal SEL becomes "H" during normal rotation, the counter (32) counts similarly. , Control signal RO (+) during 128 × 32 frames until signal DES is output.
Becomes "H" or the switching signal SEL becomes "L" and the control signal PH (+) becomes "H", so that the counter (32) is reset and the signal DES is not generated. Such an operation prevents reverse acceleration of the disk motor.

(G) Effect of the Invention As described above, according to the present invention, it is possible to prevent abnormal rotation of the disk motor, and to automatically stabilize the disk motor against abnormalities.
CLV servo can be realized. Further, in the case where the disk motor control circuit is integrated into a circuit, conventionally, abnormality detection was detected by a microcomputer and a command is given to the integrated circuit. However, according to the present invention, the load is imposed on the microcomputer because it is performed by the integrated circuit itself. Has the advantage of being reduced.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing an embodiment of the present invention, FIG. 2 and FIG.
The figure is a timing diagram illustrating the operation of the embodiment shown in FIG. (1) (2) ... frequency divider circuit, (3) ... phase comparison circuit,
(4) …… Shift register, (5) …… Decoder,
(6) …… Hold circuit, (7) …… Bottom priority circuit,
(8) …… Control signal generation circuit, (10) …… Selection circuit,
(9) …… Frame counter, (11) (12) (17) (3
2) …… Counter, (15) …… EFM signal presence / absence detection circuit.

 ─────────────────────────────────────────────────── --- Continuation of the front page (72) Inventor Kazuhiro Kimura 180 Sakata, Oizumi-cho, Gunma-gun Ojizumi-cho, Higashi Kyoyo Electric Co., Ltd. Sanyo Electric Co., Ltd.

Claims (1)

[Claims] 1. A phase servo for controlling the rotation of a disk motor by phase comparison between a frequency-divided output of a synchronizing signal generated based on an EFM signal and a frequency-divided output of a reference clock pulse, and a shortest period of the EFM signal ( In the disk motor control circuit for selecting the rough servo for controlling the rotation of the disk motor by comparing the three-bit continuous period) with the reference cycle,
An EFM presence / absence detection circuit that detects the presence or absence of an EFM signal, a gate circuit that inhibits the phase servo and rough servo when the detection signal without the EFM signal is generated from the detection circuit, and a predetermined interval when the detection signal without the EFM signal is generated. , An intermittent acceleration circuit that outputs an acceleration signal of the disk motor, and a counter that counts while the rough servo is generating a deceleration signal when selecting the rough servo and that prohibits the generation of the deceleration signal when counting a predetermined number. A disk motor control circuit, which is provided and protects the rotation of the disk motor.